1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Clause 45 PHY support 4 */ 5 #include <linux/ethtool.h> 6 #include <linux/export.h> 7 #include <linux/mdio.h> 8 #include <linux/mii.h> 9 #include <linux/phy.h> 10 11 /** 12 * genphy_c45_setup_forced - configures a forced speed 13 * @phydev: target phy_device struct 14 */ 15 int genphy_c45_pma_setup_forced(struct phy_device *phydev) 16 { 17 int ctrl1, ctrl2, ret; 18 19 /* Half duplex is not supported */ 20 if (phydev->duplex != DUPLEX_FULL) 21 return -EINVAL; 22 23 ctrl1 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1); 24 if (ctrl1 < 0) 25 return ctrl1; 26 27 ctrl2 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL2); 28 if (ctrl2 < 0) 29 return ctrl2; 30 31 ctrl1 &= ~MDIO_CTRL1_SPEEDSEL; 32 /* 33 * PMA/PMD type selection is 1.7.5:0 not 1.7.3:0. See 45.2.1.6.1 34 * in 802.3-2012 and 802.3-2015. 35 */ 36 ctrl2 &= ~(MDIO_PMA_CTRL2_TYPE | 0x30); 37 38 switch (phydev->speed) { 39 case SPEED_10: 40 ctrl2 |= MDIO_PMA_CTRL2_10BT; 41 break; 42 case SPEED_100: 43 ctrl1 |= MDIO_PMA_CTRL1_SPEED100; 44 ctrl2 |= MDIO_PMA_CTRL2_100BTX; 45 break; 46 case SPEED_1000: 47 ctrl1 |= MDIO_PMA_CTRL1_SPEED1000; 48 /* Assume 1000base-T */ 49 ctrl2 |= MDIO_PMA_CTRL2_1000BT; 50 break; 51 case SPEED_2500: 52 ctrl1 |= MDIO_CTRL1_SPEED2_5G; 53 /* Assume 2.5Gbase-T */ 54 ctrl2 |= MDIO_PMA_CTRL2_2_5GBT; 55 break; 56 case SPEED_5000: 57 ctrl1 |= MDIO_CTRL1_SPEED5G; 58 /* Assume 5Gbase-T */ 59 ctrl2 |= MDIO_PMA_CTRL2_5GBT; 60 break; 61 case SPEED_10000: 62 ctrl1 |= MDIO_CTRL1_SPEED10G; 63 /* Assume 10Gbase-T */ 64 ctrl2 |= MDIO_PMA_CTRL2_10GBT; 65 break; 66 default: 67 return -EINVAL; 68 } 69 70 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, ctrl1); 71 if (ret < 0) 72 return ret; 73 74 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL2, ctrl2); 75 if (ret < 0) 76 return ret; 77 78 return genphy_c45_an_disable_aneg(phydev); 79 } 80 EXPORT_SYMBOL_GPL(genphy_c45_pma_setup_forced); 81 82 /** 83 * genphy_c45_an_config_aneg - configure advertisement registers 84 * @phydev: target phy_device struct 85 * 86 * Configure advertisement registers based on modes set in phydev->advertising 87 * 88 * Returns negative errno code on failure, 0 if advertisement didn't change, 89 * or 1 if advertised modes changed. 90 */ 91 int genphy_c45_an_config_aneg(struct phy_device *phydev) 92 { 93 int changed, ret; 94 u32 adv; 95 96 linkmode_and(phydev->advertising, phydev->advertising, 97 phydev->supported); 98 99 changed = genphy_config_eee_advert(phydev); 100 101 adv = linkmode_adv_to_mii_adv_t(phydev->advertising); 102 103 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE, 104 ADVERTISE_ALL | ADVERTISE_100BASE4 | 105 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM, 106 adv); 107 if (ret < 0) 108 return ret; 109 if (ret > 0) 110 changed = 1; 111 112 adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising); 113 114 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, 115 MDIO_AN_10GBT_CTRL_ADV10G | 116 MDIO_AN_10GBT_CTRL_ADV5G | 117 MDIO_AN_10GBT_CTRL_ADV2_5G, adv); 118 if (ret < 0) 119 return ret; 120 if (ret > 0) 121 changed = 1; 122 123 return changed; 124 } 125 EXPORT_SYMBOL_GPL(genphy_c45_an_config_aneg); 126 127 /** 128 * genphy_c45_an_disable_aneg - disable auto-negotiation 129 * @phydev: target phy_device struct 130 * 131 * Disable auto-negotiation in the Clause 45 PHY. The link parameters 132 * parameters are controlled through the PMA/PMD MMD registers. 133 * 134 * Returns zero on success, negative errno code on failure. 135 */ 136 int genphy_c45_an_disable_aneg(struct phy_device *phydev) 137 { 138 139 return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1, 140 MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART); 141 } 142 EXPORT_SYMBOL_GPL(genphy_c45_an_disable_aneg); 143 144 /** 145 * genphy_c45_restart_aneg - Enable and restart auto-negotiation 146 * @phydev: target phy_device struct 147 * 148 * This assumes that the auto-negotiation MMD is present. 149 * 150 * Enable and restart auto-negotiation. 151 */ 152 int genphy_c45_restart_aneg(struct phy_device *phydev) 153 { 154 return phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1, 155 MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART); 156 } 157 EXPORT_SYMBOL_GPL(genphy_c45_restart_aneg); 158 159 /** 160 * genphy_c45_check_and_restart_aneg - Enable and restart auto-negotiation 161 * @phydev: target phy_device struct 162 * @restart: whether aneg restart is requested 163 * 164 * This assumes that the auto-negotiation MMD is present. 165 * 166 * Check, and restart auto-negotiation if needed. 167 */ 168 int genphy_c45_check_and_restart_aneg(struct phy_device *phydev, bool restart) 169 { 170 int ret; 171 172 if (!restart) { 173 /* Configure and restart aneg if it wasn't set before */ 174 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1); 175 if (ret < 0) 176 return ret; 177 178 if (!(ret & MDIO_AN_CTRL1_ENABLE)) 179 restart = true; 180 } 181 182 if (restart) 183 return genphy_c45_restart_aneg(phydev); 184 185 return 0; 186 } 187 EXPORT_SYMBOL_GPL(genphy_c45_check_and_restart_aneg); 188 189 /** 190 * genphy_c45_aneg_done - return auto-negotiation complete status 191 * @phydev: target phy_device struct 192 * 193 * This assumes that the auto-negotiation MMD is present. 194 * 195 * Reads the status register from the auto-negotiation MMD, returning: 196 * - positive if auto-negotiation is complete 197 * - negative errno code on error 198 * - zero otherwise 199 */ 200 int genphy_c45_aneg_done(struct phy_device *phydev) 201 { 202 int val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); 203 204 return val < 0 ? val : val & MDIO_AN_STAT1_COMPLETE ? 1 : 0; 205 } 206 EXPORT_SYMBOL_GPL(genphy_c45_aneg_done); 207 208 /** 209 * genphy_c45_read_link - read the overall link status from the MMDs 210 * @phydev: target phy_device struct 211 * 212 * Read the link status from the specified MMDs, and if they all indicate 213 * that the link is up, set phydev->link to 1. If an error is encountered, 214 * a negative errno will be returned, otherwise zero. 215 */ 216 int genphy_c45_read_link(struct phy_device *phydev) 217 { 218 u32 mmd_mask = MDIO_DEVS_PMAPMD; 219 int val, devad; 220 bool link = true; 221 222 if (phydev->c45_ids.mmds_present & MDIO_DEVS_AN) { 223 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1); 224 if (val < 0) 225 return val; 226 227 /* Autoneg is being started, therefore disregard current 228 * link status and report link as down. 229 */ 230 if (val & MDIO_AN_CTRL1_RESTART) { 231 phydev->link = 0; 232 return 0; 233 } 234 } 235 236 while (mmd_mask && link) { 237 devad = __ffs(mmd_mask); 238 mmd_mask &= ~BIT(devad); 239 240 /* The link state is latched low so that momentary link 241 * drops can be detected. Do not double-read the status 242 * in polling mode to detect such short link drops except 243 * the link was already down. 244 */ 245 if (!phy_polling_mode(phydev) || !phydev->link) { 246 val = phy_read_mmd(phydev, devad, MDIO_STAT1); 247 if (val < 0) 248 return val; 249 else if (val & MDIO_STAT1_LSTATUS) 250 continue; 251 } 252 253 val = phy_read_mmd(phydev, devad, MDIO_STAT1); 254 if (val < 0) 255 return val; 256 257 if (!(val & MDIO_STAT1_LSTATUS)) 258 link = false; 259 } 260 261 phydev->link = link; 262 263 return 0; 264 } 265 EXPORT_SYMBOL_GPL(genphy_c45_read_link); 266 267 /** 268 * genphy_c45_read_lpa - read the link partner advertisement and pause 269 * @phydev: target phy_device struct 270 * 271 * Read the Clause 45 defined base (7.19) and 10G (7.33) status registers, 272 * filling in the link partner advertisement, pause and asym_pause members 273 * in @phydev. This assumes that the auto-negotiation MMD is present, and 274 * the backplane bit (7.48.0) is clear. Clause 45 PHY drivers are expected 275 * to fill in the remainder of the link partner advert from vendor registers. 276 */ 277 int genphy_c45_read_lpa(struct phy_device *phydev) 278 { 279 int val; 280 281 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); 282 if (val < 0) 283 return val; 284 285 if (!(val & MDIO_AN_STAT1_COMPLETE)) { 286 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 287 phydev->lp_advertising); 288 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, 0); 289 mii_adv_mod_linkmode_adv_t(phydev->lp_advertising, 0); 290 phydev->pause = 0; 291 phydev->asym_pause = 0; 292 293 return 0; 294 } 295 296 linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising, 297 val & MDIO_AN_STAT1_LPABLE); 298 299 /* Read the link partner's base page advertisement */ 300 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA); 301 if (val < 0) 302 return val; 303 304 mii_adv_mod_linkmode_adv_t(phydev->lp_advertising, val); 305 phydev->pause = val & LPA_PAUSE_CAP ? 1 : 0; 306 phydev->asym_pause = val & LPA_PAUSE_ASYM ? 1 : 0; 307 308 /* Read the link partner's 10G advertisement */ 309 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT); 310 if (val < 0) 311 return val; 312 313 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, val); 314 315 return 0; 316 } 317 EXPORT_SYMBOL_GPL(genphy_c45_read_lpa); 318 319 /** 320 * genphy_c45_read_pma - read link speed etc from PMA 321 * @phydev: target phy_device struct 322 */ 323 int genphy_c45_read_pma(struct phy_device *phydev) 324 { 325 int val; 326 327 linkmode_zero(phydev->lp_advertising); 328 329 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1); 330 if (val < 0) 331 return val; 332 333 switch (val & MDIO_CTRL1_SPEEDSEL) { 334 case 0: 335 phydev->speed = SPEED_10; 336 break; 337 case MDIO_PMA_CTRL1_SPEED100: 338 phydev->speed = SPEED_100; 339 break; 340 case MDIO_PMA_CTRL1_SPEED1000: 341 phydev->speed = SPEED_1000; 342 break; 343 case MDIO_CTRL1_SPEED2_5G: 344 phydev->speed = SPEED_2500; 345 break; 346 case MDIO_CTRL1_SPEED5G: 347 phydev->speed = SPEED_5000; 348 break; 349 case MDIO_CTRL1_SPEED10G: 350 phydev->speed = SPEED_10000; 351 break; 352 default: 353 phydev->speed = SPEED_UNKNOWN; 354 break; 355 } 356 357 phydev->duplex = DUPLEX_FULL; 358 359 return 0; 360 } 361 EXPORT_SYMBOL_GPL(genphy_c45_read_pma); 362 363 /** 364 * genphy_c45_read_mdix - read mdix status from PMA 365 * @phydev: target phy_device struct 366 */ 367 int genphy_c45_read_mdix(struct phy_device *phydev) 368 { 369 int val; 370 371 if (phydev->speed == SPEED_10000) { 372 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, 373 MDIO_PMA_10GBT_SWAPPOL); 374 if (val < 0) 375 return val; 376 377 switch (val) { 378 case MDIO_PMA_10GBT_SWAPPOL_ABNX | MDIO_PMA_10GBT_SWAPPOL_CDNX: 379 phydev->mdix = ETH_TP_MDI; 380 break; 381 382 case 0: 383 phydev->mdix = ETH_TP_MDI_X; 384 break; 385 386 default: 387 phydev->mdix = ETH_TP_MDI_INVALID; 388 break; 389 } 390 } 391 392 return 0; 393 } 394 EXPORT_SYMBOL_GPL(genphy_c45_read_mdix); 395 396 /** 397 * genphy_c45_pma_read_abilities - read supported link modes from PMA 398 * @phydev: target phy_device struct 399 * 400 * Read the supported link modes from the PMA Status 2 (1.8) register. If bit 401 * 1.8.9 is set, the list of supported modes is build using the values in the 402 * PMA Extended Abilities (1.11) register, indicating 1000BASET an 10G related 403 * modes. If bit 1.11.14 is set, then the list is also extended with the modes 404 * in the 2.5G/5G PMA Extended register (1.21), indicating if 2.5GBASET and 405 * 5GBASET are supported. 406 */ 407 int genphy_c45_pma_read_abilities(struct phy_device *phydev) 408 { 409 int val; 410 411 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported); 412 if (phydev->c45_ids.mmds_present & MDIO_DEVS_AN) { 413 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); 414 if (val < 0) 415 return val; 416 417 if (val & MDIO_AN_STAT1_ABLE) 418 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 419 phydev->supported); 420 } 421 422 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT2); 423 if (val < 0) 424 return val; 425 426 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, 427 phydev->supported, 428 val & MDIO_PMA_STAT2_10GBSR); 429 430 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseLR_Full_BIT, 431 phydev->supported, 432 val & MDIO_PMA_STAT2_10GBLR); 433 434 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseER_Full_BIT, 435 phydev->supported, 436 val & MDIO_PMA_STAT2_10GBER); 437 438 if (val & MDIO_PMA_STAT2_EXTABLE) { 439 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE); 440 if (val < 0) 441 return val; 442 443 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT, 444 phydev->supported, 445 val & MDIO_PMA_EXTABLE_10GBLRM); 446 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 447 phydev->supported, 448 val & MDIO_PMA_EXTABLE_10GBT); 449 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT, 450 phydev->supported, 451 val & MDIO_PMA_EXTABLE_10GBKX4); 452 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, 453 phydev->supported, 454 val & MDIO_PMA_EXTABLE_10GBKR); 455 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 456 phydev->supported, 457 val & MDIO_PMA_EXTABLE_1000BT); 458 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, 459 phydev->supported, 460 val & MDIO_PMA_EXTABLE_1000BKX); 461 462 linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, 463 phydev->supported, 464 val & MDIO_PMA_EXTABLE_100BTX); 465 linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, 466 phydev->supported, 467 val & MDIO_PMA_EXTABLE_100BTX); 468 469 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, 470 phydev->supported, 471 val & MDIO_PMA_EXTABLE_10BT); 472 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, 473 phydev->supported, 474 val & MDIO_PMA_EXTABLE_10BT); 475 476 if (val & MDIO_PMA_EXTABLE_NBT) { 477 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, 478 MDIO_PMA_NG_EXTABLE); 479 if (val < 0) 480 return val; 481 482 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 483 phydev->supported, 484 val & MDIO_PMA_NG_EXTABLE_2_5GBT); 485 486 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 487 phydev->supported, 488 val & MDIO_PMA_NG_EXTABLE_5GBT); 489 } 490 } 491 492 return 0; 493 } 494 EXPORT_SYMBOL_GPL(genphy_c45_pma_read_abilities); 495 496 /** 497 * genphy_c45_read_status - read PHY status 498 * @phydev: target phy_device struct 499 * 500 * Reads status from PHY and sets phy_device members accordingly. 501 */ 502 int genphy_c45_read_status(struct phy_device *phydev) 503 { 504 int ret; 505 506 ret = genphy_c45_read_link(phydev); 507 if (ret) 508 return ret; 509 510 phydev->speed = SPEED_UNKNOWN; 511 phydev->duplex = DUPLEX_UNKNOWN; 512 phydev->pause = 0; 513 phydev->asym_pause = 0; 514 515 if (phydev->autoneg == AUTONEG_ENABLE) { 516 ret = genphy_c45_read_lpa(phydev); 517 if (ret) 518 return ret; 519 520 phy_resolve_aneg_linkmode(phydev); 521 } else { 522 ret = genphy_c45_read_pma(phydev); 523 } 524 525 return ret; 526 } 527 EXPORT_SYMBOL_GPL(genphy_c45_read_status); 528 529 /** 530 * genphy_c45_config_aneg - restart auto-negotiation or forced setup 531 * @phydev: target phy_device struct 532 * 533 * Description: If auto-negotiation is enabled, we configure the 534 * advertising, and then restart auto-negotiation. If it is not 535 * enabled, then we force a configuration. 536 */ 537 int genphy_c45_config_aneg(struct phy_device *phydev) 538 { 539 bool changed = false; 540 int ret; 541 542 if (phydev->autoneg == AUTONEG_DISABLE) 543 return genphy_c45_pma_setup_forced(phydev); 544 545 ret = genphy_c45_an_config_aneg(phydev); 546 if (ret < 0) 547 return ret; 548 if (ret > 0) 549 changed = true; 550 551 return genphy_c45_check_and_restart_aneg(phydev, changed); 552 } 553 EXPORT_SYMBOL_GPL(genphy_c45_config_aneg); 554 555 /* The gen10g_* functions are the old Clause 45 stub */ 556 557 int gen10g_config_aneg(struct phy_device *phydev) 558 { 559 return 0; 560 } 561 EXPORT_SYMBOL_GPL(gen10g_config_aneg); 562 563 struct phy_driver genphy_c45_driver = { 564 .phy_id = 0xffffffff, 565 .phy_id_mask = 0xffffffff, 566 .name = "Generic Clause 45 PHY", 567 .read_status = genphy_c45_read_status, 568 }; 569