1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Clause 45 PHY support 4 */ 5 #include <linux/ethtool.h> 6 #include <linux/export.h> 7 #include <linux/mdio.h> 8 #include <linux/mii.h> 9 #include <linux/phy.h> 10 11 /** 12 * genphy_c45_baset1_able - checks if the PMA has BASE-T1 extended abilities 13 * @phydev: target phy_device struct 14 */ 15 static bool genphy_c45_baset1_able(struct phy_device *phydev) 16 { 17 int val; 18 19 if (phydev->pma_extable == -ENODATA) { 20 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE); 21 if (val < 0) 22 return false; 23 24 phydev->pma_extable = val; 25 } 26 27 return !!(phydev->pma_extable & MDIO_PMA_EXTABLE_BT1); 28 } 29 30 /** 31 * genphy_c45_pma_can_sleep - checks if the PMA have sleep support 32 * @phydev: target phy_device struct 33 */ 34 static bool genphy_c45_pma_can_sleep(struct phy_device *phydev) 35 { 36 int stat1; 37 38 stat1 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT1); 39 if (stat1 < 0) 40 return false; 41 42 return !!(stat1 & MDIO_STAT1_LPOWERABLE); 43 } 44 45 /** 46 * genphy_c45_pma_resume - wakes up the PMA module 47 * @phydev: target phy_device struct 48 */ 49 int genphy_c45_pma_resume(struct phy_device *phydev) 50 { 51 if (!genphy_c45_pma_can_sleep(phydev)) 52 return -EOPNOTSUPP; 53 54 return phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, 55 MDIO_CTRL1_LPOWER); 56 } 57 EXPORT_SYMBOL_GPL(genphy_c45_pma_resume); 58 59 /** 60 * genphy_c45_pma_suspend - suspends the PMA module 61 * @phydev: target phy_device struct 62 */ 63 int genphy_c45_pma_suspend(struct phy_device *phydev) 64 { 65 if (!genphy_c45_pma_can_sleep(phydev)) 66 return -EOPNOTSUPP; 67 68 return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, 69 MDIO_CTRL1_LPOWER); 70 } 71 EXPORT_SYMBOL_GPL(genphy_c45_pma_suspend); 72 73 /** 74 * genphy_c45_pma_baset1_setup_master_slave - configures forced master/slave 75 * role of BaseT1 devices. 76 * @phydev: target phy_device struct 77 */ 78 int genphy_c45_pma_baset1_setup_master_slave(struct phy_device *phydev) 79 { 80 int ctl = 0; 81 82 switch (phydev->master_slave_set) { 83 case MASTER_SLAVE_CFG_MASTER_PREFERRED: 84 case MASTER_SLAVE_CFG_MASTER_FORCE: 85 ctl = MDIO_PMA_PMD_BT1_CTRL_CFG_MST; 86 break; 87 case MASTER_SLAVE_CFG_SLAVE_FORCE: 88 case MASTER_SLAVE_CFG_SLAVE_PREFERRED: 89 break; 90 case MASTER_SLAVE_CFG_UNKNOWN: 91 case MASTER_SLAVE_CFG_UNSUPPORTED: 92 return 0; 93 default: 94 phydev_warn(phydev, "Unsupported Master/Slave mode\n"); 95 return -EOPNOTSUPP; 96 } 97 98 return phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL, 99 MDIO_PMA_PMD_BT1_CTRL_CFG_MST, ctl); 100 } 101 EXPORT_SYMBOL_GPL(genphy_c45_pma_baset1_setup_master_slave); 102 103 /** 104 * genphy_c45_pma_setup_forced - configures a forced speed 105 * @phydev: target phy_device struct 106 */ 107 int genphy_c45_pma_setup_forced(struct phy_device *phydev) 108 { 109 int ctrl1, ctrl2, ret; 110 111 /* Half duplex is not supported */ 112 if (phydev->duplex != DUPLEX_FULL) 113 return -EINVAL; 114 115 ctrl1 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1); 116 if (ctrl1 < 0) 117 return ctrl1; 118 119 ctrl2 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL2); 120 if (ctrl2 < 0) 121 return ctrl2; 122 123 ctrl1 &= ~MDIO_CTRL1_SPEEDSEL; 124 /* 125 * PMA/PMD type selection is 1.7.5:0 not 1.7.3:0. See 45.2.1.6.1 126 * in 802.3-2012 and 802.3-2015. 127 */ 128 ctrl2 &= ~(MDIO_PMA_CTRL2_TYPE | 0x30); 129 130 switch (phydev->speed) { 131 case SPEED_10: 132 if (genphy_c45_baset1_able(phydev)) 133 ctrl2 |= MDIO_PMA_CTRL2_BASET1; 134 else 135 ctrl2 |= MDIO_PMA_CTRL2_10BT; 136 break; 137 case SPEED_100: 138 ctrl1 |= MDIO_PMA_CTRL1_SPEED100; 139 ctrl2 |= MDIO_PMA_CTRL2_100BTX; 140 break; 141 case SPEED_1000: 142 ctrl1 |= MDIO_PMA_CTRL1_SPEED1000; 143 /* Assume 1000base-T */ 144 ctrl2 |= MDIO_PMA_CTRL2_1000BT; 145 break; 146 case SPEED_2500: 147 ctrl1 |= MDIO_CTRL1_SPEED2_5G; 148 /* Assume 2.5Gbase-T */ 149 ctrl2 |= MDIO_PMA_CTRL2_2_5GBT; 150 break; 151 case SPEED_5000: 152 ctrl1 |= MDIO_CTRL1_SPEED5G; 153 /* Assume 5Gbase-T */ 154 ctrl2 |= MDIO_PMA_CTRL2_5GBT; 155 break; 156 case SPEED_10000: 157 ctrl1 |= MDIO_CTRL1_SPEED10G; 158 /* Assume 10Gbase-T */ 159 ctrl2 |= MDIO_PMA_CTRL2_10GBT; 160 break; 161 default: 162 return -EINVAL; 163 } 164 165 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, ctrl1); 166 if (ret < 0) 167 return ret; 168 169 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL2, ctrl2); 170 if (ret < 0) 171 return ret; 172 173 if (genphy_c45_baset1_able(phydev)) { 174 ret = genphy_c45_pma_baset1_setup_master_slave(phydev); 175 if (ret < 0) 176 return ret; 177 } 178 179 return genphy_c45_an_disable_aneg(phydev); 180 } 181 EXPORT_SYMBOL_GPL(genphy_c45_pma_setup_forced); 182 183 /* Sets master/slave preference and supported technologies. 184 * The preference is set in the BIT(4) of BASE-T1 AN 185 * advertisement register 7.515 and whether the status 186 * is forced or not, it is set in the BIT(12) of BASE-T1 187 * AN advertisement register 7.514. 188 * Sets 10BASE-T1L Ability BIT(14) in BASE-T1 autonegotiation 189 * advertisement register [31:16] if supported. 190 */ 191 static int genphy_c45_baset1_an_config_aneg(struct phy_device *phydev) 192 { 193 int changed = 0; 194 u16 adv_l = 0; 195 u16 adv_m = 0; 196 int ret; 197 198 switch (phydev->master_slave_set) { 199 case MASTER_SLAVE_CFG_MASTER_FORCE: 200 case MASTER_SLAVE_CFG_SLAVE_FORCE: 201 adv_l |= MDIO_AN_T1_ADV_L_FORCE_MS; 202 break; 203 case MASTER_SLAVE_CFG_MASTER_PREFERRED: 204 case MASTER_SLAVE_CFG_SLAVE_PREFERRED: 205 break; 206 case MASTER_SLAVE_CFG_UNKNOWN: 207 case MASTER_SLAVE_CFG_UNSUPPORTED: 208 return 0; 209 default: 210 phydev_warn(phydev, "Unsupported Master/Slave mode\n"); 211 return -EOPNOTSUPP; 212 } 213 214 switch (phydev->master_slave_set) { 215 case MASTER_SLAVE_CFG_MASTER_FORCE: 216 case MASTER_SLAVE_CFG_MASTER_PREFERRED: 217 adv_m |= MDIO_AN_T1_ADV_M_MST; 218 break; 219 case MASTER_SLAVE_CFG_SLAVE_FORCE: 220 case MASTER_SLAVE_CFG_SLAVE_PREFERRED: 221 break; 222 default: 223 break; 224 } 225 226 adv_l |= linkmode_adv_to_mii_t1_adv_l_t(phydev->advertising); 227 228 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_L, 229 (MDIO_AN_T1_ADV_L_FORCE_MS | MDIO_AN_T1_ADV_L_PAUSE_CAP 230 | MDIO_AN_T1_ADV_L_PAUSE_ASYM), adv_l); 231 if (ret < 0) 232 return ret; 233 if (ret > 0) 234 changed = 1; 235 236 adv_m |= linkmode_adv_to_mii_t1_adv_m_t(phydev->advertising); 237 238 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_M, 239 MDIO_AN_T1_ADV_M_MST | MDIO_AN_T1_ADV_M_B10L, adv_m); 240 if (ret < 0) 241 return ret; 242 if (ret > 0) 243 changed = 1; 244 245 return changed; 246 } 247 248 /** 249 * genphy_c45_an_config_aneg - configure advertisement registers 250 * @phydev: target phy_device struct 251 * 252 * Configure advertisement registers based on modes set in phydev->advertising 253 * 254 * Returns negative errno code on failure, 0 if advertisement didn't change, 255 * or 1 if advertised modes changed. 256 */ 257 int genphy_c45_an_config_aneg(struct phy_device *phydev) 258 { 259 int changed, ret; 260 u32 adv; 261 262 linkmode_and(phydev->advertising, phydev->advertising, 263 phydev->supported); 264 265 changed = genphy_config_eee_advert(phydev); 266 267 if (genphy_c45_baset1_able(phydev)) 268 return genphy_c45_baset1_an_config_aneg(phydev); 269 270 adv = linkmode_adv_to_mii_adv_t(phydev->advertising); 271 272 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE, 273 ADVERTISE_ALL | ADVERTISE_100BASE4 | 274 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM, 275 adv); 276 if (ret < 0) 277 return ret; 278 if (ret > 0) 279 changed = 1; 280 281 adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising); 282 283 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, 284 MDIO_AN_10GBT_CTRL_ADV10G | 285 MDIO_AN_10GBT_CTRL_ADV5G | 286 MDIO_AN_10GBT_CTRL_ADV2_5G, adv); 287 if (ret < 0) 288 return ret; 289 if (ret > 0) 290 changed = 1; 291 292 return changed; 293 } 294 EXPORT_SYMBOL_GPL(genphy_c45_an_config_aneg); 295 296 /** 297 * genphy_c45_an_disable_aneg - disable auto-negotiation 298 * @phydev: target phy_device struct 299 * 300 * Disable auto-negotiation in the Clause 45 PHY. The link parameters 301 * are controlled through the PMA/PMD MMD registers. 302 * 303 * Returns zero on success, negative errno code on failure. 304 */ 305 int genphy_c45_an_disable_aneg(struct phy_device *phydev) 306 { 307 u16 reg = MDIO_CTRL1; 308 309 if (genphy_c45_baset1_able(phydev)) 310 reg = MDIO_AN_T1_CTRL; 311 312 return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg, 313 MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART); 314 } 315 EXPORT_SYMBOL_GPL(genphy_c45_an_disable_aneg); 316 317 /** 318 * genphy_c45_restart_aneg - Enable and restart auto-negotiation 319 * @phydev: target phy_device struct 320 * 321 * This assumes that the auto-negotiation MMD is present. 322 * 323 * Enable and restart auto-negotiation. 324 */ 325 int genphy_c45_restart_aneg(struct phy_device *phydev) 326 { 327 u16 reg = MDIO_CTRL1; 328 329 if (genphy_c45_baset1_able(phydev)) 330 reg = MDIO_AN_T1_CTRL; 331 332 return phy_set_bits_mmd(phydev, MDIO_MMD_AN, reg, 333 MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART); 334 } 335 EXPORT_SYMBOL_GPL(genphy_c45_restart_aneg); 336 337 /** 338 * genphy_c45_check_and_restart_aneg - Enable and restart auto-negotiation 339 * @phydev: target phy_device struct 340 * @restart: whether aneg restart is requested 341 * 342 * This assumes that the auto-negotiation MMD is present. 343 * 344 * Check, and restart auto-negotiation if needed. 345 */ 346 int genphy_c45_check_and_restart_aneg(struct phy_device *phydev, bool restart) 347 { 348 u16 reg = MDIO_CTRL1; 349 int ret; 350 351 if (genphy_c45_baset1_able(phydev)) 352 reg = MDIO_AN_T1_CTRL; 353 354 if (!restart) { 355 /* Configure and restart aneg if it wasn't set before */ 356 ret = phy_read_mmd(phydev, MDIO_MMD_AN, reg); 357 if (ret < 0) 358 return ret; 359 360 if (!(ret & MDIO_AN_CTRL1_ENABLE)) 361 restart = true; 362 } 363 364 if (restart) 365 return genphy_c45_restart_aneg(phydev); 366 367 return 0; 368 } 369 EXPORT_SYMBOL_GPL(genphy_c45_check_and_restart_aneg); 370 371 /** 372 * genphy_c45_aneg_done - return auto-negotiation complete status 373 * @phydev: target phy_device struct 374 * 375 * This assumes that the auto-negotiation MMD is present. 376 * 377 * Reads the status register from the auto-negotiation MMD, returning: 378 * - positive if auto-negotiation is complete 379 * - negative errno code on error 380 * - zero otherwise 381 */ 382 int genphy_c45_aneg_done(struct phy_device *phydev) 383 { 384 int reg = MDIO_STAT1; 385 int val; 386 387 if (genphy_c45_baset1_able(phydev)) 388 reg = MDIO_AN_T1_STAT; 389 390 val = phy_read_mmd(phydev, MDIO_MMD_AN, reg); 391 392 return val < 0 ? val : val & MDIO_AN_STAT1_COMPLETE ? 1 : 0; 393 } 394 EXPORT_SYMBOL_GPL(genphy_c45_aneg_done); 395 396 /** 397 * genphy_c45_read_link - read the overall link status from the MMDs 398 * @phydev: target phy_device struct 399 * 400 * Read the link status from the specified MMDs, and if they all indicate 401 * that the link is up, set phydev->link to 1. If an error is encountered, 402 * a negative errno will be returned, otherwise zero. 403 */ 404 int genphy_c45_read_link(struct phy_device *phydev) 405 { 406 u32 mmd_mask = MDIO_DEVS_PMAPMD; 407 int val, devad; 408 bool link = true; 409 410 if (phydev->c45_ids.mmds_present & MDIO_DEVS_AN) { 411 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1); 412 if (val < 0) 413 return val; 414 415 /* Autoneg is being started, therefore disregard current 416 * link status and report link as down. 417 */ 418 if (val & MDIO_AN_CTRL1_RESTART) { 419 phydev->link = 0; 420 return 0; 421 } 422 } 423 424 while (mmd_mask && link) { 425 devad = __ffs(mmd_mask); 426 mmd_mask &= ~BIT(devad); 427 428 /* The link state is latched low so that momentary link 429 * drops can be detected. Do not double-read the status 430 * in polling mode to detect such short link drops except 431 * the link was already down. 432 */ 433 if (!phy_polling_mode(phydev) || !phydev->link) { 434 val = phy_read_mmd(phydev, devad, MDIO_STAT1); 435 if (val < 0) 436 return val; 437 else if (val & MDIO_STAT1_LSTATUS) 438 continue; 439 } 440 441 val = phy_read_mmd(phydev, devad, MDIO_STAT1); 442 if (val < 0) 443 return val; 444 445 if (!(val & MDIO_STAT1_LSTATUS)) 446 link = false; 447 } 448 449 phydev->link = link; 450 451 return 0; 452 } 453 EXPORT_SYMBOL_GPL(genphy_c45_read_link); 454 455 /* Read the Clause 45 defined BASE-T1 AN (7.513) status register to check 456 * if autoneg is complete. If so read the BASE-T1 Autonegotiation 457 * Advertisement registers filling in the link partner advertisement, 458 * pause and asym_pause members in phydev. 459 */ 460 static int genphy_c45_baset1_read_lpa(struct phy_device *phydev) 461 { 462 int val; 463 464 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_STAT); 465 if (val < 0) 466 return val; 467 468 if (!(val & MDIO_AN_STAT1_COMPLETE)) { 469 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising); 470 mii_t1_adv_l_mod_linkmode_t(phydev->lp_advertising, 0); 471 mii_t1_adv_m_mod_linkmode_t(phydev->lp_advertising, 0); 472 473 phydev->pause = 0; 474 phydev->asym_pause = 0; 475 476 return 0; 477 } 478 479 linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising, 1); 480 481 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_LP_L); 482 if (val < 0) 483 return val; 484 485 mii_t1_adv_l_mod_linkmode_t(phydev->lp_advertising, val); 486 phydev->pause = val & MDIO_AN_T1_ADV_L_PAUSE_CAP ? 1 : 0; 487 phydev->asym_pause = val & MDIO_AN_T1_ADV_L_PAUSE_ASYM ? 1 : 0; 488 489 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_LP_M); 490 if (val < 0) 491 return val; 492 493 mii_t1_adv_m_mod_linkmode_t(phydev->lp_advertising, val); 494 495 return 0; 496 } 497 498 /** 499 * genphy_c45_read_lpa - read the link partner advertisement and pause 500 * @phydev: target phy_device struct 501 * 502 * Read the Clause 45 defined base (7.19) and 10G (7.33) status registers, 503 * filling in the link partner advertisement, pause and asym_pause members 504 * in @phydev. This assumes that the auto-negotiation MMD is present, and 505 * the backplane bit (7.48.0) is clear. Clause 45 PHY drivers are expected 506 * to fill in the remainder of the link partner advert from vendor registers. 507 */ 508 int genphy_c45_read_lpa(struct phy_device *phydev) 509 { 510 int val; 511 512 if (genphy_c45_baset1_able(phydev)) 513 return genphy_c45_baset1_read_lpa(phydev); 514 515 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); 516 if (val < 0) 517 return val; 518 519 if (!(val & MDIO_AN_STAT1_COMPLETE)) { 520 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 521 phydev->lp_advertising); 522 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, 0); 523 mii_adv_mod_linkmode_adv_t(phydev->lp_advertising, 0); 524 phydev->pause = 0; 525 phydev->asym_pause = 0; 526 527 return 0; 528 } 529 530 linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising, 531 val & MDIO_AN_STAT1_LPABLE); 532 533 /* Read the link partner's base page advertisement */ 534 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA); 535 if (val < 0) 536 return val; 537 538 mii_adv_mod_linkmode_adv_t(phydev->lp_advertising, val); 539 phydev->pause = val & LPA_PAUSE_CAP ? 1 : 0; 540 phydev->asym_pause = val & LPA_PAUSE_ASYM ? 1 : 0; 541 542 /* Read the link partner's 10G advertisement */ 543 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT); 544 if (val < 0) 545 return val; 546 547 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, val); 548 549 return 0; 550 } 551 EXPORT_SYMBOL_GPL(genphy_c45_read_lpa); 552 553 /** 554 * genphy_c45_pma_baset1_read_master_slave - read forced master/slave 555 * configuration 556 * @phydev: target phy_device struct 557 */ 558 int genphy_c45_pma_baset1_read_master_slave(struct phy_device *phydev) 559 { 560 int val; 561 562 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; 563 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN; 564 565 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL); 566 if (val < 0) 567 return val; 568 569 if (val & MDIO_PMA_PMD_BT1_CTRL_CFG_MST) { 570 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE; 571 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER; 572 } else { 573 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE; 574 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE; 575 } 576 577 return 0; 578 } 579 EXPORT_SYMBOL_GPL(genphy_c45_pma_baset1_read_master_slave); 580 581 /** 582 * genphy_c45_read_pma - read link speed etc from PMA 583 * @phydev: target phy_device struct 584 */ 585 int genphy_c45_read_pma(struct phy_device *phydev) 586 { 587 int val; 588 589 linkmode_zero(phydev->lp_advertising); 590 591 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1); 592 if (val < 0) 593 return val; 594 595 switch (val & MDIO_CTRL1_SPEEDSEL) { 596 case 0: 597 phydev->speed = SPEED_10; 598 break; 599 case MDIO_PMA_CTRL1_SPEED100: 600 phydev->speed = SPEED_100; 601 break; 602 case MDIO_PMA_CTRL1_SPEED1000: 603 phydev->speed = SPEED_1000; 604 break; 605 case MDIO_CTRL1_SPEED2_5G: 606 phydev->speed = SPEED_2500; 607 break; 608 case MDIO_CTRL1_SPEED5G: 609 phydev->speed = SPEED_5000; 610 break; 611 case MDIO_CTRL1_SPEED10G: 612 phydev->speed = SPEED_10000; 613 break; 614 default: 615 phydev->speed = SPEED_UNKNOWN; 616 break; 617 } 618 619 phydev->duplex = DUPLEX_FULL; 620 621 if (genphy_c45_baset1_able(phydev)) { 622 val = genphy_c45_pma_baset1_read_master_slave(phydev); 623 if (val < 0) 624 return val; 625 } 626 627 return 0; 628 } 629 EXPORT_SYMBOL_GPL(genphy_c45_read_pma); 630 631 /** 632 * genphy_c45_read_mdix - read mdix status from PMA 633 * @phydev: target phy_device struct 634 */ 635 int genphy_c45_read_mdix(struct phy_device *phydev) 636 { 637 int val; 638 639 if (phydev->speed == SPEED_10000) { 640 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, 641 MDIO_PMA_10GBT_SWAPPOL); 642 if (val < 0) 643 return val; 644 645 switch (val) { 646 case MDIO_PMA_10GBT_SWAPPOL_ABNX | MDIO_PMA_10GBT_SWAPPOL_CDNX: 647 phydev->mdix = ETH_TP_MDI; 648 break; 649 650 case 0: 651 phydev->mdix = ETH_TP_MDI_X; 652 break; 653 654 default: 655 phydev->mdix = ETH_TP_MDI_INVALID; 656 break; 657 } 658 } 659 660 return 0; 661 } 662 EXPORT_SYMBOL_GPL(genphy_c45_read_mdix); 663 664 /** 665 * genphy_c45_pma_read_abilities - read supported link modes from PMA 666 * @phydev: target phy_device struct 667 * 668 * Read the supported link modes from the PMA Status 2 (1.8) register. If bit 669 * 1.8.9 is set, the list of supported modes is build using the values in the 670 * PMA Extended Abilities (1.11) register, indicating 1000BASET an 10G related 671 * modes. If bit 1.11.14 is set, then the list is also extended with the modes 672 * in the 2.5G/5G PMA Extended register (1.21), indicating if 2.5GBASET and 673 * 5GBASET are supported. 674 */ 675 int genphy_c45_pma_read_abilities(struct phy_device *phydev) 676 { 677 int val; 678 679 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported); 680 if (phydev->c45_ids.mmds_present & MDIO_DEVS_AN) { 681 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); 682 if (val < 0) 683 return val; 684 685 if (val & MDIO_AN_STAT1_ABLE) 686 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 687 phydev->supported); 688 } 689 690 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT2); 691 if (val < 0) 692 return val; 693 694 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, 695 phydev->supported, 696 val & MDIO_PMA_STAT2_10GBSR); 697 698 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseLR_Full_BIT, 699 phydev->supported, 700 val & MDIO_PMA_STAT2_10GBLR); 701 702 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseER_Full_BIT, 703 phydev->supported, 704 val & MDIO_PMA_STAT2_10GBER); 705 706 if (val & MDIO_PMA_STAT2_EXTABLE) { 707 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE); 708 if (val < 0) 709 return val; 710 711 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT, 712 phydev->supported, 713 val & MDIO_PMA_EXTABLE_10GBLRM); 714 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 715 phydev->supported, 716 val & MDIO_PMA_EXTABLE_10GBT); 717 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT, 718 phydev->supported, 719 val & MDIO_PMA_EXTABLE_10GBKX4); 720 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, 721 phydev->supported, 722 val & MDIO_PMA_EXTABLE_10GBKR); 723 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 724 phydev->supported, 725 val & MDIO_PMA_EXTABLE_1000BT); 726 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, 727 phydev->supported, 728 val & MDIO_PMA_EXTABLE_1000BKX); 729 730 linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, 731 phydev->supported, 732 val & MDIO_PMA_EXTABLE_100BTX); 733 linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, 734 phydev->supported, 735 val & MDIO_PMA_EXTABLE_100BTX); 736 737 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, 738 phydev->supported, 739 val & MDIO_PMA_EXTABLE_10BT); 740 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, 741 phydev->supported, 742 val & MDIO_PMA_EXTABLE_10BT); 743 744 if (val & MDIO_PMA_EXTABLE_NBT) { 745 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, 746 MDIO_PMA_NG_EXTABLE); 747 if (val < 0) 748 return val; 749 750 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 751 phydev->supported, 752 val & MDIO_PMA_NG_EXTABLE_2_5GBT); 753 754 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 755 phydev->supported, 756 val & MDIO_PMA_NG_EXTABLE_5GBT); 757 } 758 759 if (val & MDIO_PMA_EXTABLE_BT1) { 760 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1); 761 if (val < 0) 762 return val; 763 764 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT, 765 phydev->supported, 766 val & MDIO_PMA_PMD_BT1_B10L_ABLE); 767 768 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_STAT); 769 if (val < 0) 770 return val; 771 772 linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 773 phydev->supported, 774 val & MDIO_AN_STAT1_ABLE); 775 } 776 } 777 778 return 0; 779 } 780 EXPORT_SYMBOL_GPL(genphy_c45_pma_read_abilities); 781 782 /* Read master/slave preference from registers. 783 * The preference is read from the BIT(4) of BASE-T1 AN 784 * advertisement register 7.515 and whether the preference 785 * is forced or not, it is read from BASE-T1 AN advertisement 786 * register 7.514. 787 */ 788 int genphy_c45_baset1_read_status(struct phy_device *phydev) 789 { 790 int ret; 791 int cfg; 792 793 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN; 794 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; 795 796 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_L); 797 if (ret < 0) 798 return ret; 799 800 cfg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_M); 801 if (cfg < 0) 802 return cfg; 803 804 if (ret & MDIO_AN_T1_ADV_L_FORCE_MS) { 805 if (cfg & MDIO_AN_T1_ADV_M_MST) 806 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE; 807 else 808 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE; 809 } else { 810 if (cfg & MDIO_AN_T1_ADV_M_MST) 811 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_PREFERRED; 812 else 813 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_PREFERRED; 814 } 815 816 return 0; 817 } 818 EXPORT_SYMBOL_GPL(genphy_c45_baset1_read_status); 819 820 /** 821 * genphy_c45_read_status - read PHY status 822 * @phydev: target phy_device struct 823 * 824 * Reads status from PHY and sets phy_device members accordingly. 825 */ 826 int genphy_c45_read_status(struct phy_device *phydev) 827 { 828 int ret; 829 830 ret = genphy_c45_read_link(phydev); 831 if (ret) 832 return ret; 833 834 phydev->speed = SPEED_UNKNOWN; 835 phydev->duplex = DUPLEX_UNKNOWN; 836 phydev->pause = 0; 837 phydev->asym_pause = 0; 838 839 if (phydev->autoneg == AUTONEG_ENABLE) { 840 ret = genphy_c45_read_lpa(phydev); 841 if (ret) 842 return ret; 843 844 if (genphy_c45_baset1_able(phydev)) { 845 ret = genphy_c45_baset1_read_status(phydev); 846 if (ret < 0) 847 return ret; 848 } 849 850 phy_resolve_aneg_linkmode(phydev); 851 } else { 852 ret = genphy_c45_read_pma(phydev); 853 } 854 855 return ret; 856 } 857 EXPORT_SYMBOL_GPL(genphy_c45_read_status); 858 859 /** 860 * genphy_c45_config_aneg - restart auto-negotiation or forced setup 861 * @phydev: target phy_device struct 862 * 863 * Description: If auto-negotiation is enabled, we configure the 864 * advertising, and then restart auto-negotiation. If it is not 865 * enabled, then we force a configuration. 866 */ 867 int genphy_c45_config_aneg(struct phy_device *phydev) 868 { 869 bool changed = false; 870 int ret; 871 872 if (phydev->autoneg == AUTONEG_DISABLE) 873 return genphy_c45_pma_setup_forced(phydev); 874 875 ret = genphy_c45_an_config_aneg(phydev); 876 if (ret < 0) 877 return ret; 878 if (ret > 0) 879 changed = true; 880 881 return genphy_c45_check_and_restart_aneg(phydev, changed); 882 } 883 EXPORT_SYMBOL_GPL(genphy_c45_config_aneg); 884 885 /* The gen10g_* functions are the old Clause 45 stub */ 886 887 int gen10g_config_aneg(struct phy_device *phydev) 888 { 889 return 0; 890 } 891 EXPORT_SYMBOL_GPL(gen10g_config_aneg); 892 893 int genphy_c45_loopback(struct phy_device *phydev, bool enable) 894 { 895 return phy_modify_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, 896 MDIO_PCS_CTRL1_LOOPBACK, 897 enable ? MDIO_PCS_CTRL1_LOOPBACK : 0); 898 } 899 EXPORT_SYMBOL_GPL(genphy_c45_loopback); 900 901 /** 902 * genphy_c45_fast_retrain - configure fast retrain registers 903 * @phydev: target phy_device struct 904 * @enable: enable fast retrain or not 905 * 906 * Description: If fast-retrain is enabled, we configure PHY as 907 * advertising fast retrain capable and THP Bypass Request, then 908 * enable fast retrain. If it is not enabled, we configure fast 909 * retrain disabled. 910 */ 911 int genphy_c45_fast_retrain(struct phy_device *phydev, bool enable) 912 { 913 int ret; 914 915 if (!enable) 916 return phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FSRT_CSR, 917 MDIO_PMA_10GBR_FSRT_ENABLE); 918 919 if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported)) { 920 ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, 921 MDIO_AN_10GBT_CTRL_ADVFSRT2_5G); 922 if (ret) 923 return ret; 924 925 ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_CTRL2, 926 MDIO_AN_THP_BP2_5GT); 927 if (ret) 928 return ret; 929 } 930 931 return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FSRT_CSR, 932 MDIO_PMA_10GBR_FSRT_ENABLE); 933 } 934 EXPORT_SYMBOL_GPL(genphy_c45_fast_retrain); 935 936 struct phy_driver genphy_c45_driver = { 937 .phy_id = 0xffffffff, 938 .phy_id_mask = 0xffffffff, 939 .name = "Generic Clause 45 PHY", 940 .read_status = genphy_c45_read_status, 941 }; 942