1 /* 2 * Clause 45 PHY support 3 */ 4 #include <linux/ethtool.h> 5 #include <linux/export.h> 6 #include <linux/mdio.h> 7 #include <linux/mii.h> 8 #include <linux/phy.h> 9 10 /** 11 * genphy_c45_setup_forced - configures a forced speed 12 * @phydev: target phy_device struct 13 */ 14 int genphy_c45_pma_setup_forced(struct phy_device *phydev) 15 { 16 int ctrl1, ctrl2, ret; 17 18 /* Half duplex is not supported */ 19 if (phydev->duplex != DUPLEX_FULL) 20 return -EINVAL; 21 22 ctrl1 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1); 23 if (ctrl1 < 0) 24 return ctrl1; 25 26 ctrl2 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL2); 27 if (ctrl2 < 0) 28 return ctrl2; 29 30 ctrl1 &= ~MDIO_CTRL1_SPEEDSEL; 31 /* 32 * PMA/PMD type selection is 1.7.5:0 not 1.7.3:0. See 45.2.1.6.1 33 * in 802.3-2012 and 802.3-2015. 34 */ 35 ctrl2 &= ~(MDIO_PMA_CTRL2_TYPE | 0x30); 36 37 switch (phydev->speed) { 38 case SPEED_10: 39 ctrl2 |= MDIO_PMA_CTRL2_10BT; 40 break; 41 case SPEED_100: 42 ctrl1 |= MDIO_PMA_CTRL1_SPEED100; 43 ctrl2 |= MDIO_PMA_CTRL2_100BTX; 44 break; 45 case SPEED_1000: 46 ctrl1 |= MDIO_PMA_CTRL1_SPEED1000; 47 /* Assume 1000base-T */ 48 ctrl2 |= MDIO_PMA_CTRL2_1000BT; 49 break; 50 case SPEED_2500: 51 ctrl1 |= MDIO_CTRL1_SPEED2_5G; 52 /* Assume 2.5Gbase-T */ 53 ctrl2 |= MDIO_PMA_CTRL2_2_5GBT; 54 break; 55 case SPEED_5000: 56 ctrl1 |= MDIO_CTRL1_SPEED5G; 57 /* Assume 5Gbase-T */ 58 ctrl2 |= MDIO_PMA_CTRL2_5GBT; 59 break; 60 case SPEED_10000: 61 ctrl1 |= MDIO_CTRL1_SPEED10G; 62 /* Assume 10Gbase-T */ 63 ctrl2 |= MDIO_PMA_CTRL2_10GBT; 64 break; 65 default: 66 return -EINVAL; 67 } 68 69 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, ctrl1); 70 if (ret < 0) 71 return ret; 72 73 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL2, ctrl2); 74 if (ret < 0) 75 return ret; 76 77 return genphy_c45_an_disable_aneg(phydev); 78 } 79 EXPORT_SYMBOL_GPL(genphy_c45_pma_setup_forced); 80 81 /** 82 * genphy_c45_an_config_aneg - configure advertisement registers 83 * @phydev: target phy_device struct 84 * 85 * Configure advertisement registers based on modes set in phydev->advertising 86 * 87 * Returns negative errno code on failure, 0 if advertisement didn't change, 88 * or 1 if advertised modes changed. 89 */ 90 int genphy_c45_an_config_aneg(struct phy_device *phydev) 91 { 92 int changed, ret; 93 u32 adv; 94 95 linkmode_and(phydev->advertising, phydev->advertising, 96 phydev->supported); 97 98 changed = genphy_config_eee_advert(phydev); 99 100 adv = linkmode_adv_to_mii_adv_t(phydev->advertising); 101 102 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE, 103 ADVERTISE_ALL | ADVERTISE_100BASE4 | 104 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM, 105 adv); 106 if (ret < 0) 107 return ret; 108 if (ret > 0) 109 changed = 1; 110 111 adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising); 112 113 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, 114 MDIO_AN_10GBT_CTRL_ADV10G | 115 MDIO_AN_10GBT_CTRL_ADV5G | 116 MDIO_AN_10GBT_CTRL_ADV2_5G, adv); 117 if (ret < 0) 118 return ret; 119 if (ret > 0) 120 changed = 1; 121 122 return changed; 123 } 124 EXPORT_SYMBOL_GPL(genphy_c45_an_config_aneg); 125 126 /** 127 * genphy_c45_an_disable_aneg - disable auto-negotiation 128 * @phydev: target phy_device struct 129 * 130 * Disable auto-negotiation in the Clause 45 PHY. The link parameters 131 * parameters are controlled through the PMA/PMD MMD registers. 132 * 133 * Returns zero on success, negative errno code on failure. 134 */ 135 int genphy_c45_an_disable_aneg(struct phy_device *phydev) 136 { 137 138 return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1, 139 MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART); 140 } 141 EXPORT_SYMBOL_GPL(genphy_c45_an_disable_aneg); 142 143 /** 144 * genphy_c45_restart_aneg - Enable and restart auto-negotiation 145 * @phydev: target phy_device struct 146 * 147 * This assumes that the auto-negotiation MMD is present. 148 * 149 * Enable and restart auto-negotiation. 150 */ 151 int genphy_c45_restart_aneg(struct phy_device *phydev) 152 { 153 return phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1, 154 MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART); 155 } 156 EXPORT_SYMBOL_GPL(genphy_c45_restart_aneg); 157 158 /** 159 * genphy_c45_check_and_restart_aneg - Enable and restart auto-negotiation 160 * @phydev: target phy_device struct 161 * @restart: whether aneg restart is requested 162 * 163 * This assumes that the auto-negotiation MMD is present. 164 * 165 * Check, and restart auto-negotiation if needed. 166 */ 167 int genphy_c45_check_and_restart_aneg(struct phy_device *phydev, bool restart) 168 { 169 int ret = 0; 170 171 if (!restart) { 172 /* Configure and restart aneg if it wasn't set before */ 173 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1); 174 if (ret < 0) 175 return ret; 176 177 if (!(ret & MDIO_AN_CTRL1_ENABLE)) 178 restart = true; 179 } 180 181 if (restart) 182 ret = genphy_c45_restart_aneg(phydev); 183 184 return ret; 185 } 186 EXPORT_SYMBOL_GPL(genphy_c45_check_and_restart_aneg); 187 188 /** 189 * genphy_c45_aneg_done - return auto-negotiation complete status 190 * @phydev: target phy_device struct 191 * 192 * This assumes that the auto-negotiation MMD is present. 193 * 194 * Reads the status register from the auto-negotiation MMD, returning: 195 * - positive if auto-negotiation is complete 196 * - negative errno code on error 197 * - zero otherwise 198 */ 199 int genphy_c45_aneg_done(struct phy_device *phydev) 200 { 201 int val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); 202 203 return val < 0 ? val : val & MDIO_AN_STAT1_COMPLETE ? 1 : 0; 204 } 205 EXPORT_SYMBOL_GPL(genphy_c45_aneg_done); 206 207 /** 208 * genphy_c45_read_link - read the overall link status from the MMDs 209 * @phydev: target phy_device struct 210 * 211 * Read the link status from the specified MMDs, and if they all indicate 212 * that the link is up, set phydev->link to 1. If an error is encountered, 213 * a negative errno will be returned, otherwise zero. 214 */ 215 int genphy_c45_read_link(struct phy_device *phydev) 216 { 217 u32 mmd_mask = MDIO_DEVS_PMAPMD; 218 int val, devad; 219 bool link = true; 220 221 while (mmd_mask && link) { 222 devad = __ffs(mmd_mask); 223 mmd_mask &= ~BIT(devad); 224 225 /* The link state is latched low so that momentary link 226 * drops can be detected. Do not double-read the status 227 * in polling mode to detect such short link drops. 228 */ 229 if (!phy_polling_mode(phydev)) { 230 val = phy_read_mmd(phydev, devad, MDIO_STAT1); 231 if (val < 0) 232 return val; 233 else if (val & MDIO_STAT1_LSTATUS) 234 continue; 235 } 236 237 val = phy_read_mmd(phydev, devad, MDIO_STAT1); 238 if (val < 0) 239 return val; 240 241 if (!(val & MDIO_STAT1_LSTATUS)) 242 link = false; 243 } 244 245 phydev->link = link; 246 247 return 0; 248 } 249 EXPORT_SYMBOL_GPL(genphy_c45_read_link); 250 251 /** 252 * genphy_c45_read_lpa - read the link partner advertisement and pause 253 * @phydev: target phy_device struct 254 * 255 * Read the Clause 45 defined base (7.19) and 10G (7.33) status registers, 256 * filling in the link partner advertisement, pause and asym_pause members 257 * in @phydev. This assumes that the auto-negotiation MMD is present, and 258 * the backplane bit (7.48.0) is clear. Clause 45 PHY drivers are expected 259 * to fill in the remainder of the link partner advert from vendor registers. 260 */ 261 int genphy_c45_read_lpa(struct phy_device *phydev) 262 { 263 int val; 264 265 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); 266 if (val < 0) 267 return val; 268 269 if (!(val & MDIO_AN_STAT1_COMPLETE)) { 270 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 271 phydev->lp_advertising); 272 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, 0); 273 mii_adv_mod_linkmode_adv_t(phydev->lp_advertising, 0); 274 phydev->pause = 0; 275 phydev->asym_pause = 0; 276 277 return 0; 278 } 279 280 linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising, 281 val & MDIO_AN_STAT1_LPABLE); 282 283 /* Read the link partner's base page advertisement */ 284 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA); 285 if (val < 0) 286 return val; 287 288 mii_adv_mod_linkmode_adv_t(phydev->lp_advertising, val); 289 phydev->pause = val & LPA_PAUSE_CAP ? 1 : 0; 290 phydev->asym_pause = val & LPA_PAUSE_ASYM ? 1 : 0; 291 292 /* Read the link partner's 10G advertisement */ 293 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT); 294 if (val < 0) 295 return val; 296 297 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, val); 298 299 return 0; 300 } 301 EXPORT_SYMBOL_GPL(genphy_c45_read_lpa); 302 303 /** 304 * genphy_c45_read_pma - read link speed etc from PMA 305 * @phydev: target phy_device struct 306 */ 307 int genphy_c45_read_pma(struct phy_device *phydev) 308 { 309 int val; 310 311 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1); 312 if (val < 0) 313 return val; 314 315 switch (val & MDIO_CTRL1_SPEEDSEL) { 316 case 0: 317 phydev->speed = SPEED_10; 318 break; 319 case MDIO_PMA_CTRL1_SPEED100: 320 phydev->speed = SPEED_100; 321 break; 322 case MDIO_PMA_CTRL1_SPEED1000: 323 phydev->speed = SPEED_1000; 324 break; 325 case MDIO_CTRL1_SPEED2_5G: 326 phydev->speed = SPEED_2500; 327 break; 328 case MDIO_CTRL1_SPEED5G: 329 phydev->speed = SPEED_5000; 330 break; 331 case MDIO_CTRL1_SPEED10G: 332 phydev->speed = SPEED_10000; 333 break; 334 default: 335 phydev->speed = SPEED_UNKNOWN; 336 break; 337 } 338 339 phydev->duplex = DUPLEX_FULL; 340 341 return 0; 342 } 343 EXPORT_SYMBOL_GPL(genphy_c45_read_pma); 344 345 /** 346 * genphy_c45_read_mdix - read mdix status from PMA 347 * @phydev: target phy_device struct 348 */ 349 int genphy_c45_read_mdix(struct phy_device *phydev) 350 { 351 int val; 352 353 if (phydev->speed == SPEED_10000) { 354 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, 355 MDIO_PMA_10GBT_SWAPPOL); 356 if (val < 0) 357 return val; 358 359 switch (val) { 360 case MDIO_PMA_10GBT_SWAPPOL_ABNX | MDIO_PMA_10GBT_SWAPPOL_CDNX: 361 phydev->mdix = ETH_TP_MDI; 362 break; 363 364 case 0: 365 phydev->mdix = ETH_TP_MDI_X; 366 break; 367 368 default: 369 phydev->mdix = ETH_TP_MDI_INVALID; 370 break; 371 } 372 } 373 374 return 0; 375 } 376 EXPORT_SYMBOL_GPL(genphy_c45_read_mdix); 377 378 /** 379 * genphy_c45_pma_read_abilities - read supported link modes from PMA 380 * @phydev: target phy_device struct 381 * 382 * Read the supported link modes from the PMA Status 2 (1.8) register. If bit 383 * 1.8.9 is set, the list of supported modes is build using the values in the 384 * PMA Extended Abilities (1.11) register, indicating 1000BASET an 10G related 385 * modes. If bit 1.11.14 is set, then the list is also extended with the modes 386 * in the 2.5G/5G PMA Extended register (1.21), indicating if 2.5GBASET and 387 * 5GBASET are supported. 388 */ 389 int genphy_c45_pma_read_abilities(struct phy_device *phydev) 390 { 391 int val; 392 393 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported); 394 if (phydev->c45_ids.devices_in_package & MDIO_DEVS_AN) { 395 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); 396 if (val < 0) 397 return val; 398 399 if (val & MDIO_AN_STAT1_ABLE) 400 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 401 phydev->supported); 402 } 403 404 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT2); 405 if (val < 0) 406 return val; 407 408 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, 409 phydev->supported, 410 val & MDIO_PMA_STAT2_10GBSR); 411 412 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseLR_Full_BIT, 413 phydev->supported, 414 val & MDIO_PMA_STAT2_10GBLR); 415 416 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseER_Full_BIT, 417 phydev->supported, 418 val & MDIO_PMA_STAT2_10GBER); 419 420 if (val & MDIO_PMA_STAT2_EXTABLE) { 421 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE); 422 if (val < 0) 423 return val; 424 425 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT, 426 phydev->supported, 427 val & MDIO_PMA_EXTABLE_10GBLRM); 428 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 429 phydev->supported, 430 val & MDIO_PMA_EXTABLE_10GBT); 431 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT, 432 phydev->supported, 433 val & MDIO_PMA_EXTABLE_10GBKX4); 434 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, 435 phydev->supported, 436 val & MDIO_PMA_EXTABLE_10GBKR); 437 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 438 phydev->supported, 439 val & MDIO_PMA_EXTABLE_1000BT); 440 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, 441 phydev->supported, 442 val & MDIO_PMA_EXTABLE_1000BKX); 443 444 linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, 445 phydev->supported, 446 val & MDIO_PMA_EXTABLE_100BTX); 447 linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, 448 phydev->supported, 449 val & MDIO_PMA_EXTABLE_100BTX); 450 451 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, 452 phydev->supported, 453 val & MDIO_PMA_EXTABLE_10BT); 454 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, 455 phydev->supported, 456 val & MDIO_PMA_EXTABLE_10BT); 457 458 if (val & MDIO_PMA_EXTABLE_NBT) { 459 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, 460 MDIO_PMA_NG_EXTABLE); 461 if (val < 0) 462 return val; 463 464 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 465 phydev->supported, 466 val & MDIO_PMA_NG_EXTABLE_2_5GBT); 467 468 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 469 phydev->supported, 470 val & MDIO_PMA_NG_EXTABLE_5GBT); 471 } 472 } 473 474 return 0; 475 } 476 EXPORT_SYMBOL_GPL(genphy_c45_pma_read_abilities); 477 478 /** 479 * genphy_c45_read_status - read PHY status 480 * @phydev: target phy_device struct 481 * 482 * Reads status from PHY and sets phy_device members accordingly. 483 */ 484 int genphy_c45_read_status(struct phy_device *phydev) 485 { 486 int ret; 487 488 ret = genphy_c45_read_link(phydev); 489 if (ret) 490 return ret; 491 492 phydev->speed = SPEED_UNKNOWN; 493 phydev->duplex = DUPLEX_UNKNOWN; 494 phydev->pause = 0; 495 phydev->asym_pause = 0; 496 497 if (phydev->autoneg == AUTONEG_ENABLE) { 498 ret = genphy_c45_read_lpa(phydev); 499 if (ret) 500 return ret; 501 502 phy_resolve_aneg_linkmode(phydev); 503 } else { 504 ret = genphy_c45_read_pma(phydev); 505 } 506 507 return ret; 508 } 509 EXPORT_SYMBOL_GPL(genphy_c45_read_status); 510 511 /* The gen10g_* functions are the old Clause 45 stub */ 512 513 int gen10g_config_aneg(struct phy_device *phydev) 514 { 515 return 0; 516 } 517 EXPORT_SYMBOL_GPL(gen10g_config_aneg); 518 519 struct phy_driver genphy_c45_driver = { 520 .phy_id = 0xffffffff, 521 .phy_id_mask = 0xffffffff, 522 .name = "Generic Clause 45 PHY", 523 .soft_reset = genphy_no_soft_reset, 524 .read_status = genphy_c45_read_status, 525 }; 526