1 /* 2 * Clause 45 PHY support 3 */ 4 #include <linux/ethtool.h> 5 #include <linux/export.h> 6 #include <linux/mdio.h> 7 #include <linux/mii.h> 8 #include <linux/phy.h> 9 10 /** 11 * genphy_c45_setup_forced - configures a forced speed 12 * @phydev: target phy_device struct 13 */ 14 int genphy_c45_pma_setup_forced(struct phy_device *phydev) 15 { 16 int ctrl1, ctrl2, ret; 17 18 /* Half duplex is not supported */ 19 if (phydev->duplex != DUPLEX_FULL) 20 return -EINVAL; 21 22 ctrl1 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1); 23 if (ctrl1 < 0) 24 return ctrl1; 25 26 ctrl2 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL2); 27 if (ctrl2 < 0) 28 return ctrl2; 29 30 ctrl1 &= ~MDIO_CTRL1_SPEEDSEL; 31 /* 32 * PMA/PMD type selection is 1.7.5:0 not 1.7.3:0. See 45.2.1.6.1 33 * in 802.3-2012 and 802.3-2015. 34 */ 35 ctrl2 &= ~(MDIO_PMA_CTRL2_TYPE | 0x30); 36 37 switch (phydev->speed) { 38 case SPEED_10: 39 ctrl2 |= MDIO_PMA_CTRL2_10BT; 40 break; 41 case SPEED_100: 42 ctrl1 |= MDIO_PMA_CTRL1_SPEED100; 43 ctrl2 |= MDIO_PMA_CTRL2_100BTX; 44 break; 45 case SPEED_1000: 46 ctrl1 |= MDIO_PMA_CTRL1_SPEED1000; 47 /* Assume 1000base-T */ 48 ctrl2 |= MDIO_PMA_CTRL2_1000BT; 49 break; 50 case SPEED_2500: 51 ctrl1 |= MDIO_CTRL1_SPEED2_5G; 52 /* Assume 2.5Gbase-T */ 53 ctrl2 |= MDIO_PMA_CTRL2_2_5GBT; 54 break; 55 case SPEED_5000: 56 ctrl1 |= MDIO_CTRL1_SPEED5G; 57 /* Assume 5Gbase-T */ 58 ctrl2 |= MDIO_PMA_CTRL2_5GBT; 59 break; 60 case SPEED_10000: 61 ctrl1 |= MDIO_CTRL1_SPEED10G; 62 /* Assume 10Gbase-T */ 63 ctrl2 |= MDIO_PMA_CTRL2_10GBT; 64 break; 65 default: 66 return -EINVAL; 67 } 68 69 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, ctrl1); 70 if (ret < 0) 71 return ret; 72 73 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL2, ctrl2); 74 if (ret < 0) 75 return ret; 76 77 return genphy_c45_an_disable_aneg(phydev); 78 } 79 EXPORT_SYMBOL_GPL(genphy_c45_pma_setup_forced); 80 81 /** 82 * genphy_c45_an_config_aneg - configure advertisement registers 83 * @phydev: target phy_device struct 84 * 85 * Configure advertisement registers based on modes set in phydev->advertising 86 * 87 * Returns negative errno code on failure, 0 if advertisement didn't change, 88 * or 1 if advertised modes changed. 89 */ 90 int genphy_c45_an_config_aneg(struct phy_device *phydev) 91 { 92 int changed, ret; 93 u32 adv; 94 95 linkmode_and(phydev->advertising, phydev->advertising, 96 phydev->supported); 97 98 changed = genphy_config_eee_advert(phydev); 99 100 adv = linkmode_adv_to_mii_adv_t(phydev->advertising); 101 102 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE, 103 ADVERTISE_ALL | ADVERTISE_100BASE4 | 104 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM, 105 adv); 106 if (ret < 0) 107 return ret; 108 if (ret > 0) 109 changed = 1; 110 111 adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising); 112 113 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, 114 MDIO_AN_10GBT_CTRL_ADV10G | 115 MDIO_AN_10GBT_CTRL_ADV5G | 116 MDIO_AN_10GBT_CTRL_ADV2_5G, adv); 117 if (ret < 0) 118 return ret; 119 if (ret > 0) 120 changed = 1; 121 122 return changed; 123 } 124 EXPORT_SYMBOL_GPL(genphy_c45_an_config_aneg); 125 126 /** 127 * genphy_c45_an_disable_aneg - disable auto-negotiation 128 * @phydev: target phy_device struct 129 * 130 * Disable auto-negotiation in the Clause 45 PHY. The link parameters 131 * parameters are controlled through the PMA/PMD MMD registers. 132 * 133 * Returns zero on success, negative errno code on failure. 134 */ 135 int genphy_c45_an_disable_aneg(struct phy_device *phydev) 136 { 137 138 return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1, 139 MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART); 140 } 141 EXPORT_SYMBOL_GPL(genphy_c45_an_disable_aneg); 142 143 /** 144 * genphy_c45_restart_aneg - Enable and restart auto-negotiation 145 * @phydev: target phy_device struct 146 * 147 * This assumes that the auto-negotiation MMD is present. 148 * 149 * Enable and restart auto-negotiation. 150 */ 151 int genphy_c45_restart_aneg(struct phy_device *phydev) 152 { 153 return phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1, 154 MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART); 155 } 156 EXPORT_SYMBOL_GPL(genphy_c45_restart_aneg); 157 158 /** 159 * genphy_c45_check_and_restart_aneg - Enable and restart auto-negotiation 160 * @phydev: target phy_device struct 161 * @restart: whether aneg restart is requested 162 * 163 * This assumes that the auto-negotiation MMD is present. 164 * 165 * Check, and restart auto-negotiation if needed. 166 */ 167 int genphy_c45_check_and_restart_aneg(struct phy_device *phydev, bool restart) 168 { 169 int ret = 0; 170 171 if (!restart) { 172 /* Configure and restart aneg if it wasn't set before */ 173 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1); 174 if (ret < 0) 175 return ret; 176 177 if (!(ret & MDIO_AN_CTRL1_ENABLE)) 178 restart = true; 179 } 180 181 if (restart) 182 ret = genphy_c45_restart_aneg(phydev); 183 184 return ret; 185 } 186 EXPORT_SYMBOL_GPL(genphy_c45_check_and_restart_aneg); 187 188 /** 189 * genphy_c45_aneg_done - return auto-negotiation complete status 190 * @phydev: target phy_device struct 191 * 192 * This assumes that the auto-negotiation MMD is present. 193 * 194 * Reads the status register from the auto-negotiation MMD, returning: 195 * - positive if auto-negotiation is complete 196 * - negative errno code on error 197 * - zero otherwise 198 */ 199 int genphy_c45_aneg_done(struct phy_device *phydev) 200 { 201 int val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); 202 203 return val < 0 ? val : val & MDIO_AN_STAT1_COMPLETE ? 1 : 0; 204 } 205 EXPORT_SYMBOL_GPL(genphy_c45_aneg_done); 206 207 /** 208 * genphy_c45_read_link - read the overall link status from the MMDs 209 * @phydev: target phy_device struct 210 * 211 * Read the link status from the specified MMDs, and if they all indicate 212 * that the link is up, set phydev->link to 1. If an error is encountered, 213 * a negative errno will be returned, otherwise zero. 214 */ 215 int genphy_c45_read_link(struct phy_device *phydev) 216 { 217 u32 mmd_mask = MDIO_DEVS_PMAPMD; 218 int val, devad; 219 bool link = true; 220 221 while (mmd_mask && link) { 222 devad = __ffs(mmd_mask); 223 mmd_mask &= ~BIT(devad); 224 225 /* The link state is latched low so that momentary link 226 * drops can be detected. Do not double-read the status 227 * in polling mode to detect such short link drops. 228 */ 229 if (!phy_polling_mode(phydev)) { 230 val = phy_read_mmd(phydev, devad, MDIO_STAT1); 231 if (val < 0) 232 return val; 233 else if (val & MDIO_STAT1_LSTATUS) 234 continue; 235 } 236 237 val = phy_read_mmd(phydev, devad, MDIO_STAT1); 238 if (val < 0) 239 return val; 240 241 if (!(val & MDIO_STAT1_LSTATUS)) 242 link = false; 243 } 244 245 phydev->link = link; 246 247 return 0; 248 } 249 EXPORT_SYMBOL_GPL(genphy_c45_read_link); 250 251 /** 252 * genphy_c45_read_lpa - read the link partner advertisement and pause 253 * @phydev: target phy_device struct 254 * 255 * Read the Clause 45 defined base (7.19) and 10G (7.33) status registers, 256 * filling in the link partner advertisement, pause and asym_pause members 257 * in @phydev. This assumes that the auto-negotiation MMD is present, and 258 * the backplane bit (7.48.0) is clear. Clause 45 PHY drivers are expected 259 * to fill in the remainder of the link partner advert from vendor registers. 260 */ 261 int genphy_c45_read_lpa(struct phy_device *phydev) 262 { 263 int val; 264 265 /* Read the link partner's base page advertisement */ 266 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA); 267 if (val < 0) 268 return val; 269 270 mii_lpa_mod_linkmode_lpa_t(phydev->lp_advertising, val); 271 phydev->pause = val & LPA_PAUSE_CAP ? 1 : 0; 272 phydev->asym_pause = val & LPA_PAUSE_ASYM ? 1 : 0; 273 274 /* Read the link partner's 10G advertisement */ 275 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT); 276 if (val < 0) 277 return val; 278 279 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, val); 280 281 return 0; 282 } 283 EXPORT_SYMBOL_GPL(genphy_c45_read_lpa); 284 285 /** 286 * genphy_c45_read_pma - read link speed etc from PMA 287 * @phydev: target phy_device struct 288 */ 289 int genphy_c45_read_pma(struct phy_device *phydev) 290 { 291 int val; 292 293 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1); 294 if (val < 0) 295 return val; 296 297 switch (val & MDIO_CTRL1_SPEEDSEL) { 298 case 0: 299 phydev->speed = SPEED_10; 300 break; 301 case MDIO_PMA_CTRL1_SPEED100: 302 phydev->speed = SPEED_100; 303 break; 304 case MDIO_PMA_CTRL1_SPEED1000: 305 phydev->speed = SPEED_1000; 306 break; 307 case MDIO_CTRL1_SPEED2_5G: 308 phydev->speed = SPEED_2500; 309 break; 310 case MDIO_CTRL1_SPEED5G: 311 phydev->speed = SPEED_5000; 312 break; 313 case MDIO_CTRL1_SPEED10G: 314 phydev->speed = SPEED_10000; 315 break; 316 default: 317 phydev->speed = SPEED_UNKNOWN; 318 break; 319 } 320 321 phydev->duplex = DUPLEX_FULL; 322 323 return 0; 324 } 325 EXPORT_SYMBOL_GPL(genphy_c45_read_pma); 326 327 /** 328 * genphy_c45_read_mdix - read mdix status from PMA 329 * @phydev: target phy_device struct 330 */ 331 int genphy_c45_read_mdix(struct phy_device *phydev) 332 { 333 int val; 334 335 if (phydev->speed == SPEED_10000) { 336 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, 337 MDIO_PMA_10GBT_SWAPPOL); 338 if (val < 0) 339 return val; 340 341 switch (val) { 342 case MDIO_PMA_10GBT_SWAPPOL_ABNX | MDIO_PMA_10GBT_SWAPPOL_CDNX: 343 phydev->mdix = ETH_TP_MDI; 344 break; 345 346 case 0: 347 phydev->mdix = ETH_TP_MDI_X; 348 break; 349 350 default: 351 phydev->mdix = ETH_TP_MDI_INVALID; 352 break; 353 } 354 } 355 356 return 0; 357 } 358 EXPORT_SYMBOL_GPL(genphy_c45_read_mdix); 359 360 /** 361 * genphy_c45_pma_read_abilities - read supported link modes from PMA 362 * @phydev: target phy_device struct 363 * 364 * Read the supported link modes from the PMA Status 2 (1.8) register. If bit 365 * 1.8.9 is set, the list of supported modes is build using the values in the 366 * PMA Extended Abilities (1.11) register, indicating 1000BASET an 10G related 367 * modes. If bit 1.11.14 is set, then the list is also extended with the modes 368 * in the 2.5G/5G PMA Extended register (1.21), indicating if 2.5GBASET and 369 * 5GBASET are supported. 370 */ 371 int genphy_c45_pma_read_abilities(struct phy_device *phydev) 372 { 373 int val; 374 375 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported); 376 if (phydev->c45_ids.devices_in_package & MDIO_DEVS_AN) { 377 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); 378 if (val < 0) 379 return val; 380 381 if (val & MDIO_AN_STAT1_ABLE) 382 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 383 phydev->supported); 384 } 385 386 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT2); 387 if (val < 0) 388 return val; 389 390 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, 391 phydev->supported, 392 val & MDIO_PMA_STAT2_10GBSR); 393 394 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseLR_Full_BIT, 395 phydev->supported, 396 val & MDIO_PMA_STAT2_10GBLR); 397 398 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseER_Full_BIT, 399 phydev->supported, 400 val & MDIO_PMA_STAT2_10GBER); 401 402 if (val & MDIO_PMA_STAT2_EXTABLE) { 403 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE); 404 if (val < 0) 405 return val; 406 407 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT, 408 phydev->supported, 409 val & MDIO_PMA_EXTABLE_10GBLRM); 410 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 411 phydev->supported, 412 val & MDIO_PMA_EXTABLE_10GBT); 413 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT, 414 phydev->supported, 415 val & MDIO_PMA_EXTABLE_10GBKX4); 416 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, 417 phydev->supported, 418 val & MDIO_PMA_EXTABLE_10GBKR); 419 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 420 phydev->supported, 421 val & MDIO_PMA_EXTABLE_1000BT); 422 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, 423 phydev->supported, 424 val & MDIO_PMA_EXTABLE_1000BKX); 425 426 linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, 427 phydev->supported, 428 val & MDIO_PMA_EXTABLE_100BTX); 429 linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, 430 phydev->supported, 431 val & MDIO_PMA_EXTABLE_100BTX); 432 433 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, 434 phydev->supported, 435 val & MDIO_PMA_EXTABLE_10BT); 436 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, 437 phydev->supported, 438 val & MDIO_PMA_EXTABLE_10BT); 439 440 if (val & MDIO_PMA_EXTABLE_NBT) { 441 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, 442 MDIO_PMA_NG_EXTABLE); 443 if (val < 0) 444 return val; 445 446 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 447 phydev->supported, 448 val & MDIO_PMA_NG_EXTABLE_2_5GBT); 449 450 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 451 phydev->supported, 452 val & MDIO_PMA_NG_EXTABLE_5GBT); 453 } 454 } 455 456 return 0; 457 } 458 EXPORT_SYMBOL_GPL(genphy_c45_pma_read_abilities); 459 460 /** 461 * genphy_c45_read_status - read PHY status 462 * @phydev: target phy_device struct 463 * 464 * Reads status from PHY and sets phy_device members accordingly. 465 */ 466 int genphy_c45_read_status(struct phy_device *phydev) 467 { 468 int ret; 469 470 ret = genphy_c45_read_link(phydev); 471 if (ret) 472 return ret; 473 474 phydev->speed = SPEED_UNKNOWN; 475 phydev->duplex = DUPLEX_UNKNOWN; 476 phydev->pause = 0; 477 phydev->asym_pause = 0; 478 479 if (phydev->autoneg == AUTONEG_ENABLE) { 480 ret = genphy_c45_read_lpa(phydev); 481 if (ret) 482 return ret; 483 484 phy_resolve_aneg_linkmode(phydev); 485 } else { 486 ret = genphy_c45_read_pma(phydev); 487 } 488 489 return ret; 490 } 491 EXPORT_SYMBOL_GPL(genphy_c45_read_status); 492 493 /* The gen10g_* functions are the old Clause 45 stub */ 494 495 int gen10g_config_aneg(struct phy_device *phydev) 496 { 497 return 0; 498 } 499 EXPORT_SYMBOL_GPL(gen10g_config_aneg); 500 501 static int gen10g_read_status(struct phy_device *phydev) 502 { 503 /* For now just lie and say it's 10G all the time */ 504 phydev->speed = SPEED_10000; 505 phydev->duplex = DUPLEX_FULL; 506 507 return genphy_c45_read_link(phydev); 508 } 509 510 struct phy_driver genphy_10g_driver = { 511 .phy_id = 0xffffffff, 512 .phy_id_mask = 0xffffffff, 513 .name = "Generic 10G PHY", 514 .soft_reset = genphy_no_soft_reset, 515 .features = PHY_10GBIT_FEATURES, 516 .config_aneg = gen10g_config_aneg, 517 .read_status = gen10g_read_status, 518 }; 519