1*85e97f0bSBjarni Jonasson /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2*85e97f0bSBjarni Jonasson /* 3*85e97f0bSBjarni Jonasson * Driver for Microsemi VSC85xx PHYs 4*85e97f0bSBjarni Jonasson * 5*85e97f0bSBjarni Jonasson * Copyright (c) 2021 Microsemi Corporation 6*85e97f0bSBjarni Jonasson */ 7*85e97f0bSBjarni Jonasson 8*85e97f0bSBjarni Jonasson #ifndef _MSCC_SERDES_PHY_H_ 9*85e97f0bSBjarni Jonasson #define _MSCC_SERDES_PHY_H_ 10*85e97f0bSBjarni Jonasson 11*85e97f0bSBjarni Jonasson #define PHY_S6G_PLL5G_CFG2_GAIN_MASK GENMASK(9, 5) 12*85e97f0bSBjarni Jonasson #define PHY_S6G_PLL5G_CFG2_ENA_GAIN 1 13*85e97f0bSBjarni Jonasson 14*85e97f0bSBjarni Jonasson #define PHY_S6G_DES_PHY_CTRL_POS 13 15*85e97f0bSBjarni Jonasson #define PHY_S6G_DES_MBTR_CTRL_POS 10 16*85e97f0bSBjarni Jonasson #define PHY_S6G_DES_CPMD_SEL_POS 8 17*85e97f0bSBjarni Jonasson #define PHY_S6G_DES_BW_HYST_POS 5 18*85e97f0bSBjarni Jonasson #define PHY_S6G_DES_BW_ANA_POS 1 19*85e97f0bSBjarni Jonasson #define PHY_S6G_DES_CFG 0x21 20*85e97f0bSBjarni Jonasson #define PHY_S6G_IB_CFG0 0x22 21*85e97f0bSBjarni Jonasson #define PHY_S6G_IB_CFG1 0x23 22*85e97f0bSBjarni Jonasson #define PHY_S6G_IB_CFG2 0x24 23*85e97f0bSBjarni Jonasson #define PHY_S6G_IB_CFG3 0x25 24*85e97f0bSBjarni Jonasson #define PHY_S6G_IB_CFG4 0x26 25*85e97f0bSBjarni Jonasson #define PHY_S6G_GP_CFG 0x2E 26*85e97f0bSBjarni Jonasson #define PHY_S6G_DFT_CFG0 0x35 27*85e97f0bSBjarni Jonasson #define PHY_S6G_IB_DFT_CFG2 0x37 28*85e97f0bSBjarni Jonasson 29*85e97f0bSBjarni Jonasson int vsc85xx_sd6g_config_v2(struct phy_device *phydev); 30*85e97f0bSBjarni Jonasson 31*85e97f0bSBjarni Jonasson #endif /* _MSCC_PHY_SERDES_H_ */ 32