1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Driver for Microsemi VSC85xx PHYs 4 * 5 * Author: Nagaraju Lakkaraju 6 * License: Dual MIT/GPL 7 * Copyright (c) 2016 Microsemi Corporation 8 */ 9 10 #include <linux/firmware.h> 11 #include <linux/jiffies.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/mdio.h> 15 #include <linux/mii.h> 16 #include <linux/phy.h> 17 #include <linux/of.h> 18 #include <linux/netdevice.h> 19 #include <dt-bindings/net/mscc-phy-vsc8531.h> 20 #include "mscc_serdes.h" 21 #include "mscc.h" 22 23 static const struct vsc85xx_hw_stat vsc85xx_hw_stats[] = { 24 { 25 .string = "phy_receive_errors", 26 .reg = MSCC_PHY_ERR_RX_CNT, 27 .page = MSCC_PHY_PAGE_STANDARD, 28 .mask = ERR_CNT_MASK, 29 }, { 30 .string = "phy_false_carrier", 31 .reg = MSCC_PHY_ERR_FALSE_CARRIER_CNT, 32 .page = MSCC_PHY_PAGE_STANDARD, 33 .mask = ERR_CNT_MASK, 34 }, { 35 .string = "phy_cu_media_link_disconnect", 36 .reg = MSCC_PHY_ERR_LINK_DISCONNECT_CNT, 37 .page = MSCC_PHY_PAGE_STANDARD, 38 .mask = ERR_CNT_MASK, 39 }, { 40 .string = "phy_cu_media_crc_good_count", 41 .reg = MSCC_PHY_CU_MEDIA_CRC_VALID_CNT, 42 .page = MSCC_PHY_PAGE_EXTENDED, 43 .mask = VALID_CRC_CNT_CRC_MASK, 44 }, { 45 .string = "phy_cu_media_crc_error_count", 46 .reg = MSCC_PHY_EXT_PHY_CNTL_4, 47 .page = MSCC_PHY_PAGE_EXTENDED, 48 .mask = ERR_CNT_MASK, 49 }, 50 }; 51 52 static const struct vsc85xx_hw_stat vsc8584_hw_stats[] = { 53 { 54 .string = "phy_receive_errors", 55 .reg = MSCC_PHY_ERR_RX_CNT, 56 .page = MSCC_PHY_PAGE_STANDARD, 57 .mask = ERR_CNT_MASK, 58 }, { 59 .string = "phy_false_carrier", 60 .reg = MSCC_PHY_ERR_FALSE_CARRIER_CNT, 61 .page = MSCC_PHY_PAGE_STANDARD, 62 .mask = ERR_CNT_MASK, 63 }, { 64 .string = "phy_cu_media_link_disconnect", 65 .reg = MSCC_PHY_ERR_LINK_DISCONNECT_CNT, 66 .page = MSCC_PHY_PAGE_STANDARD, 67 .mask = ERR_CNT_MASK, 68 }, { 69 .string = "phy_cu_media_crc_good_count", 70 .reg = MSCC_PHY_CU_MEDIA_CRC_VALID_CNT, 71 .page = MSCC_PHY_PAGE_EXTENDED, 72 .mask = VALID_CRC_CNT_CRC_MASK, 73 }, { 74 .string = "phy_cu_media_crc_error_count", 75 .reg = MSCC_PHY_EXT_PHY_CNTL_4, 76 .page = MSCC_PHY_PAGE_EXTENDED, 77 .mask = ERR_CNT_MASK, 78 }, { 79 .string = "phy_serdes_tx_good_pkt_count", 80 .reg = MSCC_PHY_SERDES_TX_VALID_CNT, 81 .page = MSCC_PHY_PAGE_EXTENDED_3, 82 .mask = VALID_CRC_CNT_CRC_MASK, 83 }, { 84 .string = "phy_serdes_tx_bad_crc_count", 85 .reg = MSCC_PHY_SERDES_TX_CRC_ERR_CNT, 86 .page = MSCC_PHY_PAGE_EXTENDED_3, 87 .mask = ERR_CNT_MASK, 88 }, { 89 .string = "phy_serdes_rx_good_pkt_count", 90 .reg = MSCC_PHY_SERDES_RX_VALID_CNT, 91 .page = MSCC_PHY_PAGE_EXTENDED_3, 92 .mask = VALID_CRC_CNT_CRC_MASK, 93 }, { 94 .string = "phy_serdes_rx_bad_crc_count", 95 .reg = MSCC_PHY_SERDES_RX_CRC_ERR_CNT, 96 .page = MSCC_PHY_PAGE_EXTENDED_3, 97 .mask = ERR_CNT_MASK, 98 }, 99 }; 100 101 #if IS_ENABLED(CONFIG_OF_MDIO) 102 static const struct vsc8531_edge_rate_table edge_table[] = { 103 {MSCC_VDDMAC_3300, { 0, 2, 4, 7, 10, 17, 29, 53} }, 104 {MSCC_VDDMAC_2500, { 0, 3, 6, 10, 14, 23, 37, 63} }, 105 {MSCC_VDDMAC_1800, { 0, 5, 9, 16, 23, 35, 52, 76} }, 106 {MSCC_VDDMAC_1500, { 0, 6, 14, 21, 29, 42, 58, 77} }, 107 }; 108 #endif 109 110 static int vsc85xx_phy_read_page(struct phy_device *phydev) 111 { 112 return __phy_read(phydev, MSCC_EXT_PAGE_ACCESS); 113 } 114 115 static int vsc85xx_phy_write_page(struct phy_device *phydev, int page) 116 { 117 return __phy_write(phydev, MSCC_EXT_PAGE_ACCESS, page); 118 } 119 120 static int vsc85xx_get_sset_count(struct phy_device *phydev) 121 { 122 struct vsc8531_private *priv = phydev->priv; 123 124 if (!priv) 125 return 0; 126 127 return priv->nstats; 128 } 129 130 static void vsc85xx_get_strings(struct phy_device *phydev, u8 *data) 131 { 132 struct vsc8531_private *priv = phydev->priv; 133 int i; 134 135 if (!priv) 136 return; 137 138 for (i = 0; i < priv->nstats; i++) 139 strlcpy(data + i * ETH_GSTRING_LEN, priv->hw_stats[i].string, 140 ETH_GSTRING_LEN); 141 } 142 143 static u64 vsc85xx_get_stat(struct phy_device *phydev, int i) 144 { 145 struct vsc8531_private *priv = phydev->priv; 146 int val; 147 148 val = phy_read_paged(phydev, priv->hw_stats[i].page, 149 priv->hw_stats[i].reg); 150 if (val < 0) 151 return U64_MAX; 152 153 val = val & priv->hw_stats[i].mask; 154 priv->stats[i] += val; 155 156 return priv->stats[i]; 157 } 158 159 static void vsc85xx_get_stats(struct phy_device *phydev, 160 struct ethtool_stats *stats, u64 *data) 161 { 162 struct vsc8531_private *priv = phydev->priv; 163 int i; 164 165 if (!priv) 166 return; 167 168 for (i = 0; i < priv->nstats; i++) 169 data[i] = vsc85xx_get_stat(phydev, i); 170 } 171 172 static int vsc85xx_led_cntl_set(struct phy_device *phydev, 173 u8 led_num, 174 u8 mode) 175 { 176 int rc; 177 u16 reg_val; 178 179 mutex_lock(&phydev->lock); 180 reg_val = phy_read(phydev, MSCC_PHY_LED_MODE_SEL); 181 reg_val &= ~LED_MODE_SEL_MASK(led_num); 182 reg_val |= LED_MODE_SEL(led_num, (u16)mode); 183 rc = phy_write(phydev, MSCC_PHY_LED_MODE_SEL, reg_val); 184 mutex_unlock(&phydev->lock); 185 186 return rc; 187 } 188 189 static int vsc85xx_mdix_get(struct phy_device *phydev, u8 *mdix) 190 { 191 u16 reg_val; 192 193 reg_val = phy_read(phydev, MSCC_PHY_DEV_AUX_CNTL); 194 if (reg_val & HP_AUTO_MDIX_X_OVER_IND_MASK) 195 *mdix = ETH_TP_MDI_X; 196 else 197 *mdix = ETH_TP_MDI; 198 199 return 0; 200 } 201 202 static int vsc85xx_mdix_set(struct phy_device *phydev, u8 mdix) 203 { 204 int rc; 205 u16 reg_val; 206 207 reg_val = phy_read(phydev, MSCC_PHY_BYPASS_CONTROL); 208 if (mdix == ETH_TP_MDI || mdix == ETH_TP_MDI_X) { 209 reg_val |= (DISABLE_PAIR_SWAP_CORR_MASK | 210 DISABLE_POLARITY_CORR_MASK | 211 DISABLE_HP_AUTO_MDIX_MASK); 212 } else { 213 reg_val &= ~(DISABLE_PAIR_SWAP_CORR_MASK | 214 DISABLE_POLARITY_CORR_MASK | 215 DISABLE_HP_AUTO_MDIX_MASK); 216 } 217 rc = phy_write(phydev, MSCC_PHY_BYPASS_CONTROL, reg_val); 218 if (rc) 219 return rc; 220 221 reg_val = 0; 222 223 if (mdix == ETH_TP_MDI) 224 reg_val = FORCE_MDI_CROSSOVER_MDI; 225 else if (mdix == ETH_TP_MDI_X) 226 reg_val = FORCE_MDI_CROSSOVER_MDIX; 227 228 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED, 229 MSCC_PHY_EXT_MODE_CNTL, FORCE_MDI_CROSSOVER_MASK, 230 reg_val); 231 if (rc < 0) 232 return rc; 233 234 return genphy_restart_aneg(phydev); 235 } 236 237 static int vsc85xx_downshift_get(struct phy_device *phydev, u8 *count) 238 { 239 int reg_val; 240 241 reg_val = phy_read_paged(phydev, MSCC_PHY_PAGE_EXTENDED, 242 MSCC_PHY_ACTIPHY_CNTL); 243 if (reg_val < 0) 244 return reg_val; 245 246 reg_val &= DOWNSHIFT_CNTL_MASK; 247 if (!(reg_val & DOWNSHIFT_EN)) 248 *count = DOWNSHIFT_DEV_DISABLE; 249 else 250 *count = ((reg_val & ~DOWNSHIFT_EN) >> DOWNSHIFT_CNTL_POS) + 2; 251 252 return 0; 253 } 254 255 static int vsc85xx_downshift_set(struct phy_device *phydev, u8 count) 256 { 257 if (count == DOWNSHIFT_DEV_DEFAULT_COUNT) { 258 /* Default downshift count 3 (i.e. Bit3:2 = 0b01) */ 259 count = ((1 << DOWNSHIFT_CNTL_POS) | DOWNSHIFT_EN); 260 } else if (count > DOWNSHIFT_COUNT_MAX || count == 1) { 261 phydev_err(phydev, "Downshift count should be 2,3,4 or 5\n"); 262 return -ERANGE; 263 } else if (count) { 264 /* Downshift count is either 2,3,4 or 5 */ 265 count = (((count - 2) << DOWNSHIFT_CNTL_POS) | DOWNSHIFT_EN); 266 } 267 268 return phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED, 269 MSCC_PHY_ACTIPHY_CNTL, DOWNSHIFT_CNTL_MASK, 270 count); 271 } 272 273 static int vsc85xx_wol_set(struct phy_device *phydev, 274 struct ethtool_wolinfo *wol) 275 { 276 int rc; 277 u16 reg_val; 278 u8 i; 279 u16 pwd[3] = {0, 0, 0}; 280 struct ethtool_wolinfo *wol_conf = wol; 281 u8 *mac_addr = phydev->attached_dev->dev_addr; 282 283 mutex_lock(&phydev->lock); 284 rc = phy_select_page(phydev, MSCC_PHY_PAGE_EXTENDED_2); 285 if (rc < 0) { 286 rc = phy_restore_page(phydev, rc, rc); 287 goto out_unlock; 288 } 289 290 if (wol->wolopts & WAKE_MAGIC) { 291 /* Store the device address for the magic packet */ 292 for (i = 0; i < ARRAY_SIZE(pwd); i++) 293 pwd[i] = mac_addr[5 - (i * 2 + 1)] << 8 | 294 mac_addr[5 - i * 2]; 295 __phy_write(phydev, MSCC_PHY_WOL_LOWER_MAC_ADDR, pwd[0]); 296 __phy_write(phydev, MSCC_PHY_WOL_MID_MAC_ADDR, pwd[1]); 297 __phy_write(phydev, MSCC_PHY_WOL_UPPER_MAC_ADDR, pwd[2]); 298 } else { 299 __phy_write(phydev, MSCC_PHY_WOL_LOWER_MAC_ADDR, 0); 300 __phy_write(phydev, MSCC_PHY_WOL_MID_MAC_ADDR, 0); 301 __phy_write(phydev, MSCC_PHY_WOL_UPPER_MAC_ADDR, 0); 302 } 303 304 if (wol_conf->wolopts & WAKE_MAGICSECURE) { 305 for (i = 0; i < ARRAY_SIZE(pwd); i++) 306 pwd[i] = wol_conf->sopass[5 - (i * 2 + 1)] << 8 | 307 wol_conf->sopass[5 - i * 2]; 308 __phy_write(phydev, MSCC_PHY_WOL_LOWER_PASSWD, pwd[0]); 309 __phy_write(phydev, MSCC_PHY_WOL_MID_PASSWD, pwd[1]); 310 __phy_write(phydev, MSCC_PHY_WOL_UPPER_PASSWD, pwd[2]); 311 } else { 312 __phy_write(phydev, MSCC_PHY_WOL_LOWER_PASSWD, 0); 313 __phy_write(phydev, MSCC_PHY_WOL_MID_PASSWD, 0); 314 __phy_write(phydev, MSCC_PHY_WOL_UPPER_PASSWD, 0); 315 } 316 317 reg_val = __phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL); 318 if (wol_conf->wolopts & WAKE_MAGICSECURE) 319 reg_val |= SECURE_ON_ENABLE; 320 else 321 reg_val &= ~SECURE_ON_ENABLE; 322 __phy_write(phydev, MSCC_PHY_WOL_MAC_CONTROL, reg_val); 323 324 rc = phy_restore_page(phydev, rc, rc > 0 ? 0 : rc); 325 if (rc < 0) 326 goto out_unlock; 327 328 if (wol->wolopts & WAKE_MAGIC) { 329 /* Enable the WOL interrupt */ 330 reg_val = phy_read(phydev, MII_VSC85XX_INT_MASK); 331 reg_val |= MII_VSC85XX_INT_MASK_WOL; 332 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, reg_val); 333 if (rc) 334 goto out_unlock; 335 } else { 336 /* Disable the WOL interrupt */ 337 reg_val = phy_read(phydev, MII_VSC85XX_INT_MASK); 338 reg_val &= (~MII_VSC85XX_INT_MASK_WOL); 339 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, reg_val); 340 if (rc) 341 goto out_unlock; 342 } 343 /* Clear WOL iterrupt status */ 344 reg_val = phy_read(phydev, MII_VSC85XX_INT_STATUS); 345 346 out_unlock: 347 mutex_unlock(&phydev->lock); 348 349 return rc; 350 } 351 352 static void vsc85xx_wol_get(struct phy_device *phydev, 353 struct ethtool_wolinfo *wol) 354 { 355 int rc; 356 u16 reg_val; 357 u8 i; 358 u16 pwd[3] = {0, 0, 0}; 359 struct ethtool_wolinfo *wol_conf = wol; 360 361 mutex_lock(&phydev->lock); 362 rc = phy_select_page(phydev, MSCC_PHY_PAGE_EXTENDED_2); 363 if (rc < 0) 364 goto out_unlock; 365 366 reg_val = __phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL); 367 if (reg_val & SECURE_ON_ENABLE) 368 wol_conf->wolopts |= WAKE_MAGICSECURE; 369 if (wol_conf->wolopts & WAKE_MAGICSECURE) { 370 pwd[0] = __phy_read(phydev, MSCC_PHY_WOL_LOWER_PASSWD); 371 pwd[1] = __phy_read(phydev, MSCC_PHY_WOL_MID_PASSWD); 372 pwd[2] = __phy_read(phydev, MSCC_PHY_WOL_UPPER_PASSWD); 373 for (i = 0; i < ARRAY_SIZE(pwd); i++) { 374 wol_conf->sopass[5 - i * 2] = pwd[i] & 0x00ff; 375 wol_conf->sopass[5 - (i * 2 + 1)] = (pwd[i] & 0xff00) 376 >> 8; 377 } 378 } 379 380 out_unlock: 381 phy_restore_page(phydev, rc, rc > 0 ? 0 : rc); 382 mutex_unlock(&phydev->lock); 383 } 384 385 #if IS_ENABLED(CONFIG_OF_MDIO) 386 static int vsc85xx_edge_rate_magic_get(struct phy_device *phydev) 387 { 388 u32 vdd, sd; 389 int i, j; 390 struct device *dev = &phydev->mdio.dev; 391 struct device_node *of_node = dev->of_node; 392 u8 sd_array_size = ARRAY_SIZE(edge_table[0].slowdown); 393 394 if (!of_node) 395 return -ENODEV; 396 397 if (of_property_read_u32(of_node, "vsc8531,vddmac", &vdd)) 398 vdd = MSCC_VDDMAC_3300; 399 400 if (of_property_read_u32(of_node, "vsc8531,edge-slowdown", &sd)) 401 sd = 0; 402 403 for (i = 0; i < ARRAY_SIZE(edge_table); i++) 404 if (edge_table[i].vddmac == vdd) 405 for (j = 0; j < sd_array_size; j++) 406 if (edge_table[i].slowdown[j] == sd) 407 return (sd_array_size - j - 1); 408 409 return -EINVAL; 410 } 411 412 static int vsc85xx_dt_led_mode_get(struct phy_device *phydev, 413 char *led, 414 u32 default_mode) 415 { 416 struct vsc8531_private *priv = phydev->priv; 417 struct device *dev = &phydev->mdio.dev; 418 struct device_node *of_node = dev->of_node; 419 u32 led_mode; 420 int err; 421 422 if (!of_node) 423 return -ENODEV; 424 425 led_mode = default_mode; 426 err = of_property_read_u32(of_node, led, &led_mode); 427 if (!err && !(BIT(led_mode) & priv->supp_led_modes)) { 428 phydev_err(phydev, "DT %s invalid\n", led); 429 return -EINVAL; 430 } 431 432 return led_mode; 433 } 434 435 #else 436 static int vsc85xx_edge_rate_magic_get(struct phy_device *phydev) 437 { 438 return 0; 439 } 440 441 static int vsc85xx_dt_led_mode_get(struct phy_device *phydev, 442 char *led, 443 u8 default_mode) 444 { 445 return default_mode; 446 } 447 #endif /* CONFIG_OF_MDIO */ 448 449 static int vsc85xx_dt_led_modes_get(struct phy_device *phydev, 450 u32 *default_mode) 451 { 452 struct vsc8531_private *priv = phydev->priv; 453 char led_dt_prop[28]; 454 int i, ret; 455 456 for (i = 0; i < priv->nleds; i++) { 457 ret = sprintf(led_dt_prop, "vsc8531,led-%d-mode", i); 458 if (ret < 0) 459 return ret; 460 461 ret = vsc85xx_dt_led_mode_get(phydev, led_dt_prop, 462 default_mode[i]); 463 if (ret < 0) 464 return ret; 465 priv->leds_mode[i] = ret; 466 } 467 468 return 0; 469 } 470 471 static int vsc85xx_edge_rate_cntl_set(struct phy_device *phydev, u8 edge_rate) 472 { 473 int rc; 474 475 mutex_lock(&phydev->lock); 476 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED_2, 477 MSCC_PHY_WOL_MAC_CONTROL, EDGE_RATE_CNTL_MASK, 478 edge_rate << EDGE_RATE_CNTL_POS); 479 mutex_unlock(&phydev->lock); 480 481 return rc; 482 } 483 484 static int vsc85xx_mac_if_set(struct phy_device *phydev, 485 phy_interface_t interface) 486 { 487 int rc; 488 u16 reg_val; 489 490 mutex_lock(&phydev->lock); 491 reg_val = phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_1); 492 reg_val &= ~(MAC_IF_SELECTION_MASK); 493 switch (interface) { 494 case PHY_INTERFACE_MODE_RGMII_TXID: 495 case PHY_INTERFACE_MODE_RGMII_RXID: 496 case PHY_INTERFACE_MODE_RGMII_ID: 497 case PHY_INTERFACE_MODE_RGMII: 498 reg_val |= (MAC_IF_SELECTION_RGMII << MAC_IF_SELECTION_POS); 499 break; 500 case PHY_INTERFACE_MODE_RMII: 501 reg_val |= (MAC_IF_SELECTION_RMII << MAC_IF_SELECTION_POS); 502 break; 503 case PHY_INTERFACE_MODE_MII: 504 case PHY_INTERFACE_MODE_GMII: 505 reg_val |= (MAC_IF_SELECTION_GMII << MAC_IF_SELECTION_POS); 506 break; 507 default: 508 rc = -EINVAL; 509 goto out_unlock; 510 } 511 rc = phy_write(phydev, MSCC_PHY_EXT_PHY_CNTL_1, reg_val); 512 if (rc) 513 goto out_unlock; 514 515 rc = genphy_soft_reset(phydev); 516 517 out_unlock: 518 mutex_unlock(&phydev->lock); 519 520 return rc; 521 } 522 523 /* Set the RGMII RX and TX clock skews individually, according to the PHY 524 * interface type, to: 525 * * 0.2 ns (their default, and lowest, hardware value) if delays should 526 * not be enabled 527 * * 2.0 ns (which causes the data to be sampled at exactly half way between 528 * clock transitions at 1000 Mbps) if delays should be enabled 529 */ 530 static int vsc85xx_rgmii_set_skews(struct phy_device *phydev, u32 rgmii_cntl, 531 u16 rgmii_rx_delay_mask, 532 u16 rgmii_tx_delay_mask) 533 { 534 u16 rgmii_rx_delay_pos = ffs(rgmii_rx_delay_mask) - 1; 535 u16 rgmii_tx_delay_pos = ffs(rgmii_tx_delay_mask) - 1; 536 u16 reg_val = 0; 537 int rc; 538 539 mutex_lock(&phydev->lock); 540 541 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID || 542 phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) 543 reg_val |= RGMII_CLK_DELAY_2_0_NS << rgmii_rx_delay_pos; 544 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID || 545 phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) 546 reg_val |= RGMII_CLK_DELAY_2_0_NS << rgmii_tx_delay_pos; 547 548 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED_2, 549 rgmii_cntl, 550 rgmii_rx_delay_mask | rgmii_tx_delay_mask, 551 reg_val); 552 553 mutex_unlock(&phydev->lock); 554 555 return rc; 556 } 557 558 static int vsc85xx_default_config(struct phy_device *phydev) 559 { 560 int rc; 561 562 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; 563 564 if (phy_interface_mode_is_rgmii(phydev->interface)) { 565 rc = vsc85xx_rgmii_set_skews(phydev, VSC8502_RGMII_CNTL, 566 VSC8502_RGMII_RX_DELAY_MASK, 567 VSC8502_RGMII_TX_DELAY_MASK); 568 if (rc) 569 return rc; 570 } 571 572 return 0; 573 } 574 575 static int vsc85xx_get_tunable(struct phy_device *phydev, 576 struct ethtool_tunable *tuna, void *data) 577 { 578 switch (tuna->id) { 579 case ETHTOOL_PHY_DOWNSHIFT: 580 return vsc85xx_downshift_get(phydev, (u8 *)data); 581 default: 582 return -EINVAL; 583 } 584 } 585 586 static int vsc85xx_set_tunable(struct phy_device *phydev, 587 struct ethtool_tunable *tuna, 588 const void *data) 589 { 590 switch (tuna->id) { 591 case ETHTOOL_PHY_DOWNSHIFT: 592 return vsc85xx_downshift_set(phydev, *(u8 *)data); 593 default: 594 return -EINVAL; 595 } 596 } 597 598 /* mdiobus lock should be locked when using this function */ 599 static void vsc85xx_tr_write(struct phy_device *phydev, u16 addr, u32 val) 600 { 601 __phy_write(phydev, MSCC_PHY_TR_MSB, val >> 16); 602 __phy_write(phydev, MSCC_PHY_TR_LSB, val & GENMASK(15, 0)); 603 __phy_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(addr)); 604 } 605 606 static int vsc8531_pre_init_seq_set(struct phy_device *phydev) 607 { 608 int rc; 609 static const struct reg_val init_seq[] = { 610 {0x0f90, 0x00688980}, 611 {0x0696, 0x00000003}, 612 {0x07fa, 0x0050100f}, 613 {0x1686, 0x00000004}, 614 }; 615 unsigned int i; 616 int oldpage; 617 618 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_STANDARD, 619 MSCC_PHY_EXT_CNTL_STATUS, SMI_BROADCAST_WR_EN, 620 SMI_BROADCAST_WR_EN); 621 if (rc < 0) 622 return rc; 623 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_TEST, 624 MSCC_PHY_TEST_PAGE_24, 0, 0x0400); 625 if (rc < 0) 626 return rc; 627 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_TEST, 628 MSCC_PHY_TEST_PAGE_5, 0x0a00, 0x0e00); 629 if (rc < 0) 630 return rc; 631 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_TEST, 632 MSCC_PHY_TEST_PAGE_8, TR_CLK_DISABLE, TR_CLK_DISABLE); 633 if (rc < 0) 634 return rc; 635 636 mutex_lock(&phydev->lock); 637 oldpage = phy_select_page(phydev, MSCC_PHY_PAGE_TR); 638 if (oldpage < 0) 639 goto out_unlock; 640 641 for (i = 0; i < ARRAY_SIZE(init_seq); i++) 642 vsc85xx_tr_write(phydev, init_seq[i].reg, init_seq[i].val); 643 644 out_unlock: 645 oldpage = phy_restore_page(phydev, oldpage, oldpage); 646 mutex_unlock(&phydev->lock); 647 648 return oldpage; 649 } 650 651 static int vsc85xx_eee_init_seq_set(struct phy_device *phydev) 652 { 653 static const struct reg_val init_eee[] = { 654 {0x0f82, 0x0012b00a}, 655 {0x1686, 0x00000004}, 656 {0x168c, 0x00d2c46f}, 657 {0x17a2, 0x00000620}, 658 {0x16a0, 0x00eeffdd}, 659 {0x16a6, 0x00071448}, 660 {0x16a4, 0x0013132f}, 661 {0x16a8, 0x00000000}, 662 {0x0ffc, 0x00c0a028}, 663 {0x0fe8, 0x0091b06c}, 664 {0x0fea, 0x00041600}, 665 {0x0f80, 0x00000af4}, 666 {0x0fec, 0x00901809}, 667 {0x0fee, 0x0000a6a1}, 668 {0x0ffe, 0x00b01007}, 669 {0x16b0, 0x00eeff00}, 670 {0x16b2, 0x00007000}, 671 {0x16b4, 0x00000814}, 672 }; 673 unsigned int i; 674 int oldpage; 675 676 mutex_lock(&phydev->lock); 677 oldpage = phy_select_page(phydev, MSCC_PHY_PAGE_TR); 678 if (oldpage < 0) 679 goto out_unlock; 680 681 for (i = 0; i < ARRAY_SIZE(init_eee); i++) 682 vsc85xx_tr_write(phydev, init_eee[i].reg, init_eee[i].val); 683 684 out_unlock: 685 oldpage = phy_restore_page(phydev, oldpage, oldpage); 686 mutex_unlock(&phydev->lock); 687 688 return oldpage; 689 } 690 691 /* phydev->bus->mdio_lock should be locked when using this function */ 692 int phy_base_write(struct phy_device *phydev, u32 regnum, u16 val) 693 { 694 if (unlikely(!mutex_is_locked(&phydev->mdio.bus->mdio_lock))) { 695 dev_err(&phydev->mdio.dev, "MDIO bus lock not held!\n"); 696 dump_stack(); 697 } 698 699 return __phy_package_write(phydev, regnum, val); 700 } 701 702 /* phydev->bus->mdio_lock should be locked when using this function */ 703 int phy_base_read(struct phy_device *phydev, u32 regnum) 704 { 705 if (unlikely(!mutex_is_locked(&phydev->mdio.bus->mdio_lock))) { 706 dev_err(&phydev->mdio.dev, "MDIO bus lock not held!\n"); 707 dump_stack(); 708 } 709 710 return __phy_package_read(phydev, regnum); 711 } 712 713 u32 vsc85xx_csr_read(struct phy_device *phydev, 714 enum csr_target target, u32 reg) 715 { 716 unsigned long deadline; 717 u32 val, val_l, val_h; 718 719 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_CSR_CNTL); 720 721 /* CSR registers are grouped under different Target IDs. 722 * 6-bit Target_ID is split between MSCC_EXT_PAGE_CSR_CNTL_20 and 723 * MSCC_EXT_PAGE_CSR_CNTL_19 registers. 724 * Target_ID[5:2] maps to bits[3:0] of MSCC_EXT_PAGE_CSR_CNTL_20 725 * and Target_ID[1:0] maps to bits[13:12] of MSCC_EXT_PAGE_CSR_CNTL_19. 726 */ 727 728 /* Setup the Target ID */ 729 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_20, 730 MSCC_PHY_CSR_CNTL_20_TARGET(target >> 2)); 731 732 if ((target >> 2 == 0x1) || (target >> 2 == 0x3)) 733 /* non-MACsec access */ 734 target &= 0x3; 735 else 736 target = 0; 737 738 /* Trigger CSR Action - Read into the CSR's */ 739 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_19, 740 MSCC_PHY_CSR_CNTL_19_CMD | MSCC_PHY_CSR_CNTL_19_READ | 741 MSCC_PHY_CSR_CNTL_19_REG_ADDR(reg) | 742 MSCC_PHY_CSR_CNTL_19_TARGET(target)); 743 744 /* Wait for register access*/ 745 deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS); 746 do { 747 usleep_range(500, 1000); 748 val = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_19); 749 } while (time_before(jiffies, deadline) && 750 !(val & MSCC_PHY_CSR_CNTL_19_CMD)); 751 752 if (!(val & MSCC_PHY_CSR_CNTL_19_CMD)) 753 return 0xffffffff; 754 755 /* Read the Least Significant Word (LSW) (17) */ 756 val_l = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_17); 757 758 /* Read the Most Significant Word (MSW) (18) */ 759 val_h = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_18); 760 761 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, 762 MSCC_PHY_PAGE_STANDARD); 763 764 return (val_h << 16) | val_l; 765 } 766 767 int vsc85xx_csr_write(struct phy_device *phydev, 768 enum csr_target target, u32 reg, u32 val) 769 { 770 unsigned long deadline; 771 772 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_CSR_CNTL); 773 774 /* CSR registers are grouped under different Target IDs. 775 * 6-bit Target_ID is split between MSCC_EXT_PAGE_CSR_CNTL_20 and 776 * MSCC_EXT_PAGE_CSR_CNTL_19 registers. 777 * Target_ID[5:2] maps to bits[3:0] of MSCC_EXT_PAGE_CSR_CNTL_20 778 * and Target_ID[1:0] maps to bits[13:12] of MSCC_EXT_PAGE_CSR_CNTL_19. 779 */ 780 781 /* Setup the Target ID */ 782 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_20, 783 MSCC_PHY_CSR_CNTL_20_TARGET(target >> 2)); 784 785 /* Write the Least Significant Word (LSW) (17) */ 786 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_17, (u16)val); 787 788 /* Write the Most Significant Word (MSW) (18) */ 789 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_18, (u16)(val >> 16)); 790 791 if ((target >> 2 == 0x1) || (target >> 2 == 0x3)) 792 /* non-MACsec access */ 793 target &= 0x3; 794 else 795 target = 0; 796 797 /* Trigger CSR Action - Write into the CSR's */ 798 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_19, 799 MSCC_PHY_CSR_CNTL_19_CMD | 800 MSCC_PHY_CSR_CNTL_19_REG_ADDR(reg) | 801 MSCC_PHY_CSR_CNTL_19_TARGET(target)); 802 803 /* Wait for register access */ 804 deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS); 805 do { 806 usleep_range(500, 1000); 807 val = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_19); 808 } while (time_before(jiffies, deadline) && 809 !(val & MSCC_PHY_CSR_CNTL_19_CMD)); 810 811 if (!(val & MSCC_PHY_CSR_CNTL_19_CMD)) 812 return -ETIMEDOUT; 813 814 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, 815 MSCC_PHY_PAGE_STANDARD); 816 817 return 0; 818 } 819 820 /* bus->mdio_lock should be locked when using this function */ 821 static void vsc8584_csr_write(struct phy_device *phydev, u16 addr, u32 val) 822 { 823 phy_base_write(phydev, MSCC_PHY_TR_MSB, val >> 16); 824 phy_base_write(phydev, MSCC_PHY_TR_LSB, val & GENMASK(15, 0)); 825 phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(addr)); 826 } 827 828 /* bus->mdio_lock should be locked when using this function */ 829 int vsc8584_cmd(struct phy_device *phydev, u16 val) 830 { 831 unsigned long deadline; 832 u16 reg_val; 833 834 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, 835 MSCC_PHY_PAGE_EXTENDED_GPIO); 836 837 phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_NCOMPLETED | val); 838 839 deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS); 840 do { 841 reg_val = phy_base_read(phydev, MSCC_PHY_PROC_CMD); 842 } while (time_before(jiffies, deadline) && 843 (reg_val & PROC_CMD_NCOMPLETED) && 844 !(reg_val & PROC_CMD_FAILED)); 845 846 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 847 848 if (reg_val & PROC_CMD_FAILED) 849 return -EIO; 850 851 if (reg_val & PROC_CMD_NCOMPLETED) 852 return -ETIMEDOUT; 853 854 return 0; 855 } 856 857 /* bus->mdio_lock should be locked when using this function */ 858 static int vsc8584_micro_deassert_reset(struct phy_device *phydev, 859 bool patch_en) 860 { 861 u32 enable, release; 862 863 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, 864 MSCC_PHY_PAGE_EXTENDED_GPIO); 865 866 enable = RUN_FROM_INT_ROM | MICRO_CLK_EN | DW8051_CLK_EN; 867 release = MICRO_NSOFT_RESET | RUN_FROM_INT_ROM | DW8051_CLK_EN | 868 MICRO_CLK_EN; 869 870 if (patch_en) { 871 enable |= MICRO_PATCH_EN; 872 release |= MICRO_PATCH_EN; 873 874 /* Clear all patches */ 875 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_RAM); 876 } 877 878 /* Enable 8051 Micro clock; CLEAR/SET patch present; disable PRAM clock 879 * override and addr. auto-incr; operate at 125 MHz 880 */ 881 phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, enable); 882 /* Release 8051 Micro SW reset */ 883 phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, release); 884 885 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 886 887 return 0; 888 } 889 890 /* bus->mdio_lock should be locked when using this function */ 891 static int vsc8584_micro_assert_reset(struct phy_device *phydev) 892 { 893 int ret; 894 u16 reg; 895 896 ret = vsc8584_cmd(phydev, PROC_CMD_NOP); 897 if (ret) 898 return ret; 899 900 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, 901 MSCC_PHY_PAGE_EXTENDED_GPIO); 902 903 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL); 904 reg &= ~EN_PATCH_RAM_TRAP_ADDR(4); 905 phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg); 906 907 phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(4), 0x005b); 908 phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(4), 0x005b); 909 910 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL); 911 reg |= EN_PATCH_RAM_TRAP_ADDR(4); 912 phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg); 913 914 phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_NOP); 915 916 reg = phy_base_read(phydev, MSCC_DW8051_CNTL_STATUS); 917 reg &= ~MICRO_NSOFT_RESET; 918 phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, reg); 919 920 phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_MCB_ACCESS_MAC_CONF | 921 PROC_CMD_SGMII_PORT(0) | PROC_CMD_NO_MAC_CONF | 922 PROC_CMD_READ); 923 924 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL); 925 reg &= ~EN_PATCH_RAM_TRAP_ADDR(4); 926 phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg); 927 928 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 929 930 return 0; 931 } 932 933 /* bus->mdio_lock should be locked when using this function */ 934 static int vsc8584_get_fw_crc(struct phy_device *phydev, u16 start, u16 size, 935 u16 *crc) 936 { 937 int ret; 938 939 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED); 940 941 phy_base_write(phydev, MSCC_PHY_VERIPHY_CNTL_2, start); 942 phy_base_write(phydev, MSCC_PHY_VERIPHY_CNTL_3, size); 943 944 /* Start Micro command */ 945 ret = vsc8584_cmd(phydev, PROC_CMD_CRC16); 946 if (ret) 947 goto out; 948 949 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED); 950 951 *crc = phy_base_read(phydev, MSCC_PHY_VERIPHY_CNTL_2); 952 953 out: 954 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 955 956 return ret; 957 } 958 959 /* bus->mdio_lock should be locked when using this function */ 960 static int vsc8584_patch_fw(struct phy_device *phydev, 961 const struct firmware *fw) 962 { 963 int i, ret; 964 965 ret = vsc8584_micro_assert_reset(phydev); 966 if (ret) { 967 dev_err(&phydev->mdio.dev, 968 "%s: failed to assert reset of micro\n", __func__); 969 return ret; 970 } 971 972 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, 973 MSCC_PHY_PAGE_EXTENDED_GPIO); 974 975 /* Hold 8051 Micro in SW Reset, Enable auto incr address and patch clock 976 * Disable the 8051 Micro clock 977 */ 978 phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, RUN_FROM_INT_ROM | 979 AUTOINC_ADDR | PATCH_RAM_CLK | MICRO_CLK_EN | 980 MICRO_CLK_DIVIDE(2)); 981 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_PRAM | INT_MEM_WRITE_EN | 982 INT_MEM_DATA(2)); 983 phy_base_write(phydev, MSCC_INT_MEM_ADDR, 0x0000); 984 985 for (i = 0; i < fw->size; i++) 986 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_PRAM | 987 INT_MEM_WRITE_EN | fw->data[i]); 988 989 /* Clear internal memory access */ 990 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_RAM); 991 992 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 993 994 return 0; 995 } 996 997 /* bus->mdio_lock should be locked when using this function */ 998 static bool vsc8574_is_serdes_init(struct phy_device *phydev) 999 { 1000 u16 reg; 1001 bool ret; 1002 1003 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, 1004 MSCC_PHY_PAGE_EXTENDED_GPIO); 1005 1006 reg = phy_base_read(phydev, MSCC_TRAP_ROM_ADDR(1)); 1007 if (reg != 0x3eb7) { 1008 ret = false; 1009 goto out; 1010 } 1011 1012 reg = phy_base_read(phydev, MSCC_PATCH_RAM_ADDR(1)); 1013 if (reg != 0x4012) { 1014 ret = false; 1015 goto out; 1016 } 1017 1018 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL); 1019 if (reg != EN_PATCH_RAM_TRAP_ADDR(1)) { 1020 ret = false; 1021 goto out; 1022 } 1023 1024 reg = phy_base_read(phydev, MSCC_DW8051_CNTL_STATUS); 1025 if ((MICRO_NSOFT_RESET | RUN_FROM_INT_ROM | DW8051_CLK_EN | 1026 MICRO_CLK_EN) != (reg & MSCC_DW8051_VLD_MASK)) { 1027 ret = false; 1028 goto out; 1029 } 1030 1031 ret = true; 1032 out: 1033 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 1034 1035 return ret; 1036 } 1037 1038 /* bus->mdio_lock should be locked when using this function */ 1039 static int vsc8574_config_pre_init(struct phy_device *phydev) 1040 { 1041 static const struct reg_val pre_init1[] = { 1042 {0x0fae, 0x000401bd}, 1043 {0x0fac, 0x000f000f}, 1044 {0x17a0, 0x00a0f147}, 1045 {0x0fe4, 0x00052f54}, 1046 {0x1792, 0x0027303d}, 1047 {0x07fe, 0x00000704}, 1048 {0x0fe0, 0x00060150}, 1049 {0x0f82, 0x0012b00a}, 1050 {0x0f80, 0x00000d74}, 1051 {0x02e0, 0x00000012}, 1052 {0x03a2, 0x00050208}, 1053 {0x03b2, 0x00009186}, 1054 {0x0fb0, 0x000e3700}, 1055 {0x1688, 0x00049f81}, 1056 {0x0fd2, 0x0000ffff}, 1057 {0x168a, 0x00039fa2}, 1058 {0x1690, 0x0020640b}, 1059 {0x0258, 0x00002220}, 1060 {0x025a, 0x00002a20}, 1061 {0x025c, 0x00003060}, 1062 {0x025e, 0x00003fa0}, 1063 {0x03a6, 0x0000e0f0}, 1064 {0x0f92, 0x00001489}, 1065 {0x16a2, 0x00007000}, 1066 {0x16a6, 0x00071448}, 1067 {0x16a0, 0x00eeffdd}, 1068 {0x0fe8, 0x0091b06c}, 1069 {0x0fea, 0x00041600}, 1070 {0x16b0, 0x00eeff00}, 1071 {0x16b2, 0x00007000}, 1072 {0x16b4, 0x00000814}, 1073 {0x0f90, 0x00688980}, 1074 {0x03a4, 0x0000d8f0}, 1075 {0x0fc0, 0x00000400}, 1076 {0x07fa, 0x0050100f}, 1077 {0x0796, 0x00000003}, 1078 {0x07f8, 0x00c3ff98}, 1079 {0x0fa4, 0x0018292a}, 1080 {0x168c, 0x00d2c46f}, 1081 {0x17a2, 0x00000620}, 1082 {0x16a4, 0x0013132f}, 1083 {0x16a8, 0x00000000}, 1084 {0x0ffc, 0x00c0a028}, 1085 {0x0fec, 0x00901c09}, 1086 {0x0fee, 0x0004a6a1}, 1087 {0x0ffe, 0x00b01807}, 1088 }; 1089 static const struct reg_val pre_init2[] = { 1090 {0x0486, 0x0008a518}, 1091 {0x0488, 0x006dc696}, 1092 {0x048a, 0x00000912}, 1093 {0x048e, 0x00000db6}, 1094 {0x049c, 0x00596596}, 1095 {0x049e, 0x00000514}, 1096 {0x04a2, 0x00410280}, 1097 {0x04a4, 0x00000000}, 1098 {0x04a6, 0x00000000}, 1099 {0x04a8, 0x00000000}, 1100 {0x04aa, 0x00000000}, 1101 {0x04ae, 0x007df7dd}, 1102 {0x04b0, 0x006d95d4}, 1103 {0x04b2, 0x00492410}, 1104 }; 1105 struct device *dev = &phydev->mdio.dev; 1106 const struct firmware *fw; 1107 unsigned int i; 1108 u16 crc, reg; 1109 bool serdes_init; 1110 int ret; 1111 1112 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 1113 1114 /* all writes below are broadcasted to all PHYs in the same package */ 1115 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS); 1116 reg |= SMI_BROADCAST_WR_EN; 1117 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg); 1118 1119 phy_base_write(phydev, MII_VSC85XX_INT_MASK, 0); 1120 1121 /* The below register writes are tweaking analog and electrical 1122 * configuration that were determined through characterization by PHY 1123 * engineers. These don't mean anything more than "these are the best 1124 * values". 1125 */ 1126 phy_base_write(phydev, MSCC_PHY_EXT_PHY_CNTL_2, 0x0040); 1127 1128 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST); 1129 1130 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_20, 0x4320); 1131 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_24, 0x0c00); 1132 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_9, 0x18ca); 1133 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_5, 0x1b20); 1134 1135 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8); 1136 reg |= TR_CLK_DISABLE; 1137 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg); 1138 1139 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR); 1140 1141 for (i = 0; i < ARRAY_SIZE(pre_init1); i++) 1142 vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val); 1143 1144 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_2); 1145 1146 phy_base_write(phydev, MSCC_PHY_CU_PMD_TX_CNTL, 0x028e); 1147 1148 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR); 1149 1150 for (i = 0; i < ARRAY_SIZE(pre_init2); i++) 1151 vsc8584_csr_write(phydev, pre_init2[i].reg, pre_init2[i].val); 1152 1153 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST); 1154 1155 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8); 1156 reg &= ~TR_CLK_DISABLE; 1157 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg); 1158 1159 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 1160 1161 /* end of write broadcasting */ 1162 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS); 1163 reg &= ~SMI_BROADCAST_WR_EN; 1164 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg); 1165 1166 ret = request_firmware(&fw, MSCC_VSC8574_REVB_INT8051_FW, dev); 1167 if (ret) { 1168 dev_err(dev, "failed to load firmware %s, ret: %d\n", 1169 MSCC_VSC8574_REVB_INT8051_FW, ret); 1170 return ret; 1171 } 1172 1173 /* Add one byte to size for the one added by the patch_fw function */ 1174 ret = vsc8584_get_fw_crc(phydev, 1175 MSCC_VSC8574_REVB_INT8051_FW_START_ADDR, 1176 fw->size + 1, &crc); 1177 if (ret) 1178 goto out; 1179 1180 if (crc == MSCC_VSC8574_REVB_INT8051_FW_CRC) { 1181 serdes_init = vsc8574_is_serdes_init(phydev); 1182 1183 if (!serdes_init) { 1184 ret = vsc8584_micro_assert_reset(phydev); 1185 if (ret) { 1186 dev_err(dev, 1187 "%s: failed to assert reset of micro\n", 1188 __func__); 1189 goto out; 1190 } 1191 } 1192 } else { 1193 dev_dbg(dev, "FW CRC is not the expected one, patching FW\n"); 1194 1195 serdes_init = false; 1196 1197 if (vsc8584_patch_fw(phydev, fw)) 1198 dev_warn(dev, 1199 "failed to patch FW, expect non-optimal device\n"); 1200 } 1201 1202 if (!serdes_init) { 1203 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, 1204 MSCC_PHY_PAGE_EXTENDED_GPIO); 1205 1206 phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(1), 0x3eb7); 1207 phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(1), 0x4012); 1208 phy_base_write(phydev, MSCC_INT_MEM_CNTL, 1209 EN_PATCH_RAM_TRAP_ADDR(1)); 1210 1211 vsc8584_micro_deassert_reset(phydev, false); 1212 1213 /* Add one byte to size for the one added by the patch_fw 1214 * function 1215 */ 1216 ret = vsc8584_get_fw_crc(phydev, 1217 MSCC_VSC8574_REVB_INT8051_FW_START_ADDR, 1218 fw->size + 1, &crc); 1219 if (ret) 1220 goto out; 1221 1222 if (crc != MSCC_VSC8574_REVB_INT8051_FW_CRC) 1223 dev_warn(dev, 1224 "FW CRC after patching is not the expected one, expect non-optimal device\n"); 1225 } 1226 1227 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, 1228 MSCC_PHY_PAGE_EXTENDED_GPIO); 1229 1230 ret = vsc8584_cmd(phydev, PROC_CMD_1588_DEFAULT_INIT | 1231 PROC_CMD_PHY_INIT); 1232 1233 out: 1234 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 1235 1236 release_firmware(fw); 1237 1238 return ret; 1239 } 1240 1241 /* Access LCPLL Cfg_2 */ 1242 static void vsc8584_pll5g_cfg2_wr(struct phy_device *phydev, 1243 bool disable_fsm) 1244 { 1245 u32 rd_dat; 1246 1247 rd_dat = vsc85xx_csr_read(phydev, MACRO_CTRL, PHY_S6G_PLL5G_CFG2); 1248 rd_dat &= ~BIT(PHY_S6G_CFG2_FSM_DIS); 1249 rd_dat |= (disable_fsm << PHY_S6G_CFG2_FSM_DIS); 1250 vsc85xx_csr_write(phydev, MACRO_CTRL, PHY_S6G_PLL5G_CFG2, rd_dat); 1251 } 1252 1253 /* trigger a read to the spcified MCB */ 1254 static int vsc8584_mcb_rd_trig(struct phy_device *phydev, 1255 u32 mcb_reg_addr, u8 mcb_slave_num) 1256 { 1257 u32 rd_dat = 0; 1258 1259 /* read MCB */ 1260 vsc85xx_csr_write(phydev, MACRO_CTRL, mcb_reg_addr, 1261 (0x40000000 | (1L << mcb_slave_num))); 1262 1263 return read_poll_timeout(vsc85xx_csr_read, rd_dat, 1264 !(rd_dat & 0x40000000), 1265 4000, 200000, 0, 1266 phydev, MACRO_CTRL, mcb_reg_addr); 1267 } 1268 1269 /* trigger a write to the spcified MCB */ 1270 static int vsc8584_mcb_wr_trig(struct phy_device *phydev, 1271 u32 mcb_reg_addr, 1272 u8 mcb_slave_num) 1273 { 1274 u32 rd_dat = 0; 1275 1276 /* write back MCB */ 1277 vsc85xx_csr_write(phydev, MACRO_CTRL, mcb_reg_addr, 1278 (0x80000000 | (1L << mcb_slave_num))); 1279 1280 return read_poll_timeout(vsc85xx_csr_read, rd_dat, 1281 !(rd_dat & 0x80000000), 1282 4000, 200000, 0, 1283 phydev, MACRO_CTRL, mcb_reg_addr); 1284 } 1285 1286 /* Sequence to Reset LCPLL for the VIPER and ELISE PHY */ 1287 static int vsc8584_pll5g_reset(struct phy_device *phydev) 1288 { 1289 bool dis_fsm; 1290 int ret = 0; 1291 1292 ret = vsc8584_mcb_rd_trig(phydev, 0x11, 0); 1293 if (ret < 0) 1294 goto done; 1295 dis_fsm = 1; 1296 1297 /* Reset LCPLL */ 1298 vsc8584_pll5g_cfg2_wr(phydev, dis_fsm); 1299 1300 /* write back LCPLL MCB */ 1301 ret = vsc8584_mcb_wr_trig(phydev, 0x11, 0); 1302 if (ret < 0) 1303 goto done; 1304 1305 /* 10 mSec sleep while LCPLL is hold in reset */ 1306 usleep_range(10000, 20000); 1307 1308 /* read LCPLL MCB into CSRs */ 1309 ret = vsc8584_mcb_rd_trig(phydev, 0x11, 0); 1310 if (ret < 0) 1311 goto done; 1312 dis_fsm = 0; 1313 1314 /* Release the Reset of LCPLL */ 1315 vsc8584_pll5g_cfg2_wr(phydev, dis_fsm); 1316 1317 /* write back LCPLL MCB */ 1318 ret = vsc8584_mcb_wr_trig(phydev, 0x11, 0); 1319 if (ret < 0) 1320 goto done; 1321 1322 usleep_range(110000, 200000); 1323 done: 1324 return ret; 1325 } 1326 1327 /* bus->mdio_lock should be locked when using this function */ 1328 static int vsc8584_config_pre_init(struct phy_device *phydev) 1329 { 1330 static const struct reg_val pre_init1[] = { 1331 {0x07fa, 0x0050100f}, 1332 {0x1688, 0x00049f81}, 1333 {0x0f90, 0x00688980}, 1334 {0x03a4, 0x0000d8f0}, 1335 {0x0fc0, 0x00000400}, 1336 {0x0f82, 0x0012b002}, 1337 {0x1686, 0x00000004}, 1338 {0x168c, 0x00d2c46f}, 1339 {0x17a2, 0x00000620}, 1340 {0x16a0, 0x00eeffdd}, 1341 {0x16a6, 0x00071448}, 1342 {0x16a4, 0x0013132f}, 1343 {0x16a8, 0x00000000}, 1344 {0x0ffc, 0x00c0a028}, 1345 {0x0fe8, 0x0091b06c}, 1346 {0x0fea, 0x00041600}, 1347 {0x0f80, 0x00fffaff}, 1348 {0x0fec, 0x00901809}, 1349 {0x0ffe, 0x00b01007}, 1350 {0x16b0, 0x00eeff00}, 1351 {0x16b2, 0x00007000}, 1352 {0x16b4, 0x00000814}, 1353 }; 1354 static const struct reg_val pre_init2[] = { 1355 {0x0486, 0x0008a518}, 1356 {0x0488, 0x006dc696}, 1357 {0x048a, 0x00000912}, 1358 }; 1359 const struct firmware *fw; 1360 struct device *dev = &phydev->mdio.dev; 1361 unsigned int i; 1362 u16 crc, reg; 1363 int ret; 1364 1365 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 1366 1367 /* all writes below are broadcasted to all PHYs in the same package */ 1368 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS); 1369 reg |= SMI_BROADCAST_WR_EN; 1370 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg); 1371 1372 phy_base_write(phydev, MII_VSC85XX_INT_MASK, 0); 1373 1374 reg = phy_base_read(phydev, MSCC_PHY_BYPASS_CONTROL); 1375 reg |= PARALLEL_DET_IGNORE_ADVERTISED; 1376 phy_base_write(phydev, MSCC_PHY_BYPASS_CONTROL, reg); 1377 1378 /* The below register writes are tweaking analog and electrical 1379 * configuration that were determined through characterization by PHY 1380 * engineers. These don't mean anything more than "these are the best 1381 * values". 1382 */ 1383 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_3); 1384 1385 phy_base_write(phydev, MSCC_PHY_SERDES_TX_CRC_ERR_CNT, 0x2000); 1386 1387 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST); 1388 1389 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_5, 0x1f20); 1390 1391 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8); 1392 reg |= TR_CLK_DISABLE; 1393 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg); 1394 1395 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR); 1396 1397 phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(0x2fa4)); 1398 1399 reg = phy_base_read(phydev, MSCC_PHY_TR_MSB); 1400 reg &= ~0x007f; 1401 reg |= 0x0019; 1402 phy_base_write(phydev, MSCC_PHY_TR_MSB, reg); 1403 1404 phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(0x0fa4)); 1405 1406 for (i = 0; i < ARRAY_SIZE(pre_init1); i++) 1407 vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val); 1408 1409 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_2); 1410 1411 phy_base_write(phydev, MSCC_PHY_CU_PMD_TX_CNTL, 0x028e); 1412 1413 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR); 1414 1415 for (i = 0; i < ARRAY_SIZE(pre_init2); i++) 1416 vsc8584_csr_write(phydev, pre_init2[i].reg, pre_init2[i].val); 1417 1418 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST); 1419 1420 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8); 1421 reg &= ~TR_CLK_DISABLE; 1422 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg); 1423 1424 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 1425 1426 /* end of write broadcasting */ 1427 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS); 1428 reg &= ~SMI_BROADCAST_WR_EN; 1429 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg); 1430 1431 ret = request_firmware(&fw, MSCC_VSC8584_REVB_INT8051_FW, dev); 1432 if (ret) { 1433 dev_err(dev, "failed to load firmware %s, ret: %d\n", 1434 MSCC_VSC8584_REVB_INT8051_FW, ret); 1435 return ret; 1436 } 1437 1438 /* Add one byte to size for the one added by the patch_fw function */ 1439 ret = vsc8584_get_fw_crc(phydev, 1440 MSCC_VSC8584_REVB_INT8051_FW_START_ADDR, 1441 fw->size + 1, &crc); 1442 if (ret) 1443 goto out; 1444 1445 if (crc != MSCC_VSC8584_REVB_INT8051_FW_CRC) { 1446 dev_dbg(dev, "FW CRC is not the expected one, patching FW\n"); 1447 if (vsc8584_patch_fw(phydev, fw)) 1448 dev_warn(dev, 1449 "failed to patch FW, expect non-optimal device\n"); 1450 } 1451 1452 vsc8584_micro_deassert_reset(phydev, false); 1453 1454 /* Add one byte to size for the one added by the patch_fw function */ 1455 ret = vsc8584_get_fw_crc(phydev, 1456 MSCC_VSC8584_REVB_INT8051_FW_START_ADDR, 1457 fw->size + 1, &crc); 1458 if (ret) 1459 goto out; 1460 1461 if (crc != MSCC_VSC8584_REVB_INT8051_FW_CRC) 1462 dev_warn(dev, 1463 "FW CRC after patching is not the expected one, expect non-optimal device\n"); 1464 1465 ret = vsc8584_micro_assert_reset(phydev); 1466 if (ret) 1467 goto out; 1468 1469 vsc8584_micro_deassert_reset(phydev, true); 1470 1471 out: 1472 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 1473 1474 release_firmware(fw); 1475 1476 return ret; 1477 } 1478 1479 static void vsc8584_get_base_addr(struct phy_device *phydev) 1480 { 1481 struct vsc8531_private *vsc8531 = phydev->priv; 1482 u16 val, addr; 1483 1484 phy_lock_mdio_bus(phydev); 1485 __phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED); 1486 1487 addr = __phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_4); 1488 addr >>= PHY_CNTL_4_ADDR_POS; 1489 1490 val = __phy_read(phydev, MSCC_PHY_ACTIPHY_CNTL); 1491 1492 __phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 1493 phy_unlock_mdio_bus(phydev); 1494 1495 /* In the package, there are two pairs of PHYs (PHY0 + PHY2 and 1496 * PHY1 + PHY3). The first PHY of each pair (PHY0 and PHY1) is 1497 * the base PHY for timestamping operations. 1498 */ 1499 vsc8531->ts_base_addr = phydev->mdio.addr; 1500 vsc8531->ts_base_phy = addr; 1501 1502 if (val & PHY_ADDR_REVERSED) { 1503 vsc8531->base_addr = phydev->mdio.addr + addr; 1504 if (addr > 1) { 1505 vsc8531->ts_base_addr += 2; 1506 vsc8531->ts_base_phy += 2; 1507 } 1508 } else { 1509 vsc8531->base_addr = phydev->mdio.addr - addr; 1510 if (addr > 1) { 1511 vsc8531->ts_base_addr -= 2; 1512 vsc8531->ts_base_phy -= 2; 1513 } 1514 } 1515 1516 vsc8531->addr = addr; 1517 } 1518 1519 static void vsc85xx_coma_mode_release(struct phy_device *phydev) 1520 { 1521 /* The coma mode (pin or reg) provides an optional feature that 1522 * may be used to control when the PHYs become active. 1523 * Alternatively the COMA_MODE pin may be connected low 1524 * so that the PHYs are fully active once out of reset. 1525 */ 1526 1527 /* Enable output (mode=0) and write zero to it */ 1528 vsc85xx_phy_write_page(phydev, MSCC_PHY_PAGE_EXTENDED_GPIO); 1529 __phy_modify(phydev, MSCC_PHY_GPIO_CONTROL_2, 1530 MSCC_PHY_COMA_MODE | MSCC_PHY_COMA_OUTPUT, 0); 1531 vsc85xx_phy_write_page(phydev, MSCC_PHY_PAGE_STANDARD); 1532 } 1533 1534 static int vsc8584_config_init(struct phy_device *phydev) 1535 { 1536 struct vsc8531_private *vsc8531 = phydev->priv; 1537 int ret, i; 1538 u16 val; 1539 1540 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; 1541 1542 phy_lock_mdio_bus(phydev); 1543 1544 /* Some parts of the init sequence are identical for every PHY in the 1545 * package. Some parts are modifying the GPIO register bank which is a 1546 * set of registers that are affecting all PHYs, a few resetting the 1547 * microprocessor common to all PHYs. The CRC check responsible of the 1548 * checking the firmware within the 8051 microprocessor can only be 1549 * accessed via the PHY whose internal address in the package is 0. 1550 * All PHYs' interrupts mask register has to be zeroed before enabling 1551 * any PHY's interrupt in this register. 1552 * For all these reasons, we need to do the init sequence once and only 1553 * once whatever is the first PHY in the package that is initialized and 1554 * do the correct init sequence for all PHYs that are package-critical 1555 * in this pre-init function. 1556 */ 1557 if (phy_package_init_once(phydev)) { 1558 /* The following switch statement assumes that the lowest 1559 * nibble of the phy_id_mask is always 0. This works because 1560 * the lowest nibble of the PHY_ID's below are also 0. 1561 */ 1562 WARN_ON(phydev->drv->phy_id_mask & 0xf); 1563 1564 switch (phydev->phy_id & phydev->drv->phy_id_mask) { 1565 case PHY_ID_VSC8504: 1566 case PHY_ID_VSC8552: 1567 case PHY_ID_VSC8572: 1568 case PHY_ID_VSC8574: 1569 ret = vsc8574_config_pre_init(phydev); 1570 break; 1571 case PHY_ID_VSC856X: 1572 case PHY_ID_VSC8575: 1573 case PHY_ID_VSC8582: 1574 case PHY_ID_VSC8584: 1575 ret = vsc8584_config_pre_init(phydev); 1576 break; 1577 default: 1578 ret = -EINVAL; 1579 break; 1580 } 1581 1582 if (ret) 1583 goto err; 1584 } 1585 1586 ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, 1587 MSCC_PHY_PAGE_EXTENDED_GPIO); 1588 if (ret) 1589 goto err; 1590 1591 val = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK); 1592 val &= ~MAC_CFG_MASK; 1593 if (phydev->interface == PHY_INTERFACE_MODE_QSGMII) { 1594 val |= MAC_CFG_QSGMII; 1595 } else if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { 1596 val |= MAC_CFG_SGMII; 1597 } else if (phy_interface_is_rgmii(phydev)) { 1598 val |= MAC_CFG_RGMII; 1599 } else { 1600 ret = -EINVAL; 1601 goto err; 1602 } 1603 1604 ret = phy_base_write(phydev, MSCC_PHY_MAC_CFG_FASTLINK, val); 1605 if (ret) 1606 goto err; 1607 1608 ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, 1609 MSCC_PHY_PAGE_STANDARD); 1610 if (ret) 1611 goto err; 1612 1613 if (!phy_interface_is_rgmii(phydev)) { 1614 val = PROC_CMD_MCB_ACCESS_MAC_CONF | PROC_CMD_RST_CONF_PORT | 1615 PROC_CMD_READ_MOD_WRITE_PORT; 1616 if (phydev->interface == PHY_INTERFACE_MODE_QSGMII) 1617 val |= PROC_CMD_QSGMII_MAC; 1618 else 1619 val |= PROC_CMD_SGMII_MAC; 1620 1621 ret = vsc8584_cmd(phydev, val); 1622 if (ret) 1623 goto err; 1624 1625 usleep_range(10000, 20000); 1626 } 1627 1628 /* Disable SerDes for 100Base-FX */ 1629 ret = vsc8584_cmd(phydev, PROC_CMD_FIBER_MEDIA_CONF | 1630 PROC_CMD_FIBER_PORT(vsc8531->addr) | 1631 PROC_CMD_FIBER_DISABLE | 1632 PROC_CMD_READ_MOD_WRITE_PORT | 1633 PROC_CMD_RST_CONF_PORT | PROC_CMD_FIBER_100BASE_FX); 1634 if (ret) 1635 goto err; 1636 1637 /* Disable SerDes for 1000Base-X */ 1638 ret = vsc8584_cmd(phydev, PROC_CMD_FIBER_MEDIA_CONF | 1639 PROC_CMD_FIBER_PORT(vsc8531->addr) | 1640 PROC_CMD_FIBER_DISABLE | 1641 PROC_CMD_READ_MOD_WRITE_PORT | 1642 PROC_CMD_RST_CONF_PORT | PROC_CMD_FIBER_1000BASE_X); 1643 if (ret) 1644 goto err; 1645 1646 phy_unlock_mdio_bus(phydev); 1647 1648 ret = vsc8584_macsec_init(phydev); 1649 if (ret) 1650 return ret; 1651 1652 ret = vsc8584_ptp_init(phydev); 1653 if (ret) 1654 return ret; 1655 1656 val = phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_1); 1657 val &= ~(MEDIA_OP_MODE_MASK | VSC8584_MAC_IF_SELECTION_MASK); 1658 val |= (MEDIA_OP_MODE_COPPER << MEDIA_OP_MODE_POS) | 1659 (VSC8584_MAC_IF_SELECTION_SGMII << VSC8584_MAC_IF_SELECTION_POS); 1660 ret = phy_write(phydev, MSCC_PHY_EXT_PHY_CNTL_1, val); 1661 if (ret) 1662 return ret; 1663 1664 if (phy_interface_is_rgmii(phydev)) { 1665 ret = vsc85xx_rgmii_set_skews(phydev, VSC8572_RGMII_CNTL, 1666 VSC8572_RGMII_RX_DELAY_MASK, 1667 VSC8572_RGMII_TX_DELAY_MASK); 1668 if (ret) 1669 return ret; 1670 } 1671 1672 ret = genphy_soft_reset(phydev); 1673 if (ret) 1674 return ret; 1675 1676 for (i = 0; i < vsc8531->nleds; i++) { 1677 ret = vsc85xx_led_cntl_set(phydev, i, vsc8531->leds_mode[i]); 1678 if (ret) 1679 return ret; 1680 } 1681 1682 return 0; 1683 1684 err: 1685 phy_unlock_mdio_bus(phydev); 1686 return ret; 1687 } 1688 1689 static irqreturn_t vsc8584_handle_interrupt(struct phy_device *phydev) 1690 { 1691 irqreturn_t ret; 1692 int irq_status; 1693 1694 irq_status = phy_read(phydev, MII_VSC85XX_INT_STATUS); 1695 if (irq_status < 0) 1696 return IRQ_NONE; 1697 1698 /* Timestamping IRQ does not set a bit in the global INT_STATUS, so 1699 * irq_status would be 0. 1700 */ 1701 ret = vsc8584_handle_ts_interrupt(phydev); 1702 if (!(irq_status & MII_VSC85XX_INT_MASK_MASK)) 1703 return ret; 1704 1705 if (irq_status & MII_VSC85XX_INT_MASK_EXT) 1706 vsc8584_handle_macsec_interrupt(phydev); 1707 1708 if (irq_status & MII_VSC85XX_INT_MASK_LINK_CHG) 1709 phy_trigger_machine(phydev); 1710 1711 return IRQ_HANDLED; 1712 } 1713 1714 static int vsc85xx_config_init(struct phy_device *phydev) 1715 { 1716 int rc, i, phy_id; 1717 struct vsc8531_private *vsc8531 = phydev->priv; 1718 1719 rc = vsc85xx_default_config(phydev); 1720 if (rc) 1721 return rc; 1722 1723 rc = vsc85xx_mac_if_set(phydev, phydev->interface); 1724 if (rc) 1725 return rc; 1726 1727 rc = vsc85xx_edge_rate_cntl_set(phydev, vsc8531->rate_magic); 1728 if (rc) 1729 return rc; 1730 1731 phy_id = phydev->drv->phy_id & phydev->drv->phy_id_mask; 1732 if (PHY_ID_VSC8531 == phy_id || PHY_ID_VSC8541 == phy_id || 1733 PHY_ID_VSC8530 == phy_id || PHY_ID_VSC8540 == phy_id) { 1734 rc = vsc8531_pre_init_seq_set(phydev); 1735 if (rc) 1736 return rc; 1737 } 1738 1739 rc = vsc85xx_eee_init_seq_set(phydev); 1740 if (rc) 1741 return rc; 1742 1743 for (i = 0; i < vsc8531->nleds; i++) { 1744 rc = vsc85xx_led_cntl_set(phydev, i, vsc8531->leds_mode[i]); 1745 if (rc) 1746 return rc; 1747 } 1748 1749 return 0; 1750 } 1751 1752 static int __phy_write_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb, 1753 u32 op) 1754 { 1755 unsigned long deadline; 1756 u32 val; 1757 int ret; 1758 1759 ret = vsc85xx_csr_write(phydev, PHY_MCB_TARGET, reg, 1760 op | (1 << mcb)); 1761 if (ret) 1762 return -EINVAL; 1763 1764 deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS); 1765 do { 1766 usleep_range(500, 1000); 1767 val = vsc85xx_csr_read(phydev, PHY_MCB_TARGET, reg); 1768 1769 if (val == 0xffffffff) 1770 return -EIO; 1771 1772 } while (time_before(jiffies, deadline) && (val & op)); 1773 1774 if (val & op) 1775 return -ETIMEDOUT; 1776 1777 return 0; 1778 } 1779 1780 /* Trigger a read to the specified MCB */ 1781 int phy_update_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb) 1782 { 1783 return __phy_write_mcb_s6g(phydev, reg, mcb, PHY_MCB_S6G_READ); 1784 } 1785 1786 /* Trigger a write to the specified MCB */ 1787 int phy_commit_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb) 1788 { 1789 return __phy_write_mcb_s6g(phydev, reg, mcb, PHY_MCB_S6G_WRITE); 1790 } 1791 1792 static int vsc8514_config_host_serdes(struct phy_device *phydev) 1793 { 1794 int ret; 1795 u16 val; 1796 1797 ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, 1798 MSCC_PHY_PAGE_EXTENDED_GPIO); 1799 if (ret) 1800 return ret; 1801 1802 val = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK); 1803 val &= ~MAC_CFG_MASK; 1804 val |= MAC_CFG_QSGMII; 1805 ret = phy_base_write(phydev, MSCC_PHY_MAC_CFG_FASTLINK, val); 1806 if (ret) 1807 return ret; 1808 1809 ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, 1810 MSCC_PHY_PAGE_STANDARD); 1811 if (ret) 1812 return ret; 1813 1814 ret = vsc8584_cmd(phydev, PROC_CMD_NOP); 1815 if (ret) 1816 return ret; 1817 1818 ret = vsc8584_cmd(phydev, 1819 PROC_CMD_MCB_ACCESS_MAC_CONF | 1820 PROC_CMD_RST_CONF_PORT | 1821 PROC_CMD_READ_MOD_WRITE_PORT | PROC_CMD_QSGMII_MAC); 1822 if (ret) { 1823 dev_err(&phydev->mdio.dev, "%s: QSGMII error: %d\n", 1824 __func__, ret); 1825 return ret; 1826 } 1827 1828 /* Apply 6G SerDes FOJI Algorithm 1829 * Initial condition requirement: 1830 * 1. hold 8051 in reset 1831 * 2. disable patch vector 0, in order to allow IB cal poll during FoJi 1832 * 3. deassert 8051 reset after change patch vector status 1833 * 4. proceed with FoJi (vsc85xx_sd6g_config_v2) 1834 */ 1835 vsc8584_micro_assert_reset(phydev); 1836 val = phy_base_read(phydev, MSCC_INT_MEM_CNTL); 1837 /* clear bit 8, to disable patch vector 0 */ 1838 val &= ~PATCH_VEC_ZERO_EN; 1839 ret = phy_base_write(phydev, MSCC_INT_MEM_CNTL, val); 1840 /* Enable 8051 clock, don't set patch present, disable PRAM clock override */ 1841 vsc8584_micro_deassert_reset(phydev, false); 1842 1843 return vsc85xx_sd6g_config_v2(phydev); 1844 } 1845 1846 static int vsc8514_config_pre_init(struct phy_device *phydev) 1847 { 1848 /* These are the settings to override the silicon default 1849 * values to handle hardware performance of PHY. They 1850 * are set at Power-On state and remain until PHY Reset. 1851 */ 1852 static const struct reg_val pre_init1[] = { 1853 {0x0f90, 0x00688980}, 1854 {0x0786, 0x00000003}, 1855 {0x07fa, 0x0050100f}, 1856 {0x0f82, 0x0012b002}, 1857 {0x1686, 0x00000004}, 1858 {0x168c, 0x00d2c46f}, 1859 {0x17a2, 0x00000620}, 1860 {0x16a0, 0x00eeffdd}, 1861 {0x16a6, 0x00071448}, 1862 {0x16a4, 0x0013132f}, 1863 {0x16a8, 0x00000000}, 1864 {0x0ffc, 0x00c0a028}, 1865 {0x0fe8, 0x0091b06c}, 1866 {0x0fea, 0x00041600}, 1867 {0x0f80, 0x00fffaff}, 1868 {0x0fec, 0x00901809}, 1869 {0x0ffe, 0x00b01007}, 1870 {0x16b0, 0x00eeff00}, 1871 {0x16b2, 0x00007000}, 1872 {0x16b4, 0x00000814}, 1873 }; 1874 struct device *dev = &phydev->mdio.dev; 1875 unsigned int i; 1876 u16 reg; 1877 int ret; 1878 1879 ret = vsc8584_pll5g_reset(phydev); 1880 if (ret < 0) { 1881 dev_err(dev, "failed LCPLL reset, ret: %d\n", ret); 1882 return ret; 1883 } 1884 1885 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 1886 1887 /* all writes below are broadcasted to all PHYs in the same package */ 1888 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS); 1889 reg |= SMI_BROADCAST_WR_EN; 1890 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg); 1891 1892 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST); 1893 1894 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8); 1895 reg |= BIT(15); 1896 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg); 1897 1898 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR); 1899 1900 for (i = 0; i < ARRAY_SIZE(pre_init1); i++) 1901 vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val); 1902 1903 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST); 1904 1905 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8); 1906 reg &= ~BIT(15); 1907 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg); 1908 1909 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 1910 1911 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS); 1912 reg &= ~SMI_BROADCAST_WR_EN; 1913 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg); 1914 1915 /* Add pre-patching commands to: 1916 * 1. enable 8051 clock, operate 8051 clock at 125 MHz 1917 * instead of HW default 62.5MHz 1918 * 2. write patch vector 0, to skip IB cal polling executed 1919 * as part of the 0x80E0 ROM command 1920 */ 1921 vsc8584_micro_deassert_reset(phydev, false); 1922 1923 vsc8584_micro_assert_reset(phydev); 1924 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, 1925 MSCC_PHY_PAGE_EXTENDED_GPIO); 1926 /* ROM address to trap, for patch vector 0 */ 1927 reg = MSCC_ROM_TRAP_SERDES_6G_CFG; 1928 ret = phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(1), reg); 1929 if (ret) 1930 goto err; 1931 /* RAM address to jump to, when patch vector 0 enabled */ 1932 reg = MSCC_RAM_TRAP_SERDES_6G_CFG; 1933 ret = phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(1), reg); 1934 if (ret) 1935 goto err; 1936 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL); 1937 reg |= PATCH_VEC_ZERO_EN; /* bit 8, enable patch vector 0 */ 1938 ret = phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg); 1939 if (ret) 1940 goto err; 1941 1942 /* Enable 8051 clock, don't set patch present 1943 * yet, disable PRAM clock override 1944 */ 1945 vsc8584_micro_deassert_reset(phydev, false); 1946 return ret; 1947 err: 1948 /* restore 8051 and bail w error */ 1949 vsc8584_micro_deassert_reset(phydev, false); 1950 return ret; 1951 } 1952 1953 static int vsc8514_config_init(struct phy_device *phydev) 1954 { 1955 struct vsc8531_private *vsc8531 = phydev->priv; 1956 int ret, i; 1957 1958 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; 1959 1960 phy_lock_mdio_bus(phydev); 1961 1962 /* Some parts of the init sequence are identical for every PHY in the 1963 * package. Some parts are modifying the GPIO register bank which is a 1964 * set of registers that are affecting all PHYs, a few resetting the 1965 * microprocessor common to all PHYs. 1966 * All PHYs' interrupts mask register has to be zeroed before enabling 1967 * any PHY's interrupt in this register. 1968 * For all these reasons, we need to do the init sequence once and only 1969 * once whatever is the first PHY in the package that is initialized and 1970 * do the correct init sequence for all PHYs that are package-critical 1971 * in this pre-init function. 1972 */ 1973 if (phy_package_init_once(phydev)) { 1974 ret = vsc8514_config_pre_init(phydev); 1975 if (ret) 1976 goto err; 1977 ret = vsc8514_config_host_serdes(phydev); 1978 if (ret) 1979 goto err; 1980 vsc85xx_coma_mode_release(phydev); 1981 } 1982 1983 phy_unlock_mdio_bus(phydev); 1984 1985 ret = phy_modify(phydev, MSCC_PHY_EXT_PHY_CNTL_1, MEDIA_OP_MODE_MASK, 1986 MEDIA_OP_MODE_COPPER << MEDIA_OP_MODE_POS); 1987 1988 if (ret) 1989 return ret; 1990 1991 ret = genphy_soft_reset(phydev); 1992 1993 if (ret) 1994 return ret; 1995 1996 for (i = 0; i < vsc8531->nleds; i++) { 1997 ret = vsc85xx_led_cntl_set(phydev, i, vsc8531->leds_mode[i]); 1998 if (ret) 1999 return ret; 2000 } 2001 2002 return ret; 2003 2004 err: 2005 phy_unlock_mdio_bus(phydev); 2006 return ret; 2007 } 2008 2009 static int vsc85xx_ack_interrupt(struct phy_device *phydev) 2010 { 2011 int rc = 0; 2012 2013 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) 2014 rc = phy_read(phydev, MII_VSC85XX_INT_STATUS); 2015 2016 return (rc < 0) ? rc : 0; 2017 } 2018 2019 static int vsc85xx_config_intr(struct phy_device *phydev) 2020 { 2021 int rc; 2022 2023 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 2024 rc = vsc85xx_ack_interrupt(phydev); 2025 if (rc) 2026 return rc; 2027 2028 vsc8584_config_macsec_intr(phydev); 2029 vsc8584_config_ts_intr(phydev); 2030 2031 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, 2032 MII_VSC85XX_INT_MASK_MASK); 2033 } else { 2034 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, 0); 2035 if (rc < 0) 2036 return rc; 2037 rc = phy_read(phydev, MII_VSC85XX_INT_STATUS); 2038 if (rc < 0) 2039 return rc; 2040 2041 rc = vsc85xx_ack_interrupt(phydev); 2042 } 2043 2044 return rc; 2045 } 2046 2047 static irqreturn_t vsc85xx_handle_interrupt(struct phy_device *phydev) 2048 { 2049 int irq_status; 2050 2051 irq_status = phy_read(phydev, MII_VSC85XX_INT_STATUS); 2052 if (irq_status < 0) { 2053 phy_error(phydev); 2054 return IRQ_NONE; 2055 } 2056 2057 if (!(irq_status & MII_VSC85XX_INT_MASK_MASK)) 2058 return IRQ_NONE; 2059 2060 phy_trigger_machine(phydev); 2061 2062 return IRQ_HANDLED; 2063 } 2064 2065 static int vsc85xx_config_aneg(struct phy_device *phydev) 2066 { 2067 int rc; 2068 2069 rc = vsc85xx_mdix_set(phydev, phydev->mdix_ctrl); 2070 if (rc < 0) 2071 return rc; 2072 2073 return genphy_config_aneg(phydev); 2074 } 2075 2076 static int vsc85xx_read_status(struct phy_device *phydev) 2077 { 2078 int rc; 2079 2080 rc = vsc85xx_mdix_get(phydev, &phydev->mdix); 2081 if (rc < 0) 2082 return rc; 2083 2084 return genphy_read_status(phydev); 2085 } 2086 2087 static int vsc8514_probe(struct phy_device *phydev) 2088 { 2089 struct vsc8531_private *vsc8531; 2090 u32 default_mode[4] = {VSC8531_LINK_1000_ACTIVITY, 2091 VSC8531_LINK_100_ACTIVITY, VSC8531_LINK_ACTIVITY, 2092 VSC8531_DUPLEX_COLLISION}; 2093 2094 vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL); 2095 if (!vsc8531) 2096 return -ENOMEM; 2097 2098 phydev->priv = vsc8531; 2099 2100 vsc8584_get_base_addr(phydev); 2101 devm_phy_package_join(&phydev->mdio.dev, phydev, 2102 vsc8531->base_addr, 0); 2103 2104 vsc8531->nleds = 4; 2105 vsc8531->supp_led_modes = VSC85XX_SUPP_LED_MODES; 2106 vsc8531->hw_stats = vsc85xx_hw_stats; 2107 vsc8531->nstats = ARRAY_SIZE(vsc85xx_hw_stats); 2108 vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats, 2109 sizeof(u64), GFP_KERNEL); 2110 if (!vsc8531->stats) 2111 return -ENOMEM; 2112 2113 return vsc85xx_dt_led_modes_get(phydev, default_mode); 2114 } 2115 2116 static int vsc8574_probe(struct phy_device *phydev) 2117 { 2118 struct vsc8531_private *vsc8531; 2119 u32 default_mode[4] = {VSC8531_LINK_1000_ACTIVITY, 2120 VSC8531_LINK_100_ACTIVITY, VSC8531_LINK_ACTIVITY, 2121 VSC8531_DUPLEX_COLLISION}; 2122 2123 vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL); 2124 if (!vsc8531) 2125 return -ENOMEM; 2126 2127 phydev->priv = vsc8531; 2128 2129 vsc8584_get_base_addr(phydev); 2130 devm_phy_package_join(&phydev->mdio.dev, phydev, 2131 vsc8531->base_addr, 0); 2132 2133 vsc8531->nleds = 4; 2134 vsc8531->supp_led_modes = VSC8584_SUPP_LED_MODES; 2135 vsc8531->hw_stats = vsc8584_hw_stats; 2136 vsc8531->nstats = ARRAY_SIZE(vsc8584_hw_stats); 2137 vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats, 2138 sizeof(u64), GFP_KERNEL); 2139 if (!vsc8531->stats) 2140 return -ENOMEM; 2141 2142 return vsc85xx_dt_led_modes_get(phydev, default_mode); 2143 } 2144 2145 static int vsc8584_probe(struct phy_device *phydev) 2146 { 2147 struct vsc8531_private *vsc8531; 2148 u32 default_mode[4] = {VSC8531_LINK_1000_ACTIVITY, 2149 VSC8531_LINK_100_ACTIVITY, VSC8531_LINK_ACTIVITY, 2150 VSC8531_DUPLEX_COLLISION}; 2151 int ret; 2152 2153 if ((phydev->phy_id & MSCC_DEV_REV_MASK) != VSC8584_REVB) { 2154 dev_err(&phydev->mdio.dev, "Only VSC8584 revB is supported.\n"); 2155 return -ENOTSUPP; 2156 } 2157 2158 vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL); 2159 if (!vsc8531) 2160 return -ENOMEM; 2161 2162 phydev->priv = vsc8531; 2163 2164 vsc8584_get_base_addr(phydev); 2165 devm_phy_package_join(&phydev->mdio.dev, phydev, vsc8531->base_addr, 2166 sizeof(struct vsc85xx_shared_private)); 2167 2168 vsc8531->nleds = 4; 2169 vsc8531->supp_led_modes = VSC8584_SUPP_LED_MODES; 2170 vsc8531->hw_stats = vsc8584_hw_stats; 2171 vsc8531->nstats = ARRAY_SIZE(vsc8584_hw_stats); 2172 vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats, 2173 sizeof(u64), GFP_KERNEL); 2174 if (!vsc8531->stats) 2175 return -ENOMEM; 2176 2177 if (phy_package_probe_once(phydev)) { 2178 ret = vsc8584_ptp_probe_once(phydev); 2179 if (ret) 2180 return ret; 2181 } 2182 2183 ret = vsc8584_ptp_probe(phydev); 2184 if (ret) 2185 return ret; 2186 2187 return vsc85xx_dt_led_modes_get(phydev, default_mode); 2188 } 2189 2190 static int vsc85xx_probe(struct phy_device *phydev) 2191 { 2192 struct vsc8531_private *vsc8531; 2193 int rate_magic; 2194 u32 default_mode[2] = {VSC8531_LINK_1000_ACTIVITY, 2195 VSC8531_LINK_100_ACTIVITY}; 2196 2197 rate_magic = vsc85xx_edge_rate_magic_get(phydev); 2198 if (rate_magic < 0) 2199 return rate_magic; 2200 2201 vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL); 2202 if (!vsc8531) 2203 return -ENOMEM; 2204 2205 phydev->priv = vsc8531; 2206 2207 vsc8531->rate_magic = rate_magic; 2208 vsc8531->nleds = 2; 2209 vsc8531->supp_led_modes = VSC85XX_SUPP_LED_MODES; 2210 vsc8531->hw_stats = vsc85xx_hw_stats; 2211 vsc8531->nstats = ARRAY_SIZE(vsc85xx_hw_stats); 2212 vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats, 2213 sizeof(u64), GFP_KERNEL); 2214 if (!vsc8531->stats) 2215 return -ENOMEM; 2216 2217 return vsc85xx_dt_led_modes_get(phydev, default_mode); 2218 } 2219 2220 /* Microsemi VSC85xx PHYs */ 2221 static struct phy_driver vsc85xx_driver[] = { 2222 { 2223 .phy_id = PHY_ID_VSC8502, 2224 .name = "Microsemi GE VSC8502 SyncE", 2225 .phy_id_mask = 0xfffffff0, 2226 /* PHY_BASIC_FEATURES */ 2227 .soft_reset = &genphy_soft_reset, 2228 .config_init = &vsc85xx_config_init, 2229 .config_aneg = &vsc85xx_config_aneg, 2230 .read_status = &vsc85xx_read_status, 2231 .handle_interrupt = vsc85xx_handle_interrupt, 2232 .config_intr = &vsc85xx_config_intr, 2233 .suspend = &genphy_suspend, 2234 .resume = &genphy_resume, 2235 .probe = &vsc85xx_probe, 2236 .set_wol = &vsc85xx_wol_set, 2237 .get_wol = &vsc85xx_wol_get, 2238 .get_tunable = &vsc85xx_get_tunable, 2239 .set_tunable = &vsc85xx_set_tunable, 2240 .read_page = &vsc85xx_phy_read_page, 2241 .write_page = &vsc85xx_phy_write_page, 2242 .get_sset_count = &vsc85xx_get_sset_count, 2243 .get_strings = &vsc85xx_get_strings, 2244 .get_stats = &vsc85xx_get_stats, 2245 }, 2246 { 2247 .phy_id = PHY_ID_VSC8504, 2248 .name = "Microsemi GE VSC8504 SyncE", 2249 .phy_id_mask = 0xfffffff0, 2250 /* PHY_GBIT_FEATURES */ 2251 .soft_reset = &genphy_soft_reset, 2252 .config_init = &vsc8584_config_init, 2253 .config_aneg = &vsc85xx_config_aneg, 2254 .aneg_done = &genphy_aneg_done, 2255 .read_status = &vsc85xx_read_status, 2256 .handle_interrupt = vsc85xx_handle_interrupt, 2257 .config_intr = &vsc85xx_config_intr, 2258 .suspend = &genphy_suspend, 2259 .resume = &genphy_resume, 2260 .probe = &vsc8574_probe, 2261 .set_wol = &vsc85xx_wol_set, 2262 .get_wol = &vsc85xx_wol_get, 2263 .get_tunable = &vsc85xx_get_tunable, 2264 .set_tunable = &vsc85xx_set_tunable, 2265 .read_page = &vsc85xx_phy_read_page, 2266 .write_page = &vsc85xx_phy_write_page, 2267 .get_sset_count = &vsc85xx_get_sset_count, 2268 .get_strings = &vsc85xx_get_strings, 2269 .get_stats = &vsc85xx_get_stats, 2270 }, 2271 { 2272 .phy_id = PHY_ID_VSC8514, 2273 .name = "Microsemi GE VSC8514 SyncE", 2274 .phy_id_mask = 0xfffffff0, 2275 .soft_reset = &genphy_soft_reset, 2276 .config_init = &vsc8514_config_init, 2277 .config_aneg = &vsc85xx_config_aneg, 2278 .read_status = &vsc85xx_read_status, 2279 .handle_interrupt = vsc85xx_handle_interrupt, 2280 .config_intr = &vsc85xx_config_intr, 2281 .suspend = &genphy_suspend, 2282 .resume = &genphy_resume, 2283 .probe = &vsc8514_probe, 2284 .set_wol = &vsc85xx_wol_set, 2285 .get_wol = &vsc85xx_wol_get, 2286 .get_tunable = &vsc85xx_get_tunable, 2287 .set_tunable = &vsc85xx_set_tunable, 2288 .read_page = &vsc85xx_phy_read_page, 2289 .write_page = &vsc85xx_phy_write_page, 2290 .get_sset_count = &vsc85xx_get_sset_count, 2291 .get_strings = &vsc85xx_get_strings, 2292 .get_stats = &vsc85xx_get_stats, 2293 }, 2294 { 2295 .phy_id = PHY_ID_VSC8530, 2296 .name = "Microsemi FE VSC8530", 2297 .phy_id_mask = 0xfffffff0, 2298 /* PHY_BASIC_FEATURES */ 2299 .soft_reset = &genphy_soft_reset, 2300 .config_init = &vsc85xx_config_init, 2301 .config_aneg = &vsc85xx_config_aneg, 2302 .read_status = &vsc85xx_read_status, 2303 .handle_interrupt = vsc85xx_handle_interrupt, 2304 .config_intr = &vsc85xx_config_intr, 2305 .suspend = &genphy_suspend, 2306 .resume = &genphy_resume, 2307 .probe = &vsc85xx_probe, 2308 .set_wol = &vsc85xx_wol_set, 2309 .get_wol = &vsc85xx_wol_get, 2310 .get_tunable = &vsc85xx_get_tunable, 2311 .set_tunable = &vsc85xx_set_tunable, 2312 .read_page = &vsc85xx_phy_read_page, 2313 .write_page = &vsc85xx_phy_write_page, 2314 .get_sset_count = &vsc85xx_get_sset_count, 2315 .get_strings = &vsc85xx_get_strings, 2316 .get_stats = &vsc85xx_get_stats, 2317 }, 2318 { 2319 .phy_id = PHY_ID_VSC8531, 2320 .name = "Microsemi VSC8531", 2321 .phy_id_mask = 0xfffffff0, 2322 /* PHY_GBIT_FEATURES */ 2323 .soft_reset = &genphy_soft_reset, 2324 .config_init = &vsc85xx_config_init, 2325 .config_aneg = &vsc85xx_config_aneg, 2326 .read_status = &vsc85xx_read_status, 2327 .handle_interrupt = vsc85xx_handle_interrupt, 2328 .config_intr = &vsc85xx_config_intr, 2329 .suspend = &genphy_suspend, 2330 .resume = &genphy_resume, 2331 .probe = &vsc85xx_probe, 2332 .set_wol = &vsc85xx_wol_set, 2333 .get_wol = &vsc85xx_wol_get, 2334 .get_tunable = &vsc85xx_get_tunable, 2335 .set_tunable = &vsc85xx_set_tunable, 2336 .read_page = &vsc85xx_phy_read_page, 2337 .write_page = &vsc85xx_phy_write_page, 2338 .get_sset_count = &vsc85xx_get_sset_count, 2339 .get_strings = &vsc85xx_get_strings, 2340 .get_stats = &vsc85xx_get_stats, 2341 }, 2342 { 2343 .phy_id = PHY_ID_VSC8540, 2344 .name = "Microsemi FE VSC8540 SyncE", 2345 .phy_id_mask = 0xfffffff0, 2346 /* PHY_BASIC_FEATURES */ 2347 .soft_reset = &genphy_soft_reset, 2348 .config_init = &vsc85xx_config_init, 2349 .config_aneg = &vsc85xx_config_aneg, 2350 .read_status = &vsc85xx_read_status, 2351 .handle_interrupt = vsc85xx_handle_interrupt, 2352 .config_intr = &vsc85xx_config_intr, 2353 .suspend = &genphy_suspend, 2354 .resume = &genphy_resume, 2355 .probe = &vsc85xx_probe, 2356 .set_wol = &vsc85xx_wol_set, 2357 .get_wol = &vsc85xx_wol_get, 2358 .get_tunable = &vsc85xx_get_tunable, 2359 .set_tunable = &vsc85xx_set_tunable, 2360 .read_page = &vsc85xx_phy_read_page, 2361 .write_page = &vsc85xx_phy_write_page, 2362 .get_sset_count = &vsc85xx_get_sset_count, 2363 .get_strings = &vsc85xx_get_strings, 2364 .get_stats = &vsc85xx_get_stats, 2365 }, 2366 { 2367 .phy_id = PHY_ID_VSC8541, 2368 .name = "Microsemi VSC8541 SyncE", 2369 .phy_id_mask = 0xfffffff0, 2370 /* PHY_GBIT_FEATURES */ 2371 .soft_reset = &genphy_soft_reset, 2372 .config_init = &vsc85xx_config_init, 2373 .config_aneg = &vsc85xx_config_aneg, 2374 .read_status = &vsc85xx_read_status, 2375 .handle_interrupt = vsc85xx_handle_interrupt, 2376 .config_intr = &vsc85xx_config_intr, 2377 .suspend = &genphy_suspend, 2378 .resume = &genphy_resume, 2379 .probe = &vsc85xx_probe, 2380 .set_wol = &vsc85xx_wol_set, 2381 .get_wol = &vsc85xx_wol_get, 2382 .get_tunable = &vsc85xx_get_tunable, 2383 .set_tunable = &vsc85xx_set_tunable, 2384 .read_page = &vsc85xx_phy_read_page, 2385 .write_page = &vsc85xx_phy_write_page, 2386 .get_sset_count = &vsc85xx_get_sset_count, 2387 .get_strings = &vsc85xx_get_strings, 2388 .get_stats = &vsc85xx_get_stats, 2389 }, 2390 { 2391 .phy_id = PHY_ID_VSC8552, 2392 .name = "Microsemi GE VSC8552 SyncE", 2393 .phy_id_mask = 0xfffffff0, 2394 /* PHY_GBIT_FEATURES */ 2395 .soft_reset = &genphy_soft_reset, 2396 .config_init = &vsc8584_config_init, 2397 .config_aneg = &vsc85xx_config_aneg, 2398 .read_status = &vsc85xx_read_status, 2399 .handle_interrupt = vsc85xx_handle_interrupt, 2400 .config_intr = &vsc85xx_config_intr, 2401 .suspend = &genphy_suspend, 2402 .resume = &genphy_resume, 2403 .probe = &vsc8574_probe, 2404 .set_wol = &vsc85xx_wol_set, 2405 .get_wol = &vsc85xx_wol_get, 2406 .get_tunable = &vsc85xx_get_tunable, 2407 .set_tunable = &vsc85xx_set_tunable, 2408 .read_page = &vsc85xx_phy_read_page, 2409 .write_page = &vsc85xx_phy_write_page, 2410 .get_sset_count = &vsc85xx_get_sset_count, 2411 .get_strings = &vsc85xx_get_strings, 2412 .get_stats = &vsc85xx_get_stats, 2413 }, 2414 { 2415 .phy_id = PHY_ID_VSC856X, 2416 .name = "Microsemi GE VSC856X SyncE", 2417 .phy_id_mask = 0xfffffff0, 2418 /* PHY_GBIT_FEATURES */ 2419 .soft_reset = &genphy_soft_reset, 2420 .config_init = &vsc8584_config_init, 2421 .config_aneg = &vsc85xx_config_aneg, 2422 .read_status = &vsc85xx_read_status, 2423 .handle_interrupt = vsc85xx_handle_interrupt, 2424 .config_intr = &vsc85xx_config_intr, 2425 .suspend = &genphy_suspend, 2426 .resume = &genphy_resume, 2427 .probe = &vsc8584_probe, 2428 .get_tunable = &vsc85xx_get_tunable, 2429 .set_tunable = &vsc85xx_set_tunable, 2430 .read_page = &vsc85xx_phy_read_page, 2431 .write_page = &vsc85xx_phy_write_page, 2432 .get_sset_count = &vsc85xx_get_sset_count, 2433 .get_strings = &vsc85xx_get_strings, 2434 .get_stats = &vsc85xx_get_stats, 2435 }, 2436 { 2437 .phy_id = PHY_ID_VSC8572, 2438 .name = "Microsemi GE VSC8572 SyncE", 2439 .phy_id_mask = 0xfffffff0, 2440 /* PHY_GBIT_FEATURES */ 2441 .soft_reset = &genphy_soft_reset, 2442 .config_init = &vsc8584_config_init, 2443 .config_aneg = &vsc85xx_config_aneg, 2444 .aneg_done = &genphy_aneg_done, 2445 .read_status = &vsc85xx_read_status, 2446 .handle_interrupt = &vsc8584_handle_interrupt, 2447 .config_intr = &vsc85xx_config_intr, 2448 .suspend = &genphy_suspend, 2449 .resume = &genphy_resume, 2450 .probe = &vsc8574_probe, 2451 .set_wol = &vsc85xx_wol_set, 2452 .get_wol = &vsc85xx_wol_get, 2453 .get_tunable = &vsc85xx_get_tunable, 2454 .set_tunable = &vsc85xx_set_tunable, 2455 .read_page = &vsc85xx_phy_read_page, 2456 .write_page = &vsc85xx_phy_write_page, 2457 .get_sset_count = &vsc85xx_get_sset_count, 2458 .get_strings = &vsc85xx_get_strings, 2459 .get_stats = &vsc85xx_get_stats, 2460 }, 2461 { 2462 .phy_id = PHY_ID_VSC8574, 2463 .name = "Microsemi GE VSC8574 SyncE", 2464 .phy_id_mask = 0xfffffff0, 2465 /* PHY_GBIT_FEATURES */ 2466 .soft_reset = &genphy_soft_reset, 2467 .config_init = &vsc8584_config_init, 2468 .config_aneg = &vsc85xx_config_aneg, 2469 .aneg_done = &genphy_aneg_done, 2470 .read_status = &vsc85xx_read_status, 2471 .handle_interrupt = vsc85xx_handle_interrupt, 2472 .config_intr = &vsc85xx_config_intr, 2473 .suspend = &genphy_suspend, 2474 .resume = &genphy_resume, 2475 .probe = &vsc8574_probe, 2476 .set_wol = &vsc85xx_wol_set, 2477 .get_wol = &vsc85xx_wol_get, 2478 .get_tunable = &vsc85xx_get_tunable, 2479 .set_tunable = &vsc85xx_set_tunable, 2480 .read_page = &vsc85xx_phy_read_page, 2481 .write_page = &vsc85xx_phy_write_page, 2482 .get_sset_count = &vsc85xx_get_sset_count, 2483 .get_strings = &vsc85xx_get_strings, 2484 .get_stats = &vsc85xx_get_stats, 2485 }, 2486 { 2487 .phy_id = PHY_ID_VSC8575, 2488 .name = "Microsemi GE VSC8575 SyncE", 2489 .phy_id_mask = 0xfffffff0, 2490 /* PHY_GBIT_FEATURES */ 2491 .soft_reset = &genphy_soft_reset, 2492 .config_init = &vsc8584_config_init, 2493 .config_aneg = &vsc85xx_config_aneg, 2494 .aneg_done = &genphy_aneg_done, 2495 .read_status = &vsc85xx_read_status, 2496 .handle_interrupt = &vsc8584_handle_interrupt, 2497 .config_intr = &vsc85xx_config_intr, 2498 .suspend = &genphy_suspend, 2499 .resume = &genphy_resume, 2500 .probe = &vsc8584_probe, 2501 .get_tunable = &vsc85xx_get_tunable, 2502 .set_tunable = &vsc85xx_set_tunable, 2503 .read_page = &vsc85xx_phy_read_page, 2504 .write_page = &vsc85xx_phy_write_page, 2505 .get_sset_count = &vsc85xx_get_sset_count, 2506 .get_strings = &vsc85xx_get_strings, 2507 .get_stats = &vsc85xx_get_stats, 2508 }, 2509 { 2510 .phy_id = PHY_ID_VSC8582, 2511 .name = "Microsemi GE VSC8582 SyncE", 2512 .phy_id_mask = 0xfffffff0, 2513 /* PHY_GBIT_FEATURES */ 2514 .soft_reset = &genphy_soft_reset, 2515 .config_init = &vsc8584_config_init, 2516 .config_aneg = &vsc85xx_config_aneg, 2517 .aneg_done = &genphy_aneg_done, 2518 .read_status = &vsc85xx_read_status, 2519 .handle_interrupt = &vsc8584_handle_interrupt, 2520 .config_intr = &vsc85xx_config_intr, 2521 .suspend = &genphy_suspend, 2522 .resume = &genphy_resume, 2523 .probe = &vsc8584_probe, 2524 .get_tunable = &vsc85xx_get_tunable, 2525 .set_tunable = &vsc85xx_set_tunable, 2526 .read_page = &vsc85xx_phy_read_page, 2527 .write_page = &vsc85xx_phy_write_page, 2528 .get_sset_count = &vsc85xx_get_sset_count, 2529 .get_strings = &vsc85xx_get_strings, 2530 .get_stats = &vsc85xx_get_stats, 2531 }, 2532 { 2533 .phy_id = PHY_ID_VSC8584, 2534 .name = "Microsemi GE VSC8584 SyncE", 2535 .phy_id_mask = 0xfffffff0, 2536 /* PHY_GBIT_FEATURES */ 2537 .soft_reset = &genphy_soft_reset, 2538 .config_init = &vsc8584_config_init, 2539 .config_aneg = &vsc85xx_config_aneg, 2540 .aneg_done = &genphy_aneg_done, 2541 .read_status = &vsc85xx_read_status, 2542 .handle_interrupt = &vsc8584_handle_interrupt, 2543 .config_intr = &vsc85xx_config_intr, 2544 .suspend = &genphy_suspend, 2545 .resume = &genphy_resume, 2546 .probe = &vsc8584_probe, 2547 .get_tunable = &vsc85xx_get_tunable, 2548 .set_tunable = &vsc85xx_set_tunable, 2549 .read_page = &vsc85xx_phy_read_page, 2550 .write_page = &vsc85xx_phy_write_page, 2551 .get_sset_count = &vsc85xx_get_sset_count, 2552 .get_strings = &vsc85xx_get_strings, 2553 .get_stats = &vsc85xx_get_stats, 2554 .link_change_notify = &vsc85xx_link_change_notify, 2555 } 2556 2557 }; 2558 2559 module_phy_driver(vsc85xx_driver); 2560 2561 static struct mdio_device_id __maybe_unused vsc85xx_tbl[] = { 2562 { PHY_ID_VSC8504, 0xfffffff0, }, 2563 { PHY_ID_VSC8514, 0xfffffff0, }, 2564 { PHY_ID_VSC8530, 0xfffffff0, }, 2565 { PHY_ID_VSC8531, 0xfffffff0, }, 2566 { PHY_ID_VSC8540, 0xfffffff0, }, 2567 { PHY_ID_VSC8541, 0xfffffff0, }, 2568 { PHY_ID_VSC8552, 0xfffffff0, }, 2569 { PHY_ID_VSC856X, 0xfffffff0, }, 2570 { PHY_ID_VSC8572, 0xfffffff0, }, 2571 { PHY_ID_VSC8574, 0xfffffff0, }, 2572 { PHY_ID_VSC8575, 0xfffffff0, }, 2573 { PHY_ID_VSC8582, 0xfffffff0, }, 2574 { PHY_ID_VSC8584, 0xfffffff0, }, 2575 { } 2576 }; 2577 2578 MODULE_DEVICE_TABLE(mdio, vsc85xx_tbl); 2579 2580 MODULE_DESCRIPTION("Microsemi VSC85xx PHY driver"); 2581 MODULE_AUTHOR("Nagaraju Lakkaraju"); 2582 MODULE_LICENSE("Dual MIT/GPL"); 2583