1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2 /* 3 * Driver for Microsemi VSC85xx PHYs 4 * 5 * Copyright (c) 2020 Microsemi Corporation 6 */ 7 8 #ifndef _MSCC_PHY_MACSEC_H_ 9 #define _MSCC_PHY_MACSEC_H_ 10 11 #include <net/macsec.h> 12 13 #define MSCC_MS_MAX_FLOWS 16 14 15 #define CONTROL_TYPE_EGRESS 0x6 16 #define CONTROL_TYPE_INGRESS 0xf 17 #define CONTROL_IV0 BIT(5) 18 #define CONTROL_IV1 BIT(6) 19 #define CONTROL_IV2 BIT(7) 20 #define CONTROL_UPDATE_SEQ BIT(13) 21 #define CONTROL_IV_IN_SEQ BIT(14) 22 #define CONTROL_ENCRYPT_AUTH BIT(15) 23 #define CONTROL_KEY_IN_CTX BIT(16) 24 #define CONTROL_CRYPTO_ALG(x) ((x) << 17) 25 #define CTRYPTO_ALG_AES_CTR_128 0x5 26 #define CTRYPTO_ALG_AES_CTR_192 0x6 27 #define CTRYPTO_ALG_AES_CTR_256 0x7 28 #define CONTROL_DIGEST_TYPE(x) ((x) << 21) 29 #define CONTROL_AUTH_ALG(x) ((x) << 23) 30 #define AUTH_ALG_AES_GHAS 0x4 31 #define CONTROL_AN(x) ((x) << 26) 32 #define CONTROL_SEQ_TYPE(x) ((x) << 28) 33 #define CONTROL_SEQ_MASK BIT(30) 34 #define CONTROL_CONTEXT_ID BIT(31) 35 36 enum mscc_macsec_destination_ports { 37 MSCC_MS_PORT_COMMON = 0, 38 MSCC_MS_PORT_RSVD = 1, 39 MSCC_MS_PORT_CONTROLLED = 2, 40 MSCC_MS_PORT_UNCONTROLLED = 3, 41 }; 42 43 enum mscc_macsec_drop_actions { 44 MSCC_MS_ACTION_BYPASS_CRC = 0, 45 MSCC_MS_ACTION_BYPASS_BAD = 1, 46 MSCC_MS_ACTION_DROP = 2, 47 MSCC_MS_ACTION_BYPASS = 3, 48 }; 49 50 enum mscc_macsec_flow_types { 51 MSCC_MS_FLOW_BYPASS = 0, 52 MSCC_MS_FLOW_DROP = 1, 53 MSCC_MS_FLOW_INGRESS = 2, 54 MSCC_MS_FLOW_EGRESS = 3, 55 }; 56 57 enum mscc_macsec_validate_levels { 58 MSCC_MS_VALIDATE_DISABLED = 0, 59 MSCC_MS_VALIDATE_CHECK = 1, 60 MSCC_MS_VALIDATE_STRICT = 2, 61 }; 62 63 enum macsec_bank { 64 FC_BUFFER = 0x04, 65 HOST_MAC = 0x05, 66 LINE_MAC = 0x06, 67 PROC_0 = 0x0e, 68 PROC_2 = 0x0f, 69 MACSEC_INGR = 0x38, 70 MACSEC_EGR = 0x3c, 71 }; 72 73 struct macsec_flow { 74 struct list_head list; 75 enum mscc_macsec_destination_ports port; 76 enum macsec_bank bank; 77 u32 index; 78 int assoc_num; 79 bool has_transformation; 80 81 /* Highest takes precedence [0..15] */ 82 u8 priority; 83 84 u8 key[MACSEC_KEYID_LEN]; 85 86 union { 87 struct macsec_rx_sa *rx_sa; 88 struct macsec_tx_sa *tx_sa; 89 }; 90 91 /* Matching */ 92 struct { 93 u8 sci:1; 94 u8 tagged:1; 95 u8 untagged:1; 96 u8 etype:1; 97 } match; 98 99 u16 etype; 100 101 /* Action */ 102 struct { 103 u8 bypass:1; 104 u8 drop:1; 105 } action; 106 }; 107 108 #define MSCC_EXT_PAGE_MACSEC_17 17 109 #define MSCC_EXT_PAGE_MACSEC_18 18 110 111 #define MSCC_EXT_PAGE_MACSEC_19 19 112 #define MSCC_PHY_MACSEC_19_REG_ADDR(x) (x) 113 #define MSCC_PHY_MACSEC_19_TARGET(x) ((x) << 12) 114 #define MSCC_PHY_MACSEC_19_READ BIT(14) 115 #define MSCC_PHY_MACSEC_19_CMD BIT(15) 116 117 #define MSCC_EXT_PAGE_MACSEC_20 20 118 #define MSCC_PHY_MACSEC_20_TARGET(x) (x) 119 120 #define MSCC_MS_XFORM_REC(x, y) (((x) << 5) + (y)) 121 #define MSCC_MS_ENA_CFG 0x800 122 #define MSCC_MS_FC_CFG 0x804 123 #define MSCC_MS_SAM_MAC_SA_MATCH_LO(x) (0x1000 + ((x) << 4)) 124 #define MSCC_MS_SAM_MAC_SA_MATCH_HI(x) (0x1001 + ((x) << 4)) 125 #define MSCC_MS_SAM_MISC_MATCH(x) (0x1004 + ((x) << 4)) 126 #define MSCC_MS_SAM_MATCH_SCI_LO(x) (0x1005 + ((x) << 4)) 127 #define MSCC_MS_SAM_MATCH_SCI_HI(x) (0x1006 + ((x) << 4)) 128 #define MSCC_MS_SAM_MASK(x) (0x1007 + ((x) << 4)) 129 #define MSCC_MS_SAM_ENTRY_SET1 0x1808 130 #define MSCC_MS_SAM_ENTRY_CLEAR1 0x180c 131 #define MSCC_MS_SAM_FLOW_CTRL(x) (0x1c00 + (x)) 132 #define MSCC_MS_SAM_CP_TAG 0x1e40 133 #define MSCC_MS_SAM_NM_FLOW_NCP 0x1e51 134 #define MSCC_MS_SAM_NM_FLOW_CP 0x1e52 135 #define MSCC_MS_MISC_CONTROL 0x1e5f 136 #define MSCC_MS_COUNT_CONTROL 0x3204 137 #define MSCC_MS_PARAMS2_IG_CC_CONTROL 0x3a10 138 #define MSCC_MS_PARAMS2_IG_CP_TAG 0x3a14 139 #define MSCC_MS_VLAN_MTU_CHECK(x) (0x3c40 + (x)) 140 #define MSCC_MS_NON_VLAN_MTU_CHECK 0x3c48 141 #define MSCC_MS_PP_CTRL 0x3c4b 142 #define MSCC_MS_STATUS_CONTEXT_CTRL 0x3d02 143 #define MSCC_MS_INTR_CTRL_STATUS 0x3d04 144 #define MSCC_MS_BLOCK_CTX_UPDATE 0x3d0c 145 #define MSCC_MS_AIC_CTRL 0x3e02 146 147 /* MACSEC_ENA_CFG */ 148 #define MSCC_MS_ENA_CFG_CLK_ENA BIT(0) 149 #define MSCC_MS_ENA_CFG_SW_RST BIT(1) 150 #define MSCC_MS_ENA_CFG_MACSEC_BYPASS_ENA BIT(8) 151 #define MSCC_MS_ENA_CFG_MACSEC_ENA BIT(9) 152 #define MSCC_MS_ENA_CFG_MACSEC_SPEED_MODE(x) ((x) << 10) 153 #define MSCC_MS_ENA_CFG_MACSEC_SPEED_MODE_M GENMASK(12, 10) 154 155 /* MACSEC_FC_CFG */ 156 #define MSCC_MS_FC_CFG_FCBUF_ENA BIT(0) 157 #define MSCC_MS_FC_CFG_USE_PKT_EXPANSION_INDICATION BIT(1) 158 #define MSCC_MS_FC_CFG_LOW_THRESH(x) ((x) << 4) 159 #define MSCC_MS_FC_CFG_LOW_THRESH_M GENMASK(7, 4) 160 #define MSCC_MS_FC_CFG_HIGH_THRESH(x) ((x) << 8) 161 #define MSCC_MS_FC_CFG_HIGH_THRESH_M GENMASK(11, 8) 162 #define MSCC_MS_FC_CFG_LOW_BYTES_VAL(x) ((x) << 12) 163 #define MSCC_MS_FC_CFG_LOW_BYTES_VAL_M GENMASK(14, 12) 164 #define MSCC_MS_FC_CFG_HIGH_BYTES_VAL(x) ((x) << 16) 165 #define MSCC_MS_FC_CFG_HIGH_BYTES_VAL_M GENMASK(18, 16) 166 167 /* MSCC_MS_SAM_MAC_SA_MATCH_HI */ 168 #define MSCC_MS_SAM_MAC_SA_MATCH_HI_ETYPE(x) ((x) << 16) 169 #define MSCC_MS_SAM_MAC_SA_MATCH_HI_ETYPE_M GENMASK(31, 16) 170 171 /* MACSEC_SAM_MISC_MATCH */ 172 #define MSCC_MS_SAM_MISC_MATCH_VLAN_VALID BIT(0) 173 #define MSCC_MS_SAM_MISC_MATCH_QINQ_FOUND BIT(1) 174 #define MSCC_MS_SAM_MISC_MATCH_STAG_VALID BIT(2) 175 #define MSCC_MS_SAM_MISC_MATCH_QTAG_VALID BIT(3) 176 #define MSCC_MS_SAM_MISC_MATCH_VLAN_UP(x) ((x) << 4) 177 #define MSCC_MS_SAM_MISC_MATCH_VLAN_UP_M GENMASK(6, 4) 178 #define MSCC_MS_SAM_MISC_MATCH_CONTROL_PACKET BIT(7) 179 #define MSCC_MS_SAM_MISC_MATCH_UNTAGGED BIT(8) 180 #define MSCC_MS_SAM_MISC_MATCH_TAGGED BIT(9) 181 #define MSCC_MS_SAM_MISC_MATCH_BAD_TAG BIT(10) 182 #define MSCC_MS_SAM_MISC_MATCH_KAY_TAG BIT(11) 183 #define MSCC_MS_SAM_MISC_MATCH_SOURCE_PORT(x) ((x) << 12) 184 #define MSCC_MS_SAM_MISC_MATCH_SOURCE_PORT_M GENMASK(13, 12) 185 #define MSCC_MS_SAM_MISC_MATCH_PRIORITY(x) ((x) << 16) 186 #define MSCC_MS_SAM_MISC_MATCH_PRIORITY_M GENMASK(19, 16) 187 #define MSCC_MS_SAM_MISC_MATCH_AN(x) ((x) << 24) 188 #define MSCC_MS_SAM_MISC_MATCH_TCI(x) ((x) << 26) 189 190 /* MACSEC_SAM_MASK */ 191 #define MSCC_MS_SAM_MASK_MAC_SA_MASK(x) (x) 192 #define MSCC_MS_SAM_MASK_MAC_SA_MASK_M GENMASK(5, 0) 193 #define MSCC_MS_SAM_MASK_MAC_DA_MASK(x) ((x) << 6) 194 #define MSCC_MS_SAM_MASK_MAC_DA_MASK_M GENMASK(11, 6) 195 #define MSCC_MS_SAM_MASK_MAC_ETYPE_MASK BIT(12) 196 #define MSCC_MS_SAM_MASK_VLAN_VLD_MASK BIT(13) 197 #define MSCC_MS_SAM_MASK_QINQ_FOUND_MASK BIT(14) 198 #define MSCC_MS_SAM_MASK_STAG_VLD_MASK BIT(15) 199 #define MSCC_MS_SAM_MASK_QTAG_VLD_MASK BIT(16) 200 #define MSCC_MS_SAM_MASK_VLAN_UP_MASK BIT(17) 201 #define MSCC_MS_SAM_MASK_VLAN_ID_MASK BIT(18) 202 #define MSCC_MS_SAM_MASK_SOURCE_PORT_MASK BIT(19) 203 #define MSCC_MS_SAM_MASK_CTL_PACKET_MASK BIT(20) 204 #define MSCC_MS_SAM_MASK_VLAN_UP_INNER_MASK BIT(21) 205 #define MSCC_MS_SAM_MASK_VLAN_ID_INNER_MASK BIT(22) 206 #define MSCC_MS_SAM_MASK_SCI_MASK BIT(23) 207 #define MSCC_MS_SAM_MASK_AN_MASK(x) ((x) << 24) 208 #define MSCC_MS_SAM_MASK_TCI_MASK(x) ((x) << 26) 209 210 /* MACSEC_SAM_FLOW_CTRL_EGR */ 211 #define MSCC_MS_SAM_FLOW_CTRL_FLOW_TYPE(x) (x) 212 #define MSCC_MS_SAM_FLOW_CTRL_FLOW_TYPE_M GENMASK(1, 0) 213 #define MSCC_MS_SAM_FLOW_CTRL_DEST_PORT(x) ((x) << 2) 214 #define MSCC_MS_SAM_FLOW_CTRL_DEST_PORT_M GENMASK(3, 2) 215 #define MSCC_MS_SAM_FLOW_CTRL_RESV_4 BIT(4) 216 #define MSCC_MS_SAM_FLOW_CTRL_FLOW_CRYPT_AUTH BIT(5) 217 #define MSCC_MS_SAM_FLOW_CTRL_DROP_ACTION(x) ((x) << 6) 218 #define MSCC_MS_SAM_FLOW_CTRL_DROP_ACTION_M GENMASK(7, 6) 219 #define MSCC_MS_SAM_FLOW_CTRL_RESV_15_TO_8(x) ((x) << 8) 220 #define MSCC_MS_SAM_FLOW_CTRL_RESV_15_TO_8_M GENMASK(15, 8) 221 #define MSCC_MS_SAM_FLOW_CTRL_PROTECT_FRAME BIT(16) 222 #define MSCC_MS_SAM_FLOW_CTRL_REPLAY_PROTECT BIT(16) 223 #define MSCC_MS_SAM_FLOW_CTRL_SA_IN_USE BIT(17) 224 #define MSCC_MS_SAM_FLOW_CTRL_INCLUDE_SCI BIT(18) 225 #define MSCC_MS_SAM_FLOW_CTRL_USE_ES BIT(19) 226 #define MSCC_MS_SAM_FLOW_CTRL_USE_SCB BIT(20) 227 #define MSCC_MS_SAM_FLOW_CTRL_VALIDATE_FRAMES(x) ((x) << 19) 228 #define MSCC_MS_SAM_FLOW_CTRL_TAG_BYPASS_SIZE(x) ((x) << 21) 229 #define MSCC_MS_SAM_FLOW_CTRL_TAG_BYPASS_SIZE_M GENMASK(22, 21) 230 #define MSCC_MS_SAM_FLOW_CTRL_RESV_23 BIT(23) 231 #define MSCC_MS_SAM_FLOW_CTRL_CONFIDENTIALITY_OFFSET(x) ((x) << 24) 232 #define MSCC_MS_SAM_FLOW_CTRL_CONFIDENTIALITY_OFFSET_M GENMASK(30, 24) 233 #define MSCC_MS_SAM_FLOW_CTRL_CONF_PROTECT BIT(31) 234 235 /* MACSEC_SAM_CP_TAG */ 236 #define MSCC_MS_SAM_CP_TAG_MAP_TBL(x) (x) 237 #define MSCC_MS_SAM_CP_TAG_MAP_TBL_M GENMASK(23, 0) 238 #define MSCC_MS_SAM_CP_TAG_DEF_UP(x) ((x) << 24) 239 #define MSCC_MS_SAM_CP_TAG_DEF_UP_M GENMASK(26, 24) 240 #define MSCC_MS_SAM_CP_TAG_STAG_UP_EN BIT(27) 241 #define MSCC_MS_SAM_CP_TAG_QTAG_UP_EN BIT(28) 242 #define MSCC_MS_SAM_CP_TAG_PARSE_QINQ BIT(29) 243 #define MSCC_MS_SAM_CP_TAG_PARSE_STAG BIT(30) 244 #define MSCC_MS_SAM_CP_TAG_PARSE_QTAG BIT(31) 245 246 /* MACSEC_SAM_NM_FLOW_NCP */ 247 #define MSCC_MS_SAM_NM_FLOW_NCP_UNTAGGED_FLOW_TYPE(x) (x) 248 #define MSCC_MS_SAM_NM_FLOW_NCP_UNTAGGED_DEST_PORT(x) ((x) << 2) 249 #define MSCC_MS_SAM_NM_FLOW_NCP_UNTAGGED_DROP_ACTION(x) ((x) << 6) 250 #define MSCC_MS_SAM_NM_FLOW_NCP_TAGGED_FLOW_TYPE(x) ((x) << 8) 251 #define MSCC_MS_SAM_NM_FLOW_NCP_TAGGED_DEST_PORT(x) ((x) << 10) 252 #define MSCC_MS_SAM_NM_FLOW_NCP_TAGGED_DROP_ACTION(x) ((x) << 14) 253 #define MSCC_MS_SAM_NM_FLOW_NCP_BADTAG_FLOW_TYPE(x) ((x) << 16) 254 #define MSCC_MS_SAM_NM_FLOW_NCP_BADTAG_DEST_PORT(x) ((x) << 18) 255 #define MSCC_MS_SAM_NM_FLOW_NCP_BADTAG_DROP_ACTION(x) ((x) << 22) 256 #define MSCC_MS_SAM_NM_FLOW_NCP_KAY_FLOW_TYPE(x) ((x) << 24) 257 #define MSCC_MS_SAM_NM_FLOW_NCP_KAY_DEST_PORT(x) ((x) << 26) 258 #define MSCC_MS_SAM_NM_FLOW_NCP_KAY_DROP_ACTION(x) ((x) << 30) 259 260 /* MACSEC_SAM_NM_FLOW_CP */ 261 #define MSCC_MS_SAM_NM_FLOW_CP_UNTAGGED_FLOW_TYPE(x) (x) 262 #define MSCC_MS_SAM_NM_FLOW_CP_UNTAGGED_DEST_PORT(x) ((x) << 2) 263 #define MSCC_MS_SAM_NM_FLOW_CP_UNTAGGED_DROP_ACTION(x) ((x) << 6) 264 #define MSCC_MS_SAM_NM_FLOW_CP_TAGGED_FLOW_TYPE(x) ((x) << 8) 265 #define MSCC_MS_SAM_NM_FLOW_CP_TAGGED_DEST_PORT(x) ((x) << 10) 266 #define MSCC_MS_SAM_NM_FLOW_CP_TAGGED_DROP_ACTION(x) ((x) << 14) 267 #define MSCC_MS_SAM_NM_FLOW_CP_BADTAG_FLOW_TYPE(x) ((x) << 16) 268 #define MSCC_MS_SAM_NM_FLOW_CP_BADTAG_DEST_PORT(x) ((x) << 18) 269 #define MSCC_MS_SAM_NM_FLOW_CP_BADTAG_DROP_ACTION(x) ((x) << 22) 270 #define MSCC_MS_SAM_NM_FLOW_CP_KAY_FLOW_TYPE(x) ((x) << 24) 271 #define MSCC_MS_SAM_NM_FLOW_CP_KAY_DEST_PORT(x) ((x) << 26) 272 #define MSCC_MS_SAM_NM_FLOW_CP_KAY_DROP_ACTION(x) ((x) << 30) 273 274 /* MACSEC_MISC_CONTROL */ 275 #define MSCC_MS_MISC_CONTROL_MC_LATENCY_FIX(x) (x) 276 #define MSCC_MS_MISC_CONTROL_MC_LATENCY_FIX_M GENMASK(5, 0) 277 #define MSCC_MS_MISC_CONTROL_STATIC_BYPASS BIT(8) 278 #define MSCC_MS_MISC_CONTROL_NM_MACSEC_EN BIT(9) 279 #define MSCC_MS_MISC_CONTROL_VALIDATE_FRAMES(x) ((x) << 10) 280 #define MSCC_MS_MISC_CONTROL_VALIDATE_FRAMES_M GENMASK(11, 10) 281 #define MSCC_MS_MISC_CONTROL_XFORM_REC_SIZE(x) ((x) << 24) 282 #define MSCC_MS_MISC_CONTROL_XFORM_REC_SIZE_M GENMASK(25, 24) 283 284 /* MACSEC_COUNT_CONTROL */ 285 #define MSCC_MS_COUNT_CONTROL_RESET_ALL BIT(0) 286 #define MSCC_MS_COUNT_CONTROL_DEBUG_ACCESS BIT(1) 287 #define MSCC_MS_COUNT_CONTROL_SATURATE_CNTRS BIT(2) 288 #define MSCC_MS_COUNT_CONTROL_AUTO_CNTR_RESET BIT(3) 289 290 /* MACSEC_PARAMS2_IG_CC_CONTROL */ 291 #define MSCC_MS_PARAMS2_IG_CC_CONTROL_NON_MATCH_CTRL_ACT BIT(14) 292 #define MSCC_MS_PARAMS2_IG_CC_CONTROL_NON_MATCH_ACT BIT(15) 293 294 /* MACSEC_PARAMS2_IG_CP_TAG */ 295 #define MSCC_MS_PARAMS2_IG_CP_TAG_MAP_TBL(x) (x) 296 #define MSCC_MS_PARAMS2_IG_CP_TAG_MAP_TBL_M GENMASK(23, 0) 297 #define MSCC_MS_PARAMS2_IG_CP_TAG_DEF_UP(x) ((x) << 24) 298 #define MSCC_MS_PARAMS2_IG_CP_TAG_DEF_UP_M GENMASK(26, 24) 299 #define MSCC_MS_PARAMS2_IG_CP_TAG_STAG_UP_EN BIT(27) 300 #define MSCC_MS_PARAMS2_IG_CP_TAG_QTAG_UP_EN BIT(28) 301 #define MSCC_MS_PARAMS2_IG_CP_TAG_PARSE_QINQ BIT(29) 302 #define MSCC_MS_PARAMS2_IG_CP_TAG_PARSE_STAG BIT(30) 303 #define MSCC_MS_PARAMS2_IG_CP_TAG_PARSE_QTAG BIT(31) 304 305 /* MACSEC_VLAN_MTU_CHECK */ 306 #define MSCC_MS_VLAN_MTU_CHECK_MTU_COMPARE(x) (x) 307 #define MSCC_MS_VLAN_MTU_CHECK_MTU_COMPARE_M GENMASK(14, 0) 308 #define MSCC_MS_VLAN_MTU_CHECK_MTU_COMP_DROP BIT(15) 309 310 /* MACSEC_NON_VLAN_MTU_CHECK */ 311 #define MSCC_MS_NON_VLAN_MTU_CHECK_NV_MTU_COMPARE(x) (x) 312 #define MSCC_MS_NON_VLAN_MTU_CHECK_NV_MTU_COMPARE_M GENMASK(14, 0) 313 #define MSCC_MS_NON_VLAN_MTU_CHECK_NV_MTU_COMP_DROP BIT(15) 314 315 /* MACSEC_PP_CTRL */ 316 #define MSCC_MS_PP_CTRL_MACSEC_OCTET_INCR_MODE BIT(0) 317 318 /* MACSEC_INTR_CTRL_STATUS */ 319 #define MSCC_MS_INTR_CTRL_STATUS_INTR_CLR_STATUS(x) (x) 320 #define MSCC_MS_INTR_CTRL_STATUS_INTR_CLR_STATUS_M GENMASK(15, 0) 321 #define MSCC_MS_INTR_CTRL_STATUS_INTR_ENABLE(x) ((x) << 16) 322 #define MSCC_MS_INTR_CTRL_STATUS_INTR_ENABLE_M GENMASK(31, 16) 323 #define MACSEC_INTR_CTRL_STATUS_ROLLOVER BIT(5) 324 325 #endif /* _MSCC_PHY_MACSEC_H_ */ 326