1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Driver for Microchip 10BASE-T1S LAN867X PHY 4 * 5 * Support: Microchip Phys: 6 * lan8670, lan8671, lan8672 7 */ 8 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/phy.h> 12 13 #define PHY_ID_LAN867X 0x0007C160 14 15 #define LAN867X_REG_IRQ_1_CTL 0x001C 16 #define LAN867X_REG_IRQ_2_CTL 0x001D 17 18 /* The arrays below are pulled from the following table from AN1699 19 * Access MMD Address Value Mask 20 * RMW 0x1F 0x00D0 0x0002 0x0E03 21 * RMW 0x1F 0x00D1 0x0000 0x0300 22 * RMW 0x1F 0x0084 0x3380 0xFFC0 23 * RMW 0x1F 0x0085 0x0006 0x000F 24 * RMW 0x1F 0x008A 0xC000 0xF800 25 * RMW 0x1F 0x0087 0x801C 0x801C 26 * RMW 0x1F 0x0088 0x033F 0x1FFF 27 * W 0x1F 0x008B 0x0404 ------ 28 * RMW 0x1F 0x0080 0x0600 0x0600 29 * RMW 0x1F 0x00F1 0x2400 0x7F00 30 * RMW 0x1F 0x0096 0x2000 0x2000 31 * W 0x1F 0x0099 0x7F80 ------ 32 */ 33 34 static const int lan867x_fixup_registers[12] = { 35 0x00D0, 0x00D1, 0x0084, 0x0085, 36 0x008A, 0x0087, 0x0088, 0x008B, 37 0x0080, 0x00F1, 0x0096, 0x0099, 38 }; 39 40 static const int lan867x_fixup_values[12] = { 41 0x0002, 0x0000, 0x3380, 0x0006, 42 0xC000, 0x801C, 0x033F, 0x0404, 43 0x0600, 0x2400, 0x2000, 0x7F80, 44 }; 45 46 static const int lan867x_fixup_masks[12] = { 47 0x0E03, 0x0300, 0xFFC0, 0x000F, 48 0xF800, 0x801C, 0x1FFF, 0xFFFF, 49 0x0600, 0x7F00, 0x2000, 0xFFFF, 50 }; 51 52 static int lan867x_config_init(struct phy_device *phydev) 53 { 54 /* HW quirk: Microchip states in the application note (AN1699) for the phy 55 * that a set of read-modify-write (rmw) operations has to be performed 56 * on a set of seemingly magic registers. 57 * The result of these operations is just described as 'optimal performance' 58 * Microchip gives no explanation as to what these mmd regs do, 59 * in fact they are marked as reserved in the datasheet. 60 * It is unclear if phy_modify_mmd would be safe to use or if a write 61 * really has to happen to each register. 62 * In order to exactly conform to what is stated in the AN phy_write_mmd is 63 * used, which might then write the same value back as read + modified. 64 */ 65 66 int reg_value; 67 int err; 68 int reg; 69 70 /* Read-Modified Write Pseudocode (from AN1699) 71 * current_val = read_register(mmd, addr) // Read current register value 72 * new_val = current_val AND (NOT mask) // Clear bit fields to be written 73 * new_val = new_val OR value // Set bits 74 * write_register(mmd, addr, new_val) // Write back updated register value 75 */ 76 for (int i = 0; i < ARRAY_SIZE(lan867x_fixup_registers); i++) { 77 reg = lan867x_fixup_registers[i]; 78 reg_value = phy_read_mmd(phydev, MDIO_MMD_VEND2, reg); 79 reg_value &= ~lan867x_fixup_masks[i]; 80 reg_value |= lan867x_fixup_values[i]; 81 err = phy_write_mmd(phydev, MDIO_MMD_VEND2, reg, reg_value); 82 if (err != 0) 83 return err; 84 } 85 86 /* None of the interrupts in the lan867x phy seem relevant. 87 * Other phys inspect the link status and call phy_trigger_machine 88 * in the interrupt handler. 89 * This phy does not support link status, and thus has no interrupt 90 * for it either. 91 * So we'll just disable all interrupts on the chip. 92 */ 93 err = phy_write_mmd(phydev, MDIO_MMD_VEND2, LAN867X_REG_IRQ_1_CTL, 0xFFFF); 94 if (err != 0) 95 return err; 96 return phy_write_mmd(phydev, MDIO_MMD_VEND2, LAN867X_REG_IRQ_2_CTL, 0xFFFF); 97 } 98 99 static int lan867x_read_status(struct phy_device *phydev) 100 { 101 /* The phy has some limitations, namely: 102 * - always reports link up 103 * - only supports 10MBit half duplex 104 * - does not support auto negotiate 105 */ 106 phydev->link = 1; 107 phydev->duplex = DUPLEX_HALF; 108 phydev->speed = SPEED_10; 109 phydev->autoneg = AUTONEG_DISABLE; 110 111 return 0; 112 } 113 114 static struct phy_driver lan867x_driver[] = { 115 { 116 PHY_ID_MATCH_MODEL(PHY_ID_LAN867X), 117 .name = "LAN867X", 118 .features = PHY_BASIC_T1S_P2MP_FEATURES, 119 .config_init = lan867x_config_init, 120 .read_status = lan867x_read_status, 121 .get_plca_cfg = genphy_c45_plca_get_cfg, 122 .set_plca_cfg = genphy_c45_plca_set_cfg, 123 .get_plca_status = genphy_c45_plca_get_status, 124 } 125 }; 126 127 module_phy_driver(lan867x_driver); 128 129 static struct mdio_device_id __maybe_unused tbl[] = { 130 { PHY_ID_MATCH_MODEL(PHY_ID_LAN867X) }, 131 { } 132 }; 133 134 MODULE_DEVICE_TABLE(mdio, tbl); 135 136 MODULE_DESCRIPTION("Microchip 10BASE-T1S lan867x Phy driver"); 137 MODULE_AUTHOR("Ramón Nordin Rodriguez"); 138 MODULE_LICENSE("GPL"); 139