1 // SPDX-License-Identifier: GPL-2.0+ 2 #include <linux/bitfield.h> 3 #include <linux/module.h> 4 #include <linux/nvmem-consumer.h> 5 #include <linux/pinctrl/consumer.h> 6 #include <linux/phy.h> 7 8 #define MTK_GPHY_ID_MT7981 0x03a29461 9 #define MTK_GPHY_ID_MT7988 0x03a29481 10 11 #define MTK_EXT_PAGE_ACCESS 0x1f 12 #define MTK_PHY_PAGE_STANDARD 0x0000 13 #define MTK_PHY_PAGE_EXTENDED_3 0x0003 14 15 #define MTK_PHY_LPI_REG_14 0x14 16 #define MTK_PHY_LPI_WAKE_TIMER_1000_MASK GENMASK(8, 0) 17 18 #define MTK_PHY_LPI_REG_1c 0x1c 19 #define MTK_PHY_SMI_DET_ON_THRESH_MASK GENMASK(13, 8) 20 21 #define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30 22 #define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5 23 24 #define ANALOG_INTERNAL_OPERATION_MAX_US 20 25 #define TXRESERVE_MIN 0 26 #define TXRESERVE_MAX 7 27 28 #define MTK_PHY_ANARG_RG 0x10 29 #define MTK_PHY_TCLKOFFSET_MASK GENMASK(12, 8) 30 31 /* Registers on MDIO_MMD_VEND1 */ 32 #define MTK_PHY_TXVLD_DA_RG 0x12 33 #define MTK_PHY_DA_TX_I2MPB_A_GBE_MASK GENMASK(15, 10) 34 #define MTK_PHY_DA_TX_I2MPB_A_TBT_MASK GENMASK(5, 0) 35 36 #define MTK_PHY_TX_I2MPB_TEST_MODE_A2 0x16 37 #define MTK_PHY_DA_TX_I2MPB_A_HBT_MASK GENMASK(15, 10) 38 #define MTK_PHY_DA_TX_I2MPB_A_TST_MASK GENMASK(5, 0) 39 40 #define MTK_PHY_TX_I2MPB_TEST_MODE_B1 0x17 41 #define MTK_PHY_DA_TX_I2MPB_B_GBE_MASK GENMASK(13, 8) 42 #define MTK_PHY_DA_TX_I2MPB_B_TBT_MASK GENMASK(5, 0) 43 44 #define MTK_PHY_TX_I2MPB_TEST_MODE_B2 0x18 45 #define MTK_PHY_DA_TX_I2MPB_B_HBT_MASK GENMASK(13, 8) 46 #define MTK_PHY_DA_TX_I2MPB_B_TST_MASK GENMASK(5, 0) 47 48 #define MTK_PHY_TX_I2MPB_TEST_MODE_C1 0x19 49 #define MTK_PHY_DA_TX_I2MPB_C_GBE_MASK GENMASK(13, 8) 50 #define MTK_PHY_DA_TX_I2MPB_C_TBT_MASK GENMASK(5, 0) 51 52 #define MTK_PHY_TX_I2MPB_TEST_MODE_C2 0x20 53 #define MTK_PHY_DA_TX_I2MPB_C_HBT_MASK GENMASK(13, 8) 54 #define MTK_PHY_DA_TX_I2MPB_C_TST_MASK GENMASK(5, 0) 55 56 #define MTK_PHY_TX_I2MPB_TEST_MODE_D1 0x21 57 #define MTK_PHY_DA_TX_I2MPB_D_GBE_MASK GENMASK(13, 8) 58 #define MTK_PHY_DA_TX_I2MPB_D_TBT_MASK GENMASK(5, 0) 59 60 #define MTK_PHY_TX_I2MPB_TEST_MODE_D2 0x22 61 #define MTK_PHY_DA_TX_I2MPB_D_HBT_MASK GENMASK(13, 8) 62 #define MTK_PHY_DA_TX_I2MPB_D_TST_MASK GENMASK(5, 0) 63 64 #define MTK_PHY_RXADC_CTRL_RG7 0xc6 65 #define MTK_PHY_DA_AD_BUF_BIAS_LP_MASK GENMASK(9, 8) 66 67 #define MTK_PHY_RXADC_CTRL_RG9 0xc8 68 #define MTK_PHY_DA_RX_PSBN_TBT_MASK GENMASK(14, 12) 69 #define MTK_PHY_DA_RX_PSBN_HBT_MASK GENMASK(10, 8) 70 #define MTK_PHY_DA_RX_PSBN_GBE_MASK GENMASK(6, 4) 71 #define MTK_PHY_DA_RX_PSBN_LP_MASK GENMASK(2, 0) 72 73 #define MTK_PHY_LDO_OUTPUT_V 0xd7 74 75 #define MTK_PHY_RG_ANA_CAL_RG0 0xdb 76 #define MTK_PHY_RG_CAL_CKINV BIT(12) 77 #define MTK_PHY_RG_ANA_CALEN BIT(8) 78 #define MTK_PHY_RG_ZCALEN_A BIT(0) 79 80 #define MTK_PHY_RG_ANA_CAL_RG1 0xdc 81 #define MTK_PHY_RG_ZCALEN_B BIT(12) 82 #define MTK_PHY_RG_ZCALEN_C BIT(8) 83 #define MTK_PHY_RG_ZCALEN_D BIT(4) 84 #define MTK_PHY_RG_TXVOS_CALEN BIT(0) 85 86 #define MTK_PHY_RG_ANA_CAL_RG5 0xe0 87 #define MTK_PHY_RG_REXT_TRIM_MASK GENMASK(13, 8) 88 89 #define MTK_PHY_RG_TX_FILTER 0xfe 90 91 #define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120 0x120 92 #define MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK GENMASK(12, 8) 93 #define MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK GENMASK(4, 0) 94 95 #define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122 0x122 96 #define MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK GENMASK(7, 0) 97 98 #define MTK_PHY_RG_TESTMUX_ADC_CTRL 0x144 99 #define MTK_PHY_RG_TXEN_DIG_MASK GENMASK(5, 5) 100 101 #define MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B 0x172 102 #define MTK_PHY_CR_TX_AMP_OFFSET_A_MASK GENMASK(13, 8) 103 #define MTK_PHY_CR_TX_AMP_OFFSET_B_MASK GENMASK(6, 0) 104 105 #define MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D 0x173 106 #define MTK_PHY_CR_TX_AMP_OFFSET_C_MASK GENMASK(13, 8) 107 #define MTK_PHY_CR_TX_AMP_OFFSET_D_MASK GENMASK(6, 0) 108 109 #define MTK_PHY_RG_AD_CAL_COMP 0x17a 110 #define MTK_PHY_AD_CAL_COMP_OUT_SHIFT (8) 111 112 #define MTK_PHY_RG_AD_CAL_CLK 0x17b 113 #define MTK_PHY_DA_CAL_CLK BIT(0) 114 115 #define MTK_PHY_RG_AD_CALIN 0x17c 116 #define MTK_PHY_DA_CALIN_FLAG BIT(0) 117 118 #define MTK_PHY_RG_DASN_DAC_IN0_A 0x17d 119 #define MTK_PHY_DASN_DAC_IN0_A_MASK GENMASK(9, 0) 120 121 #define MTK_PHY_RG_DASN_DAC_IN0_B 0x17e 122 #define MTK_PHY_DASN_DAC_IN0_B_MASK GENMASK(9, 0) 123 124 #define MTK_PHY_RG_DASN_DAC_IN0_C 0x17f 125 #define MTK_PHY_DASN_DAC_IN0_C_MASK GENMASK(9, 0) 126 127 #define MTK_PHY_RG_DASN_DAC_IN0_D 0x180 128 #define MTK_PHY_DASN_DAC_IN0_D_MASK GENMASK(9, 0) 129 130 #define MTK_PHY_RG_DASN_DAC_IN1_A 0x181 131 #define MTK_PHY_DASN_DAC_IN1_A_MASK GENMASK(9, 0) 132 133 #define MTK_PHY_RG_DASN_DAC_IN1_B 0x182 134 #define MTK_PHY_DASN_DAC_IN1_B_MASK GENMASK(9, 0) 135 136 #define MTK_PHY_RG_DASN_DAC_IN1_C 0x183 137 #define MTK_PHY_DASN_DAC_IN1_C_MASK GENMASK(9, 0) 138 139 #define MTK_PHY_RG_DASN_DAC_IN1_D 0x184 140 #define MTK_PHY_DASN_DAC_IN1_D_MASK GENMASK(9, 0) 141 142 #define MTK_PHY_RG_DEV1E_REG19b 0x19b 143 #define MTK_PHY_BYPASS_DSP_LPI_READY BIT(8) 144 145 #define MTK_PHY_RG_LP_IIR2_K1_L 0x22a 146 #define MTK_PHY_RG_LP_IIR2_K1_U 0x22b 147 #define MTK_PHY_RG_LP_IIR2_K2_L 0x22c 148 #define MTK_PHY_RG_LP_IIR2_K2_U 0x22d 149 #define MTK_PHY_RG_LP_IIR2_K3_L 0x22e 150 #define MTK_PHY_RG_LP_IIR2_K3_U 0x22f 151 #define MTK_PHY_RG_LP_IIR2_K4_L 0x230 152 #define MTK_PHY_RG_LP_IIR2_K4_U 0x231 153 #define MTK_PHY_RG_LP_IIR2_K5_L 0x232 154 #define MTK_PHY_RG_LP_IIR2_K5_U 0x233 155 156 #define MTK_PHY_RG_DEV1E_REG234 0x234 157 #define MTK_PHY_TR_OPEN_LOOP_EN_MASK GENMASK(0, 0) 158 #define MTK_PHY_LPF_X_AVERAGE_MASK GENMASK(7, 4) 159 #define MTK_PHY_TR_LP_IIR_EEE_EN BIT(12) 160 161 #define MTK_PHY_RG_LPF_CNT_VAL 0x235 162 163 #define MTK_PHY_RG_DEV1E_REG238 0x238 164 #define MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK GENMASK(8, 0) 165 #define MTK_PHY_LPI_SLV_SEND_TX_EN BIT(12) 166 167 #define MTK_PHY_RG_DEV1E_REG239 0x239 168 #define MTK_PHY_LPI_SEND_LOC_TIMER_MASK GENMASK(8, 0) 169 #define MTK_PHY_LPI_TXPCS_LOC_RCV BIT(12) 170 171 #define MTK_PHY_RG_DEV1E_REG27C 0x27c 172 #define MTK_PHY_VGASTATE_FFE_THR_ST1_MASK GENMASK(12, 8) 173 #define MTK_PHY_RG_DEV1E_REG27D 0x27d 174 #define MTK_PHY_VGASTATE_FFE_THR_ST2_MASK GENMASK(4, 0) 175 176 #define MTK_PHY_RG_DEV1E_REG2C7 0x2c7 177 #define MTK_PHY_MAX_GAIN_MASK GENMASK(4, 0) 178 #define MTK_PHY_MIN_GAIN_MASK GENMASK(12, 8) 179 180 #define MTK_PHY_RG_DEV1E_REG2D1 0x2d1 181 #define MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK GENMASK(7, 0) 182 #define MTK_PHY_LPI_SKIP_SD_SLV_TR BIT(8) 183 #define MTK_PHY_LPI_TR_READY BIT(9) 184 #define MTK_PHY_LPI_VCO_EEE_STG0_EN BIT(10) 185 186 #define MTK_PHY_RG_DEV1E_REG323 0x323 187 #define MTK_PHY_EEE_WAKE_MAS_INT_DC BIT(0) 188 #define MTK_PHY_EEE_WAKE_SLV_INT_DC BIT(4) 189 190 #define MTK_PHY_RG_DEV1E_REG324 0x324 191 #define MTK_PHY_SMI_DETCNT_MAX_MASK GENMASK(5, 0) 192 #define MTK_PHY_SMI_DET_MAX_EN BIT(8) 193 194 #define MTK_PHY_RG_DEV1E_REG326 0x326 195 #define MTK_PHY_LPI_MODE_SD_ON BIT(0) 196 #define MTK_PHY_RESET_RANDUPD_CNT BIT(1) 197 #define MTK_PHY_TREC_UPDATE_ENAB_CLR BIT(2) 198 #define MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF BIT(4) 199 #define MTK_PHY_TR_READY_SKIP_AFE_WAKEUP BIT(5) 200 201 #define MTK_PHY_LDO_PUMP_EN_PAIRAB 0x502 202 #define MTK_PHY_LDO_PUMP_EN_PAIRCD 0x503 203 204 #define MTK_PHY_DA_TX_R50_PAIR_A 0x53d 205 #define MTK_PHY_DA_TX_R50_PAIR_B 0x53e 206 #define MTK_PHY_DA_TX_R50_PAIR_C 0x53f 207 #define MTK_PHY_DA_TX_R50_PAIR_D 0x540 208 209 #define MTK_PHY_RG_BG_RASEL 0x115 210 #define MTK_PHY_RG_BG_RASEL_MASK GENMASK(2, 0) 211 212 /* These macro privides efuse parsing for internal phy. */ 213 #define EFS_DA_TX_I2MPB_A(x) (((x) >> 0) & GENMASK(5, 0)) 214 #define EFS_DA_TX_I2MPB_B(x) (((x) >> 6) & GENMASK(5, 0)) 215 #define EFS_DA_TX_I2MPB_C(x) (((x) >> 12) & GENMASK(5, 0)) 216 #define EFS_DA_TX_I2MPB_D(x) (((x) >> 18) & GENMASK(5, 0)) 217 #define EFS_DA_TX_AMP_OFFSET_A(x) (((x) >> 24) & GENMASK(5, 0)) 218 219 #define EFS_DA_TX_AMP_OFFSET_B(x) (((x) >> 0) & GENMASK(5, 0)) 220 #define EFS_DA_TX_AMP_OFFSET_C(x) (((x) >> 6) & GENMASK(5, 0)) 221 #define EFS_DA_TX_AMP_OFFSET_D(x) (((x) >> 12) & GENMASK(5, 0)) 222 #define EFS_DA_TX_R50_A(x) (((x) >> 18) & GENMASK(5, 0)) 223 #define EFS_DA_TX_R50_B(x) (((x) >> 24) & GENMASK(5, 0)) 224 225 #define EFS_DA_TX_R50_C(x) (((x) >> 0) & GENMASK(5, 0)) 226 #define EFS_DA_TX_R50_D(x) (((x) >> 6) & GENMASK(5, 0)) 227 228 #define EFS_RG_BG_RASEL(x) (((x) >> 4) & GENMASK(2, 0)) 229 #define EFS_RG_REXT_TRIM(x) (((x) >> 7) & GENMASK(5, 0)) 230 231 enum { 232 NO_PAIR, 233 PAIR_A, 234 PAIR_B, 235 PAIR_C, 236 PAIR_D, 237 }; 238 239 enum { 240 GPHY_PORT0, 241 GPHY_PORT1, 242 GPHY_PORT2, 243 GPHY_PORT3, 244 }; 245 246 enum calibration_mode { 247 EFUSE_K, 248 SW_K 249 }; 250 251 enum CAL_ITEM { 252 REXT, 253 TX_OFFSET, 254 TX_AMP, 255 TX_R50, 256 TX_VCM 257 }; 258 259 enum CAL_MODE { 260 EFUSE_M, 261 SW_M 262 }; 263 264 static int mtk_socphy_read_page(struct phy_device *phydev) 265 { 266 return __phy_read(phydev, MTK_EXT_PAGE_ACCESS); 267 } 268 269 static int mtk_socphy_write_page(struct phy_device *phydev, int page) 270 { 271 return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page); 272 } 273 274 /* One calibration cycle consists of: 275 * 1.Set DA_CALIN_FLAG high to start calibration. Keep it high 276 * until AD_CAL_COMP is ready to output calibration result. 277 * 2.Wait until DA_CAL_CLK is available. 278 * 3.Fetch AD_CAL_COMP_OUT. 279 */ 280 static int cal_cycle(struct phy_device *phydev, int devad, 281 u32 regnum, u16 mask, u16 cal_val) 282 { 283 int reg_val; 284 int ret; 285 286 phy_modify_mmd(phydev, devad, regnum, 287 mask, cal_val); 288 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN, 289 MTK_PHY_DA_CALIN_FLAG); 290 291 ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, 292 MTK_PHY_RG_AD_CAL_CLK, reg_val, 293 reg_val & MTK_PHY_DA_CAL_CLK, 500, 294 ANALOG_INTERNAL_OPERATION_MAX_US, false); 295 if (ret) { 296 phydev_err(phydev, "Calibration cycle timeout\n"); 297 return ret; 298 } 299 300 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN, 301 MTK_PHY_DA_CALIN_FLAG); 302 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CAL_COMP) >> 303 MTK_PHY_AD_CAL_COMP_OUT_SHIFT; 304 phydev_dbg(phydev, "cal_val: 0x%x, ret: %d\n", cal_val, ret); 305 306 return ret; 307 } 308 309 static int rext_fill_result(struct phy_device *phydev, u16 *buf) 310 { 311 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5, 312 MTK_PHY_RG_REXT_TRIM_MASK, buf[0] << 8); 313 phy_modify_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_RG_BG_RASEL, 314 MTK_PHY_RG_BG_RASEL_MASK, buf[1]); 315 316 return 0; 317 } 318 319 static int rext_cal_efuse(struct phy_device *phydev, u32 *buf) 320 { 321 u16 rext_cal_val[2]; 322 323 rext_cal_val[0] = EFS_RG_REXT_TRIM(buf[3]); 324 rext_cal_val[1] = EFS_RG_BG_RASEL(buf[3]); 325 rext_fill_result(phydev, rext_cal_val); 326 327 return 0; 328 } 329 330 static int tx_offset_fill_result(struct phy_device *phydev, u16 *buf) 331 { 332 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B, 333 MTK_PHY_CR_TX_AMP_OFFSET_A_MASK, buf[0] << 8); 334 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B, 335 MTK_PHY_CR_TX_AMP_OFFSET_B_MASK, buf[1]); 336 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D, 337 MTK_PHY_CR_TX_AMP_OFFSET_C_MASK, buf[2] << 8); 338 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D, 339 MTK_PHY_CR_TX_AMP_OFFSET_D_MASK, buf[3]); 340 341 return 0; 342 } 343 344 static int tx_offset_cal_efuse(struct phy_device *phydev, u32 *buf) 345 { 346 u16 tx_offset_cal_val[4]; 347 348 tx_offset_cal_val[0] = EFS_DA_TX_AMP_OFFSET_A(buf[0]); 349 tx_offset_cal_val[1] = EFS_DA_TX_AMP_OFFSET_B(buf[1]); 350 tx_offset_cal_val[2] = EFS_DA_TX_AMP_OFFSET_C(buf[1]); 351 tx_offset_cal_val[3] = EFS_DA_TX_AMP_OFFSET_D(buf[1]); 352 353 tx_offset_fill_result(phydev, tx_offset_cal_val); 354 355 return 0; 356 } 357 358 static int tx_amp_fill_result(struct phy_device *phydev, u16 *buf) 359 { 360 int i; 361 int bias[16] = {}; 362 const int vals_9461[16] = { 7, 1, 4, 7, 363 7, 1, 4, 7, 364 7, 1, 4, 7, 365 7, 1, 4, 7 }; 366 const int vals_9481[16] = { 10, 6, 6, 10, 367 10, 6, 6, 10, 368 10, 6, 6, 10, 369 10, 6, 6, 10 }; 370 switch (phydev->drv->phy_id) { 371 case MTK_GPHY_ID_MT7981: 372 /* We add some calibration to efuse values 373 * due to board level influence. 374 * GBE: +7, TBT: +1, HBT: +4, TST: +7 375 */ 376 memcpy(bias, (const void *)vals_9461, sizeof(bias)); 377 break; 378 case MTK_GPHY_ID_MT7988: 379 memcpy(bias, (const void *)vals_9481, sizeof(bias)); 380 break; 381 } 382 383 /* Prevent overflow */ 384 for (i = 0; i < 12; i++) { 385 if (buf[i >> 2] + bias[i] > 63) { 386 buf[i >> 2] = 63; 387 bias[i] = 0; 388 } 389 } 390 391 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG, 392 MTK_PHY_DA_TX_I2MPB_A_GBE_MASK, (buf[0] + bias[0]) << 10); 393 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG, 394 MTK_PHY_DA_TX_I2MPB_A_TBT_MASK, buf[0] + bias[1]); 395 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2, 396 MTK_PHY_DA_TX_I2MPB_A_HBT_MASK, (buf[0] + bias[2]) << 10); 397 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2, 398 MTK_PHY_DA_TX_I2MPB_A_TST_MASK, buf[0] + bias[3]); 399 400 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1, 401 MTK_PHY_DA_TX_I2MPB_B_GBE_MASK, (buf[1] + bias[4]) << 8); 402 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1, 403 MTK_PHY_DA_TX_I2MPB_B_TBT_MASK, buf[1] + bias[5]); 404 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2, 405 MTK_PHY_DA_TX_I2MPB_B_HBT_MASK, (buf[1] + bias[6]) << 8); 406 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2, 407 MTK_PHY_DA_TX_I2MPB_B_TST_MASK, buf[1] + bias[7]); 408 409 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1, 410 MTK_PHY_DA_TX_I2MPB_C_GBE_MASK, (buf[2] + bias[8]) << 8); 411 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1, 412 MTK_PHY_DA_TX_I2MPB_C_TBT_MASK, buf[2] + bias[9]); 413 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2, 414 MTK_PHY_DA_TX_I2MPB_C_HBT_MASK, (buf[2] + bias[10]) << 8); 415 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2, 416 MTK_PHY_DA_TX_I2MPB_C_TST_MASK, buf[2] + bias[11]); 417 418 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1, 419 MTK_PHY_DA_TX_I2MPB_D_GBE_MASK, (buf[3] + bias[12]) << 8); 420 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1, 421 MTK_PHY_DA_TX_I2MPB_D_TBT_MASK, buf[3] + bias[13]); 422 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2, 423 MTK_PHY_DA_TX_I2MPB_D_HBT_MASK, (buf[3] + bias[14]) << 8); 424 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2, 425 MTK_PHY_DA_TX_I2MPB_D_TST_MASK, buf[3] + bias[15]); 426 427 return 0; 428 } 429 430 static int tx_amp_cal_efuse(struct phy_device *phydev, u32 *buf) 431 { 432 u16 tx_amp_cal_val[4]; 433 434 tx_amp_cal_val[0] = EFS_DA_TX_I2MPB_A(buf[0]); 435 tx_amp_cal_val[1] = EFS_DA_TX_I2MPB_B(buf[0]); 436 tx_amp_cal_val[2] = EFS_DA_TX_I2MPB_C(buf[0]); 437 tx_amp_cal_val[3] = EFS_DA_TX_I2MPB_D(buf[0]); 438 tx_amp_fill_result(phydev, tx_amp_cal_val); 439 440 return 0; 441 } 442 443 static int tx_r50_fill_result(struct phy_device *phydev, u16 tx_r50_cal_val, 444 u8 txg_calen_x) 445 { 446 int bias = 0; 447 u16 reg, val; 448 449 if (phydev->drv->phy_id == MTK_GPHY_ID_MT7988) 450 bias = -2; 451 452 val = clamp_val(bias + tx_r50_cal_val, 0, 63); 453 454 switch (txg_calen_x) { 455 case PAIR_A: 456 reg = MTK_PHY_DA_TX_R50_PAIR_A; 457 break; 458 case PAIR_B: 459 reg = MTK_PHY_DA_TX_R50_PAIR_B; 460 break; 461 case PAIR_C: 462 reg = MTK_PHY_DA_TX_R50_PAIR_C; 463 break; 464 case PAIR_D: 465 reg = MTK_PHY_DA_TX_R50_PAIR_D; 466 break; 467 default: 468 return -EINVAL; 469 } 470 471 phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, val | val << 8); 472 473 return 0; 474 } 475 476 static int tx_r50_cal_efuse(struct phy_device *phydev, u32 *buf, 477 u8 txg_calen_x) 478 { 479 u16 tx_r50_cal_val; 480 481 switch (txg_calen_x) { 482 case PAIR_A: 483 tx_r50_cal_val = EFS_DA_TX_R50_A(buf[1]); 484 break; 485 case PAIR_B: 486 tx_r50_cal_val = EFS_DA_TX_R50_B(buf[1]); 487 break; 488 case PAIR_C: 489 tx_r50_cal_val = EFS_DA_TX_R50_C(buf[2]); 490 break; 491 case PAIR_D: 492 tx_r50_cal_val = EFS_DA_TX_R50_D(buf[2]); 493 break; 494 default: 495 return -EINVAL; 496 } 497 tx_r50_fill_result(phydev, tx_r50_cal_val, txg_calen_x); 498 499 return 0; 500 } 501 502 static int tx_vcm_cal_sw(struct phy_device *phydev, u8 rg_txreserve_x) 503 { 504 u8 lower_idx, upper_idx, txreserve_val; 505 u8 lower_ret, upper_ret; 506 int ret; 507 508 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, 509 MTK_PHY_RG_ANA_CALEN); 510 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, 511 MTK_PHY_RG_CAL_CKINV); 512 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, 513 MTK_PHY_RG_TXVOS_CALEN); 514 515 switch (rg_txreserve_x) { 516 case PAIR_A: 517 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 518 MTK_PHY_RG_DASN_DAC_IN0_A, 519 MTK_PHY_DASN_DAC_IN0_A_MASK); 520 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 521 MTK_PHY_RG_DASN_DAC_IN1_A, 522 MTK_PHY_DASN_DAC_IN1_A_MASK); 523 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, 524 MTK_PHY_RG_ANA_CAL_RG0, 525 MTK_PHY_RG_ZCALEN_A); 526 break; 527 case PAIR_B: 528 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 529 MTK_PHY_RG_DASN_DAC_IN0_B, 530 MTK_PHY_DASN_DAC_IN0_B_MASK); 531 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 532 MTK_PHY_RG_DASN_DAC_IN1_B, 533 MTK_PHY_DASN_DAC_IN1_B_MASK); 534 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, 535 MTK_PHY_RG_ANA_CAL_RG1, 536 MTK_PHY_RG_ZCALEN_B); 537 break; 538 case PAIR_C: 539 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 540 MTK_PHY_RG_DASN_DAC_IN0_C, 541 MTK_PHY_DASN_DAC_IN0_C_MASK); 542 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 543 MTK_PHY_RG_DASN_DAC_IN1_C, 544 MTK_PHY_DASN_DAC_IN1_C_MASK); 545 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, 546 MTK_PHY_RG_ANA_CAL_RG1, 547 MTK_PHY_RG_ZCALEN_C); 548 break; 549 case PAIR_D: 550 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 551 MTK_PHY_RG_DASN_DAC_IN0_D, 552 MTK_PHY_DASN_DAC_IN0_D_MASK); 553 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 554 MTK_PHY_RG_DASN_DAC_IN1_D, 555 MTK_PHY_DASN_DAC_IN1_D_MASK); 556 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, 557 MTK_PHY_RG_ANA_CAL_RG1, 558 MTK_PHY_RG_ZCALEN_D); 559 break; 560 default: 561 ret = -EINVAL; 562 goto restore; 563 } 564 565 lower_idx = TXRESERVE_MIN; 566 upper_idx = TXRESERVE_MAX; 567 568 phydev_dbg(phydev, "Start TX-VCM SW cal.\n"); 569 while ((upper_idx - lower_idx) > 1) { 570 txreserve_val = DIV_ROUND_CLOSEST(lower_idx + upper_idx, 2); 571 ret = cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, 572 MTK_PHY_DA_RX_PSBN_TBT_MASK | 573 MTK_PHY_DA_RX_PSBN_HBT_MASK | 574 MTK_PHY_DA_RX_PSBN_GBE_MASK | 575 MTK_PHY_DA_RX_PSBN_LP_MASK, 576 txreserve_val << 12 | txreserve_val << 8 | 577 txreserve_val << 4 | txreserve_val); 578 if (ret == 1) { 579 upper_idx = txreserve_val; 580 upper_ret = ret; 581 } else if (ret == 0) { 582 lower_idx = txreserve_val; 583 lower_ret = ret; 584 } else { 585 goto restore; 586 } 587 } 588 589 if (lower_idx == TXRESERVE_MIN) { 590 lower_ret = cal_cycle(phydev, MDIO_MMD_VEND1, 591 MTK_PHY_RXADC_CTRL_RG9, 592 MTK_PHY_DA_RX_PSBN_TBT_MASK | 593 MTK_PHY_DA_RX_PSBN_HBT_MASK | 594 MTK_PHY_DA_RX_PSBN_GBE_MASK | 595 MTK_PHY_DA_RX_PSBN_LP_MASK, 596 lower_idx << 12 | lower_idx << 8 | 597 lower_idx << 4 | lower_idx); 598 ret = lower_ret; 599 } else if (upper_idx == TXRESERVE_MAX) { 600 upper_ret = cal_cycle(phydev, MDIO_MMD_VEND1, 601 MTK_PHY_RXADC_CTRL_RG9, 602 MTK_PHY_DA_RX_PSBN_TBT_MASK | 603 MTK_PHY_DA_RX_PSBN_HBT_MASK | 604 MTK_PHY_DA_RX_PSBN_GBE_MASK | 605 MTK_PHY_DA_RX_PSBN_LP_MASK, 606 upper_idx << 12 | upper_idx << 8 | 607 upper_idx << 4 | upper_idx); 608 ret = upper_ret; 609 } 610 if (ret < 0) 611 goto restore; 612 613 /* We calibrate TX-VCM in different logic. Check upper index and then 614 * lower index. If this calibration is valid, apply lower index's result. 615 */ 616 ret = upper_ret - lower_ret; 617 if (ret == 1) { 618 ret = 0; 619 /* Make sure we use upper_idx in our calibration system */ 620 cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, 621 MTK_PHY_DA_RX_PSBN_TBT_MASK | 622 MTK_PHY_DA_RX_PSBN_HBT_MASK | 623 MTK_PHY_DA_RX_PSBN_GBE_MASK | 624 MTK_PHY_DA_RX_PSBN_LP_MASK, 625 upper_idx << 12 | upper_idx << 8 | 626 upper_idx << 4 | upper_idx); 627 phydev_dbg(phydev, "TX-VCM SW cal result: 0x%x\n", upper_idx); 628 } else if (lower_idx == TXRESERVE_MIN && upper_ret == 1 && 629 lower_ret == 1) { 630 ret = 0; 631 cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, 632 MTK_PHY_DA_RX_PSBN_TBT_MASK | 633 MTK_PHY_DA_RX_PSBN_HBT_MASK | 634 MTK_PHY_DA_RX_PSBN_GBE_MASK | 635 MTK_PHY_DA_RX_PSBN_LP_MASK, 636 lower_idx << 12 | lower_idx << 8 | 637 lower_idx << 4 | lower_idx); 638 phydev_warn(phydev, "TX-VCM SW cal result at low margin 0x%x\n", 639 lower_idx); 640 } else if (upper_idx == TXRESERVE_MAX && upper_ret == 0 && 641 lower_ret == 0) { 642 ret = 0; 643 phydev_warn(phydev, "TX-VCM SW cal result at high margin 0x%x\n", 644 upper_idx); 645 } else { 646 ret = -EINVAL; 647 } 648 649 restore: 650 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, 651 MTK_PHY_RG_ANA_CALEN); 652 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, 653 MTK_PHY_RG_TXVOS_CALEN); 654 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, 655 MTK_PHY_RG_ZCALEN_A); 656 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, 657 MTK_PHY_RG_ZCALEN_B | MTK_PHY_RG_ZCALEN_C | 658 MTK_PHY_RG_ZCALEN_D); 659 660 return ret; 661 } 662 663 static void mt798x_phy_common_finetune(struct phy_device *phydev) 664 { 665 phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); 666 /* EnabRandUpdTrig = 1 */ 667 __phy_write(phydev, 0x11, 0x2f00); 668 __phy_write(phydev, 0x12, 0xe); 669 __phy_write(phydev, 0x10, 0x8fb0); 670 671 /* NormMseLoThresh = 85 */ 672 __phy_write(phydev, 0x11, 0x55a0); 673 __phy_write(phydev, 0x12, 0x0); 674 __phy_write(phydev, 0x10, 0x83aa); 675 676 /* TrFreeze = 0 */ 677 __phy_write(phydev, 0x11, 0x0); 678 __phy_write(phydev, 0x12, 0x0); 679 __phy_write(phydev, 0x10, 0x9686); 680 681 /* SSTrKp1000Slv = 5 */ 682 __phy_write(phydev, 0x11, 0xbaef); 683 __phy_write(phydev, 0x12, 0x2e); 684 __phy_write(phydev, 0x10, 0x968c); 685 686 /* MrvlTrFix100Kp = 3, MrvlTrFix100Kf = 2, 687 * MrvlTrFix1000Kp = 3, MrvlTrFix1000Kf = 2 688 */ 689 __phy_write(phydev, 0x11, 0xd10a); 690 __phy_write(phydev, 0x12, 0x34); 691 __phy_write(phydev, 0x10, 0x8f82); 692 693 /* VcoSlicerThreshBitsHigh */ 694 __phy_write(phydev, 0x11, 0x5555); 695 __phy_write(phydev, 0x12, 0x55); 696 __phy_write(phydev, 0x10, 0x8ec0); 697 phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); 698 699 /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9*/ 700 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234, 701 MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK, 702 BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9)); 703 704 /* rg_tr_lpf_cnt_val = 512 */ 705 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x200); 706 707 /* IIR2 related */ 708 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_L, 0x82); 709 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_U, 0x0); 710 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_L, 0x103); 711 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_U, 0x0); 712 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_L, 0x82); 713 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_U, 0x0); 714 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_L, 0xd177); 715 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_U, 0x3); 716 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_L, 0x2c82); 717 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_U, 0xe); 718 719 /* FFE peaking */ 720 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27C, 721 MTK_PHY_VGASTATE_FFE_THR_ST1_MASK, 0x1b << 8); 722 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27D, 723 MTK_PHY_VGASTATE_FFE_THR_ST2_MASK, 0x1e); 724 725 /* Disable LDO pump */ 726 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRAB, 0x0); 727 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRCD, 0x0); 728 /* Adjust LDO output voltage */ 729 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_OUTPUT_V, 0x2222); 730 } 731 732 static void mt7981_phy_finetune(struct phy_device *phydev) 733 { 734 u16 val[8] = { 0x01ce, 0x01c1, 735 0x020f, 0x0202, 736 0x03d0, 0x03c0, 737 0x0013, 0x0005 }; 738 int i, k; 739 740 /* 100M eye finetune: 741 * Keep middle level of TX MLT3 shapper as default. 742 * Only change TX MLT3 overshoot level here. 743 */ 744 for (k = 0, i = 1; i < 12; i++) { 745 if (i % 3 == 0) 746 continue; 747 phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[k++]); 748 } 749 750 phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); 751 /* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */ 752 __phy_write(phydev, 0x11, 0xc71); 753 __phy_write(phydev, 0x12, 0xc); 754 __phy_write(phydev, 0x10, 0x8fae); 755 756 /* ResetSyncOffset = 6 */ 757 __phy_write(phydev, 0x11, 0x600); 758 __phy_write(phydev, 0x12, 0x0); 759 __phy_write(phydev, 0x10, 0x8fc0); 760 761 /* VgaDecRate = 1 */ 762 __phy_write(phydev, 0x11, 0x4c2a); 763 __phy_write(phydev, 0x12, 0x3e); 764 __phy_write(phydev, 0x10, 0x8fa4); 765 766 /* FfeUpdGainForce = 4 */ 767 __phy_write(phydev, 0x11, 0x240); 768 __phy_write(phydev, 0x12, 0x0); 769 __phy_write(phydev, 0x10, 0x9680); 770 771 phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); 772 } 773 774 static void mt7988_phy_finetune(struct phy_device *phydev) 775 { 776 u16 val[12] = { 0x0187, 0x01cd, 0x01c8, 0x0182, 777 0x020d, 0x0206, 0x0384, 0x03d0, 778 0x03c6, 0x030a, 0x0011, 0x0005 }; 779 int i; 780 781 /* Set default MLT3 shaper first */ 782 for (i = 0; i < 12; i++) 783 phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[i]); 784 785 /* TCT finetune */ 786 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5); 787 788 /* Disable TX power saving */ 789 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7, 790 MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8); 791 792 phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); 793 794 /* SlvDSPreadyTime = 24, MasDSPreadyTime = 12 */ 795 __phy_write(phydev, 0x11, 0x671); 796 __phy_write(phydev, 0x12, 0xc); 797 __phy_write(phydev, 0x10, 0x8fae); 798 799 /* ResetSyncOffset = 5 */ 800 __phy_write(phydev, 0x11, 0x500); 801 __phy_write(phydev, 0x12, 0x0); 802 __phy_write(phydev, 0x10, 0x8fc0); 803 804 /* VgaDecRate is 1 at default on mt7988 */ 805 806 phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); 807 808 phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_2A30); 809 /* TxClkOffset = 2 */ 810 __phy_modify(phydev, MTK_PHY_ANARG_RG, MTK_PHY_TCLKOFFSET_MASK, 811 FIELD_PREP(MTK_PHY_TCLKOFFSET_MASK, 0x2)); 812 phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); 813 } 814 815 static void mt798x_phy_eee(struct phy_device *phydev) 816 { 817 phy_modify_mmd(phydev, MDIO_MMD_VEND1, 818 MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120, 819 MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK | 820 MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK, 821 FIELD_PREP(MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK, 0x0) | 822 FIELD_PREP(MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK, 0x14)); 823 824 phy_modify_mmd(phydev, MDIO_MMD_VEND1, 825 MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122, 826 MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, 827 FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, 828 0xff)); 829 830 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 831 MTK_PHY_RG_TESTMUX_ADC_CTRL, 832 MTK_PHY_RG_TXEN_DIG_MASK); 833 834 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, 835 MTK_PHY_RG_DEV1E_REG19b, MTK_PHY_BYPASS_DSP_LPI_READY); 836 837 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 838 MTK_PHY_RG_DEV1E_REG234, MTK_PHY_TR_LP_IIR_EEE_EN); 839 840 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG238, 841 MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK | 842 MTK_PHY_LPI_SLV_SEND_TX_EN, 843 FIELD_PREP(MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK, 0x120)); 844 845 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239, 846 MTK_PHY_LPI_SEND_LOC_TIMER_MASK | 847 MTK_PHY_LPI_TXPCS_LOC_RCV, 848 FIELD_PREP(MTK_PHY_LPI_SEND_LOC_TIMER_MASK, 0x117)); 849 850 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2C7, 851 MTK_PHY_MAX_GAIN_MASK | MTK_PHY_MIN_GAIN_MASK, 852 FIELD_PREP(MTK_PHY_MAX_GAIN_MASK, 0x8) | 853 FIELD_PREP(MTK_PHY_MIN_GAIN_MASK, 0x13)); 854 855 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2D1, 856 MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK, 857 FIELD_PREP(MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK, 858 0x33) | 859 MTK_PHY_LPI_SKIP_SD_SLV_TR | MTK_PHY_LPI_TR_READY | 860 MTK_PHY_LPI_VCO_EEE_STG0_EN); 861 862 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG323, 863 MTK_PHY_EEE_WAKE_MAS_INT_DC | 864 MTK_PHY_EEE_WAKE_SLV_INT_DC); 865 866 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG324, 867 MTK_PHY_SMI_DETCNT_MAX_MASK, 868 FIELD_PREP(MTK_PHY_SMI_DETCNT_MAX_MASK, 0x3f) | 869 MTK_PHY_SMI_DET_MAX_EN); 870 871 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG326, 872 MTK_PHY_LPI_MODE_SD_ON | MTK_PHY_RESET_RANDUPD_CNT | 873 MTK_PHY_TREC_UPDATE_ENAB_CLR | 874 MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF | 875 MTK_PHY_TR_READY_SKIP_AFE_WAKEUP); 876 877 phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); 878 /* Regsigdet_sel_1000 = 0 */ 879 __phy_write(phydev, 0x11, 0xb); 880 __phy_write(phydev, 0x12, 0x0); 881 __phy_write(phydev, 0x10, 0x9690); 882 883 /* REG_EEE_st2TrKf1000 = 3 */ 884 __phy_write(phydev, 0x11, 0x114f); 885 __phy_write(phydev, 0x12, 0x2); 886 __phy_write(phydev, 0x10, 0x969a); 887 888 /* RegEEE_slv_wake_tr_timer_tar = 6, RegEEE_slv_remtx_timer_tar = 20 */ 889 __phy_write(phydev, 0x11, 0x3028); 890 __phy_write(phydev, 0x12, 0x0); 891 __phy_write(phydev, 0x10, 0x969e); 892 893 /* RegEEE_slv_wake_int_timer_tar = 8 */ 894 __phy_write(phydev, 0x11, 0x5010); 895 __phy_write(phydev, 0x12, 0x0); 896 __phy_write(phydev, 0x10, 0x96a0); 897 898 /* RegEEE_trfreeze_timer2 = 586 */ 899 __phy_write(phydev, 0x11, 0x24a); 900 __phy_write(phydev, 0x12, 0x0); 901 __phy_write(phydev, 0x10, 0x96a8); 902 903 /* RegEEE100Stg1_tar = 16 */ 904 __phy_write(phydev, 0x11, 0x3210); 905 __phy_write(phydev, 0x12, 0x0); 906 __phy_write(phydev, 0x10, 0x96b8); 907 908 /* REGEEE_wake_slv_tr_wait_dfesigdet_en = 1 */ 909 __phy_write(phydev, 0x11, 0x1463); 910 __phy_write(phydev, 0x12, 0x0); 911 __phy_write(phydev, 0x10, 0x96ca); 912 913 /* DfeTailEnableVgaThresh1000 = 27 */ 914 __phy_write(phydev, 0x11, 0x36); 915 __phy_write(phydev, 0x12, 0x0); 916 __phy_write(phydev, 0x10, 0x8f80); 917 phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); 918 919 phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_3); 920 __phy_modify(phydev, MTK_PHY_LPI_REG_14, MTK_PHY_LPI_WAKE_TIMER_1000_MASK, 921 FIELD_PREP(MTK_PHY_LPI_WAKE_TIMER_1000_MASK, 0x19c)); 922 923 __phy_modify(phydev, MTK_PHY_LPI_REG_1c, MTK_PHY_SMI_DET_ON_THRESH_MASK, 924 FIELD_PREP(MTK_PHY_SMI_DET_ON_THRESH_MASK, 0xc)); 925 phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); 926 927 phy_modify_mmd(phydev, MDIO_MMD_VEND1, 928 MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122, 929 MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, 930 FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, 0xff)); 931 } 932 933 static int cal_sw(struct phy_device *phydev, enum CAL_ITEM cal_item, 934 u8 start_pair, u8 end_pair) 935 { 936 u8 pair_n; 937 int ret; 938 939 for (pair_n = start_pair; pair_n <= end_pair; pair_n++) { 940 /* TX_OFFSET & TX_AMP have no SW calibration. */ 941 switch (cal_item) { 942 case TX_VCM: 943 ret = tx_vcm_cal_sw(phydev, pair_n); 944 break; 945 default: 946 return -EINVAL; 947 } 948 if (ret) 949 return ret; 950 } 951 return 0; 952 } 953 954 static int cal_efuse(struct phy_device *phydev, enum CAL_ITEM cal_item, 955 u8 start_pair, u8 end_pair, u32 *buf) 956 { 957 u8 pair_n; 958 int ret; 959 960 for (pair_n = start_pair; pair_n <= end_pair; pair_n++) { 961 /* TX_VCM has no efuse calibration. */ 962 switch (cal_item) { 963 case REXT: 964 ret = rext_cal_efuse(phydev, buf); 965 break; 966 case TX_OFFSET: 967 ret = tx_offset_cal_efuse(phydev, buf); 968 break; 969 case TX_AMP: 970 ret = tx_amp_cal_efuse(phydev, buf); 971 break; 972 case TX_R50: 973 ret = tx_r50_cal_efuse(phydev, buf, pair_n); 974 break; 975 default: 976 return -EINVAL; 977 } 978 if (ret) 979 return ret; 980 } 981 982 return 0; 983 } 984 985 static int start_cal(struct phy_device *phydev, enum CAL_ITEM cal_item, 986 enum CAL_MODE cal_mode, u8 start_pair, 987 u8 end_pair, u32 *buf) 988 { 989 int ret; 990 991 switch (cal_mode) { 992 case EFUSE_M: 993 ret = cal_efuse(phydev, cal_item, start_pair, 994 end_pair, buf); 995 break; 996 case SW_M: 997 ret = cal_sw(phydev, cal_item, start_pair, end_pair); 998 break; 999 default: 1000 return -EINVAL; 1001 } 1002 1003 if (ret) { 1004 phydev_err(phydev, "cal %d failed\n", cal_item); 1005 return -EIO; 1006 } 1007 1008 return 0; 1009 } 1010 1011 static int mt798x_phy_calibration(struct phy_device *phydev) 1012 { 1013 int ret = 0; 1014 u32 *buf; 1015 size_t len; 1016 struct nvmem_cell *cell; 1017 1018 cell = nvmem_cell_get(&phydev->mdio.dev, "phy-cal-data"); 1019 if (IS_ERR(cell)) { 1020 if (PTR_ERR(cell) == -EPROBE_DEFER) 1021 return PTR_ERR(cell); 1022 return 0; 1023 } 1024 1025 buf = (u32 *)nvmem_cell_read(cell, &len); 1026 if (IS_ERR(buf)) 1027 return PTR_ERR(buf); 1028 nvmem_cell_put(cell); 1029 1030 if (!buf[0] || !buf[1] || !buf[2] || !buf[3] || len < 4 * sizeof(u32)) { 1031 phydev_err(phydev, "invalid efuse data\n"); 1032 ret = -EINVAL; 1033 goto out; 1034 } 1035 1036 ret = start_cal(phydev, REXT, EFUSE_M, NO_PAIR, NO_PAIR, buf); 1037 if (ret) 1038 goto out; 1039 ret = start_cal(phydev, TX_OFFSET, EFUSE_M, NO_PAIR, NO_PAIR, buf); 1040 if (ret) 1041 goto out; 1042 ret = start_cal(phydev, TX_AMP, EFUSE_M, NO_PAIR, NO_PAIR, buf); 1043 if (ret) 1044 goto out; 1045 ret = start_cal(phydev, TX_R50, EFUSE_M, PAIR_A, PAIR_D, buf); 1046 if (ret) 1047 goto out; 1048 ret = start_cal(phydev, TX_VCM, SW_M, PAIR_A, PAIR_A, buf); 1049 if (ret) 1050 goto out; 1051 1052 out: 1053 kfree(buf); 1054 return ret; 1055 } 1056 1057 static int mt798x_phy_config_init(struct phy_device *phydev) 1058 { 1059 switch (phydev->drv->phy_id) { 1060 case MTK_GPHY_ID_MT7981: 1061 mt7981_phy_finetune(phydev); 1062 break; 1063 case MTK_GPHY_ID_MT7988: 1064 mt7988_phy_finetune(phydev); 1065 break; 1066 } 1067 1068 mt798x_phy_common_finetune(phydev); 1069 mt798x_phy_eee(phydev); 1070 1071 return mt798x_phy_calibration(phydev); 1072 } 1073 1074 static struct phy_driver mtk_socphy_driver[] = { 1075 { 1076 PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981), 1077 .name = "MediaTek MT7981 PHY", 1078 .config_init = mt798x_phy_config_init, 1079 .config_intr = genphy_no_config_intr, 1080 .handle_interrupt = genphy_handle_interrupt_no_ack, 1081 .probe = mt798x_phy_calibration, 1082 .suspend = genphy_suspend, 1083 .resume = genphy_resume, 1084 .read_page = mtk_socphy_read_page, 1085 .write_page = mtk_socphy_write_page, 1086 }, 1087 { 1088 PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988), 1089 .name = "MediaTek MT7988 PHY", 1090 .config_init = mt798x_phy_config_init, 1091 .config_intr = genphy_no_config_intr, 1092 .handle_interrupt = genphy_handle_interrupt_no_ack, 1093 .probe = mt798x_phy_calibration, 1094 .suspend = genphy_suspend, 1095 .resume = genphy_resume, 1096 .read_page = mtk_socphy_read_page, 1097 .write_page = mtk_socphy_write_page, 1098 }, 1099 }; 1100 1101 module_phy_driver(mtk_socphy_driver); 1102 1103 static struct mdio_device_id __maybe_unused mtk_socphy_tbl[] = { 1104 { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981) }, 1105 { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988) }, 1106 { } 1107 }; 1108 1109 MODULE_DESCRIPTION("MediaTek SoC Gigabit Ethernet PHY driver"); 1110 MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>"); 1111 MODULE_AUTHOR("SkyLake Huang <SkyLake.Huang@mediatek.com>"); 1112 MODULE_LICENSE("GPL"); 1113 1114 MODULE_DEVICE_TABLE(mdio, mtk_socphy_tbl); 1115