1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Marvell 10G 88x3310 PHY driver 4 * 5 * Based upon the ID registers, this PHY appears to be a mixture of IPs 6 * from two different companies. 7 * 8 * There appears to be several different data paths through the PHY which 9 * are automatically managed by the PHY. The following has been determined 10 * via observation and experimentation for a setup using single-lane Serdes: 11 * 12 * SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G) 13 * 10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G) 14 * 10GBASE-KR PHYXS -- BASE-R PCS -- Fiber 15 * 16 * With XAUI, observation shows: 17 * 18 * XAUI PHYXS -- <appropriate PCS as above> 19 * 20 * and no switching of the host interface mode occurs. 21 * 22 * If both the fiber and copper ports are connected, the first to gain 23 * link takes priority and the other port is completely locked out. 24 */ 25 #include <linux/bitfield.h> 26 #include <linux/ctype.h> 27 #include <linux/delay.h> 28 #include <linux/hwmon.h> 29 #include <linux/marvell_phy.h> 30 #include <linux/phy.h> 31 #include <linux/sfp.h> 32 #include <linux/netdevice.h> 33 34 #define MV_PHY_ALASKA_NBT_QUIRK_MASK 0xfffffffe 35 #define MV_PHY_ALASKA_NBT_QUIRK_REV (MARVELL_PHY_ID_88X3310 | 0xa) 36 37 #define MV_VERSION(a,b,c,d) ((a) << 24 | (b) << 16 | (c) << 8 | (d)) 38 39 enum { 40 MV_PMA_FW_VER0 = 0xc011, 41 MV_PMA_FW_VER1 = 0xc012, 42 MV_PMA_21X0_PORT_CTRL = 0xc04a, 43 MV_PMA_21X0_PORT_CTRL_SWRST = BIT(15), 44 MV_PMA_21X0_PORT_CTRL_MACTYPE_MASK = 0x7, 45 MV_PMA_21X0_PORT_CTRL_MACTYPE_USXGMII = 0x0, 46 MV_PMA_2180_PORT_CTRL_MACTYPE_DXGMII = 0x1, 47 MV_PMA_2180_PORT_CTRL_MACTYPE_QXGMII = 0x2, 48 MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER = 0x4, 49 MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER_NO_SGMII_AN = 0x5, 50 MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH = 0x6, 51 MV_PMA_BOOT = 0xc050, 52 MV_PMA_BOOT_FATAL = BIT(0), 53 54 MV_PCS_BASE_T = 0x0000, 55 MV_PCS_BASE_R = 0x1000, 56 MV_PCS_1000BASEX = 0x2000, 57 58 MV_PCS_CSCR1 = 0x8000, 59 MV_PCS_CSCR1_ED_MASK = 0x0300, 60 MV_PCS_CSCR1_ED_OFF = 0x0000, 61 MV_PCS_CSCR1_ED_RX = 0x0200, 62 MV_PCS_CSCR1_ED_NLP = 0x0300, 63 MV_PCS_CSCR1_MDIX_MASK = 0x0060, 64 MV_PCS_CSCR1_MDIX_MDI = 0x0000, 65 MV_PCS_CSCR1_MDIX_MDIX = 0x0020, 66 MV_PCS_CSCR1_MDIX_AUTO = 0x0060, 67 68 MV_PCS_DSC1 = 0x8003, 69 MV_PCS_DSC1_ENABLE = BIT(9), 70 MV_PCS_DSC1_10GBT = 0x01c0, 71 MV_PCS_DSC1_1GBR = 0x0038, 72 MV_PCS_DSC1_100BTX = 0x0007, 73 MV_PCS_DSC2 = 0x8004, 74 MV_PCS_DSC2_2P5G = 0xf000, 75 MV_PCS_DSC2_5G = 0x0f00, 76 77 MV_PCS_CSSR1 = 0x8008, 78 MV_PCS_CSSR1_SPD1_MASK = 0xc000, 79 MV_PCS_CSSR1_SPD1_SPD2 = 0xc000, 80 MV_PCS_CSSR1_SPD1_1000 = 0x8000, 81 MV_PCS_CSSR1_SPD1_100 = 0x4000, 82 MV_PCS_CSSR1_SPD1_10 = 0x0000, 83 MV_PCS_CSSR1_DUPLEX_FULL= BIT(13), 84 MV_PCS_CSSR1_RESOLVED = BIT(11), 85 MV_PCS_CSSR1_MDIX = BIT(6), 86 MV_PCS_CSSR1_SPD2_MASK = 0x000c, 87 MV_PCS_CSSR1_SPD2_5000 = 0x0008, 88 MV_PCS_CSSR1_SPD2_2500 = 0x0004, 89 MV_PCS_CSSR1_SPD2_10000 = 0x0000, 90 91 /* Temperature read register (88E2110 only) */ 92 MV_PCS_TEMP = 0x8042, 93 94 /* Number of ports on the device */ 95 MV_PCS_PORT_INFO = 0xd00d, 96 MV_PCS_PORT_INFO_NPORTS_MASK = 0x0380, 97 MV_PCS_PORT_INFO_NPORTS_SHIFT = 7, 98 99 /* SerDes reinitialization 88E21X0 */ 100 MV_AN_21X0_SERDES_CTRL2 = 0x800f, 101 MV_AN_21X0_SERDES_CTRL2_AUTO_INIT_DIS = BIT(13), 102 MV_AN_21X0_SERDES_CTRL2_RUN_INIT = BIT(15), 103 104 /* These registers appear at 0x800X and 0xa00X - the 0xa00X control 105 * registers appear to set themselves to the 0x800X when AN is 106 * restarted, but status registers appear readable from either. 107 */ 108 MV_AN_CTRL1000 = 0x8000, /* 1000base-T control register */ 109 MV_AN_STAT1000 = 0x8001, /* 1000base-T status register */ 110 111 /* Vendor2 MMD registers */ 112 MV_V2_PORT_CTRL = 0xf001, 113 MV_V2_PORT_CTRL_PWRDOWN = BIT(11), 114 MV_V2_33X0_PORT_CTRL_SWRST = BIT(15), 115 MV_V2_33X0_PORT_CTRL_MACTYPE_MASK = 0x7, 116 MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI = 0x0, 117 MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH = 0x1, 118 MV_V2_3340_PORT_CTRL_MACTYPE_RXAUI_NO_SGMII_AN = 0x1, 119 MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH = 0x2, 120 MV_V2_3310_PORT_CTRL_MACTYPE_XAUI = 0x3, 121 MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER = 0x4, 122 MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_NO_SGMII_AN = 0x5, 123 MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH = 0x6, 124 MV_V2_33X0_PORT_CTRL_MACTYPE_USXGMII = 0x7, 125 MV_V2_PORT_INTR_STS = 0xf040, 126 MV_V2_PORT_INTR_MASK = 0xf043, 127 MV_V2_PORT_INTR_STS_WOL_EN = BIT(8), 128 MV_V2_MAGIC_PKT_WORD0 = 0xf06b, 129 MV_V2_MAGIC_PKT_WORD1 = 0xf06c, 130 MV_V2_MAGIC_PKT_WORD2 = 0xf06d, 131 /* Wake on LAN registers */ 132 MV_V2_WOL_CTRL = 0xf06e, 133 MV_V2_WOL_CTRL_CLEAR_STS = BIT(15), 134 MV_V2_WOL_CTRL_MAGIC_PKT_EN = BIT(0), 135 /* Temperature control/read registers (88X3310 only) */ 136 MV_V2_TEMP_CTRL = 0xf08a, 137 MV_V2_TEMP_CTRL_MASK = 0xc000, 138 MV_V2_TEMP_CTRL_SAMPLE = 0x0000, 139 MV_V2_TEMP_CTRL_DISABLE = 0xc000, 140 MV_V2_TEMP = 0xf08c, 141 MV_V2_TEMP_UNKNOWN = 0x9600, /* unknown function */ 142 }; 143 144 struct mv3310_chip { 145 bool (*has_downshift)(struct phy_device *phydev); 146 void (*init_supported_interfaces)(unsigned long *mask); 147 int (*get_mactype)(struct phy_device *phydev); 148 int (*set_mactype)(struct phy_device *phydev, int mactype); 149 int (*select_mactype)(unsigned long *interfaces); 150 int (*init_interface)(struct phy_device *phydev, int mactype); 151 152 #ifdef CONFIG_HWMON 153 int (*hwmon_read_temp_reg)(struct phy_device *phydev); 154 #endif 155 }; 156 157 struct mv3310_priv { 158 DECLARE_BITMAP(supported_interfaces, PHY_INTERFACE_MODE_MAX); 159 160 u32 firmware_ver; 161 bool has_downshift; 162 bool rate_match; 163 phy_interface_t const_interface; 164 165 struct device *hwmon_dev; 166 char *hwmon_name; 167 }; 168 169 static const struct mv3310_chip *to_mv3310_chip(struct phy_device *phydev) 170 { 171 return phydev->drv->driver_data; 172 } 173 174 #ifdef CONFIG_HWMON 175 static umode_t mv3310_hwmon_is_visible(const void *data, 176 enum hwmon_sensor_types type, 177 u32 attr, int channel) 178 { 179 if (type == hwmon_chip && attr == hwmon_chip_update_interval) 180 return 0444; 181 if (type == hwmon_temp && attr == hwmon_temp_input) 182 return 0444; 183 return 0; 184 } 185 186 static int mv3310_hwmon_read_temp_reg(struct phy_device *phydev) 187 { 188 return phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP); 189 } 190 191 static int mv2110_hwmon_read_temp_reg(struct phy_device *phydev) 192 { 193 return phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_TEMP); 194 } 195 196 static int mv3310_hwmon_read(struct device *dev, enum hwmon_sensor_types type, 197 u32 attr, int channel, long *value) 198 { 199 struct phy_device *phydev = dev_get_drvdata(dev); 200 const struct mv3310_chip *chip = to_mv3310_chip(phydev); 201 int temp; 202 203 if (type == hwmon_chip && attr == hwmon_chip_update_interval) { 204 *value = MSEC_PER_SEC; 205 return 0; 206 } 207 208 if (type == hwmon_temp && attr == hwmon_temp_input) { 209 temp = chip->hwmon_read_temp_reg(phydev); 210 if (temp < 0) 211 return temp; 212 213 *value = ((temp & 0xff) - 75) * 1000; 214 215 return 0; 216 } 217 218 return -EOPNOTSUPP; 219 } 220 221 static const struct hwmon_ops mv3310_hwmon_ops = { 222 .is_visible = mv3310_hwmon_is_visible, 223 .read = mv3310_hwmon_read, 224 }; 225 226 static u32 mv3310_hwmon_chip_config[] = { 227 HWMON_C_REGISTER_TZ | HWMON_C_UPDATE_INTERVAL, 228 0, 229 }; 230 231 static const struct hwmon_channel_info mv3310_hwmon_chip = { 232 .type = hwmon_chip, 233 .config = mv3310_hwmon_chip_config, 234 }; 235 236 static u32 mv3310_hwmon_temp_config[] = { 237 HWMON_T_INPUT, 238 0, 239 }; 240 241 static const struct hwmon_channel_info mv3310_hwmon_temp = { 242 .type = hwmon_temp, 243 .config = mv3310_hwmon_temp_config, 244 }; 245 246 static const struct hwmon_channel_info * const mv3310_hwmon_info[] = { 247 &mv3310_hwmon_chip, 248 &mv3310_hwmon_temp, 249 NULL, 250 }; 251 252 static const struct hwmon_chip_info mv3310_hwmon_chip_info = { 253 .ops = &mv3310_hwmon_ops, 254 .info = mv3310_hwmon_info, 255 }; 256 257 static int mv3310_hwmon_config(struct phy_device *phydev, bool enable) 258 { 259 u16 val; 260 int ret; 261 262 if (phydev->drv->phy_id != MARVELL_PHY_ID_88X3310) 263 return 0; 264 265 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP, 266 MV_V2_TEMP_UNKNOWN); 267 if (ret < 0) 268 return ret; 269 270 val = enable ? MV_V2_TEMP_CTRL_SAMPLE : MV_V2_TEMP_CTRL_DISABLE; 271 272 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP_CTRL, 273 MV_V2_TEMP_CTRL_MASK, val); 274 } 275 276 static int mv3310_hwmon_probe(struct phy_device *phydev) 277 { 278 struct device *dev = &phydev->mdio.dev; 279 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); 280 int i, j, ret; 281 282 priv->hwmon_name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL); 283 if (!priv->hwmon_name) 284 return -ENODEV; 285 286 for (i = j = 0; priv->hwmon_name[i]; i++) { 287 if (isalnum(priv->hwmon_name[i])) { 288 if (i != j) 289 priv->hwmon_name[j] = priv->hwmon_name[i]; 290 j++; 291 } 292 } 293 priv->hwmon_name[j] = '\0'; 294 295 ret = mv3310_hwmon_config(phydev, true); 296 if (ret) 297 return ret; 298 299 priv->hwmon_dev = devm_hwmon_device_register_with_info(dev, 300 priv->hwmon_name, phydev, 301 &mv3310_hwmon_chip_info, NULL); 302 303 return PTR_ERR_OR_ZERO(priv->hwmon_dev); 304 } 305 #else 306 static inline int mv3310_hwmon_config(struct phy_device *phydev, bool enable) 307 { 308 return 0; 309 } 310 311 static int mv3310_hwmon_probe(struct phy_device *phydev) 312 { 313 return 0; 314 } 315 #endif 316 317 static int mv3310_power_down(struct phy_device *phydev) 318 { 319 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, 320 MV_V2_PORT_CTRL_PWRDOWN); 321 } 322 323 static int mv3310_power_up(struct phy_device *phydev) 324 { 325 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); 326 int ret; 327 328 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, 329 MV_V2_PORT_CTRL_PWRDOWN); 330 331 /* Sometimes, the power down bit doesn't clear immediately, and 332 * a read of this register causes the bit not to clear. Delay 333 * 100us to allow the PHY to come out of power down mode before 334 * the next access. 335 */ 336 udelay(100); 337 338 if (phydev->drv->phy_id != MARVELL_PHY_ID_88X3310 || 339 priv->firmware_ver < 0x00030000) 340 return ret; 341 342 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, 343 MV_V2_33X0_PORT_CTRL_SWRST); 344 } 345 346 static int mv3310_reset(struct phy_device *phydev, u32 unit) 347 { 348 int val, err; 349 350 err = phy_modify_mmd(phydev, MDIO_MMD_PCS, unit + MDIO_CTRL1, 351 MDIO_CTRL1_RESET, MDIO_CTRL1_RESET); 352 if (err < 0) 353 return err; 354 355 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_PCS, 356 unit + MDIO_CTRL1, val, 357 !(val & MDIO_CTRL1_RESET), 358 5000, 100000, true); 359 } 360 361 static int mv3310_get_downshift(struct phy_device *phydev, u8 *ds) 362 { 363 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); 364 int val; 365 366 if (!priv->has_downshift) 367 return -EOPNOTSUPP; 368 369 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_DSC1); 370 if (val < 0) 371 return val; 372 373 if (val & MV_PCS_DSC1_ENABLE) 374 /* assume that all fields are the same */ 375 *ds = 1 + FIELD_GET(MV_PCS_DSC1_10GBT, (u16)val); 376 else 377 *ds = DOWNSHIFT_DEV_DISABLE; 378 379 return 0; 380 } 381 382 static int mv3310_set_downshift(struct phy_device *phydev, u8 ds) 383 { 384 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); 385 u16 val; 386 int err; 387 388 if (!priv->has_downshift) 389 return -EOPNOTSUPP; 390 391 if (ds == DOWNSHIFT_DEV_DISABLE) 392 return phy_clear_bits_mmd(phydev, MDIO_MMD_PCS, MV_PCS_DSC1, 393 MV_PCS_DSC1_ENABLE); 394 395 /* DOWNSHIFT_DEV_DEFAULT_COUNT is confusing. It looks like it should 396 * set the default settings for the PHY. However, it is used for 397 * "ethtool --set-phy-tunable ethN downshift on". The intention is 398 * to enable downshift at a default number of retries. The default 399 * settings for 88x3310 are for two retries with downshift disabled. 400 * So let's use two retries with downshift enabled. 401 */ 402 if (ds == DOWNSHIFT_DEV_DEFAULT_COUNT) 403 ds = 2; 404 405 if (ds > 8) 406 return -E2BIG; 407 408 ds -= 1; 409 val = FIELD_PREP(MV_PCS_DSC2_2P5G, ds); 410 val |= FIELD_PREP(MV_PCS_DSC2_5G, ds); 411 err = phy_modify_mmd(phydev, MDIO_MMD_PCS, MV_PCS_DSC2, 412 MV_PCS_DSC2_2P5G | MV_PCS_DSC2_5G, val); 413 if (err < 0) 414 return err; 415 416 val = MV_PCS_DSC1_ENABLE; 417 val |= FIELD_PREP(MV_PCS_DSC1_10GBT, ds); 418 val |= FIELD_PREP(MV_PCS_DSC1_1GBR, ds); 419 val |= FIELD_PREP(MV_PCS_DSC1_100BTX, ds); 420 421 return phy_modify_mmd(phydev, MDIO_MMD_PCS, MV_PCS_DSC1, 422 MV_PCS_DSC1_ENABLE | MV_PCS_DSC1_10GBT | 423 MV_PCS_DSC1_1GBR | MV_PCS_DSC1_100BTX, val); 424 } 425 426 static int mv3310_get_edpd(struct phy_device *phydev, u16 *edpd) 427 { 428 int val; 429 430 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1); 431 if (val < 0) 432 return val; 433 434 switch (val & MV_PCS_CSCR1_ED_MASK) { 435 case MV_PCS_CSCR1_ED_NLP: 436 *edpd = 1000; 437 break; 438 case MV_PCS_CSCR1_ED_RX: 439 *edpd = ETHTOOL_PHY_EDPD_NO_TX; 440 break; 441 default: 442 *edpd = ETHTOOL_PHY_EDPD_DISABLE; 443 break; 444 } 445 return 0; 446 } 447 448 static int mv3310_set_edpd(struct phy_device *phydev, u16 edpd) 449 { 450 u16 val; 451 int err; 452 453 switch (edpd) { 454 case 1000: 455 case ETHTOOL_PHY_EDPD_DFLT_TX_MSECS: 456 val = MV_PCS_CSCR1_ED_NLP; 457 break; 458 459 case ETHTOOL_PHY_EDPD_NO_TX: 460 val = MV_PCS_CSCR1_ED_RX; 461 break; 462 463 case ETHTOOL_PHY_EDPD_DISABLE: 464 val = MV_PCS_CSCR1_ED_OFF; 465 break; 466 467 default: 468 return -EINVAL; 469 } 470 471 err = phy_modify_mmd_changed(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1, 472 MV_PCS_CSCR1_ED_MASK, val); 473 if (err > 0) 474 err = mv3310_reset(phydev, MV_PCS_BASE_T); 475 476 return err; 477 } 478 479 static int mv3310_sfp_insert(void *upstream, const struct sfp_eeprom_id *id) 480 { 481 struct phy_device *phydev = upstream; 482 __ETHTOOL_DECLARE_LINK_MODE_MASK(support) = { 0, }; 483 DECLARE_PHY_INTERFACE_MASK(interfaces); 484 phy_interface_t iface; 485 486 sfp_parse_support(phydev->sfp_bus, id, support, interfaces); 487 iface = sfp_select_interface(phydev->sfp_bus, support); 488 489 if (iface != PHY_INTERFACE_MODE_10GBASER) { 490 dev_err(&phydev->mdio.dev, "incompatible SFP module inserted\n"); 491 return -EINVAL; 492 } 493 return 0; 494 } 495 496 static const struct sfp_upstream_ops mv3310_sfp_ops = { 497 .attach = phy_sfp_attach, 498 .detach = phy_sfp_detach, 499 .module_insert = mv3310_sfp_insert, 500 }; 501 502 static int mv3310_probe(struct phy_device *phydev) 503 { 504 const struct mv3310_chip *chip = to_mv3310_chip(phydev); 505 struct mv3310_priv *priv; 506 u32 mmd_mask = MDIO_DEVS_PMAPMD | MDIO_DEVS_AN; 507 int ret; 508 509 if (!phydev->is_c45 || 510 (phydev->c45_ids.devices_in_package & mmd_mask) != mmd_mask) 511 return -ENODEV; 512 513 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_BOOT); 514 if (ret < 0) 515 return ret; 516 517 if (ret & MV_PMA_BOOT_FATAL) { 518 dev_warn(&phydev->mdio.dev, 519 "PHY failed to boot firmware, status=%04x\n", ret); 520 return -ENODEV; 521 } 522 523 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); 524 if (!priv) 525 return -ENOMEM; 526 527 dev_set_drvdata(&phydev->mdio.dev, priv); 528 529 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_FW_VER0); 530 if (ret < 0) 531 return ret; 532 533 priv->firmware_ver = ret << 16; 534 535 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_FW_VER1); 536 if (ret < 0) 537 return ret; 538 539 priv->firmware_ver |= ret; 540 541 phydev_info(phydev, "Firmware version %u.%u.%u.%u\n", 542 priv->firmware_ver >> 24, (priv->firmware_ver >> 16) & 255, 543 (priv->firmware_ver >> 8) & 255, priv->firmware_ver & 255); 544 545 if (chip->has_downshift) 546 priv->has_downshift = chip->has_downshift(phydev); 547 548 /* Powering down the port when not in use saves about 600mW */ 549 ret = mv3310_power_down(phydev); 550 if (ret) 551 return ret; 552 553 ret = mv3310_hwmon_probe(phydev); 554 if (ret) 555 return ret; 556 557 chip->init_supported_interfaces(priv->supported_interfaces); 558 559 return phy_sfp_probe(phydev, &mv3310_sfp_ops); 560 } 561 562 static void mv3310_remove(struct phy_device *phydev) 563 { 564 mv3310_hwmon_config(phydev, false); 565 } 566 567 static int mv3310_suspend(struct phy_device *phydev) 568 { 569 return mv3310_power_down(phydev); 570 } 571 572 static int mv3310_resume(struct phy_device *phydev) 573 { 574 int ret; 575 576 ret = mv3310_power_up(phydev); 577 if (ret) 578 return ret; 579 580 return mv3310_hwmon_config(phydev, true); 581 } 582 583 /* Some PHYs in the Alaska family such as the 88X3310 and the 88E2010 584 * don't set bit 14 in PMA Extended Abilities (1.11), although they do 585 * support 2.5GBASET and 5GBASET. For these models, we can still read their 586 * 2.5G/5G extended abilities register (1.21). We detect these models based on 587 * the PMA device identifier, with a mask matching models known to have this 588 * issue 589 */ 590 static bool mv3310_has_pma_ngbaset_quirk(struct phy_device *phydev) 591 { 592 if (!(phydev->c45_ids.devices_in_package & MDIO_DEVS_PMAPMD)) 593 return false; 594 595 /* Only some revisions of the 88X3310 family PMA seem to be impacted */ 596 return (phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] & 597 MV_PHY_ALASKA_NBT_QUIRK_MASK) == MV_PHY_ALASKA_NBT_QUIRK_REV; 598 } 599 600 static int mv2110_get_mactype(struct phy_device *phydev) 601 { 602 int mactype; 603 604 mactype = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_21X0_PORT_CTRL); 605 if (mactype < 0) 606 return mactype; 607 608 return mactype & MV_PMA_21X0_PORT_CTRL_MACTYPE_MASK; 609 } 610 611 static int mv2110_set_mactype(struct phy_device *phydev, int mactype) 612 { 613 int err, val; 614 615 mactype &= MV_PMA_21X0_PORT_CTRL_MACTYPE_MASK; 616 err = phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_21X0_PORT_CTRL, 617 MV_PMA_21X0_PORT_CTRL_SWRST | 618 MV_PMA_21X0_PORT_CTRL_MACTYPE_MASK, 619 MV_PMA_21X0_PORT_CTRL_SWRST | mactype); 620 if (err) 621 return err; 622 623 err = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MV_AN_21X0_SERDES_CTRL2, 624 MV_AN_21X0_SERDES_CTRL2_AUTO_INIT_DIS | 625 MV_AN_21X0_SERDES_CTRL2_RUN_INIT); 626 if (err) 627 return err; 628 629 err = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_AN, 630 MV_AN_21X0_SERDES_CTRL2, val, 631 !(val & 632 MV_AN_21X0_SERDES_CTRL2_RUN_INIT), 633 5000, 100000, true); 634 if (err) 635 return err; 636 637 return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, MV_AN_21X0_SERDES_CTRL2, 638 MV_AN_21X0_SERDES_CTRL2_AUTO_INIT_DIS); 639 } 640 641 static int mv2110_select_mactype(unsigned long *interfaces) 642 { 643 if (test_bit(PHY_INTERFACE_MODE_USXGMII, interfaces)) 644 return MV_PMA_21X0_PORT_CTRL_MACTYPE_USXGMII; 645 else if (test_bit(PHY_INTERFACE_MODE_SGMII, interfaces) && 646 !test_bit(PHY_INTERFACE_MODE_10GBASER, interfaces)) 647 return MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER; 648 else if (test_bit(PHY_INTERFACE_MODE_10GBASER, interfaces)) 649 return MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH; 650 else 651 return -1; 652 } 653 654 static int mv3310_get_mactype(struct phy_device *phydev) 655 { 656 int mactype; 657 658 mactype = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL); 659 if (mactype < 0) 660 return mactype; 661 662 return mactype & MV_V2_33X0_PORT_CTRL_MACTYPE_MASK; 663 } 664 665 static int mv3310_set_mactype(struct phy_device *phydev, int mactype) 666 { 667 int ret; 668 669 mactype &= MV_V2_33X0_PORT_CTRL_MACTYPE_MASK; 670 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, 671 MV_V2_33X0_PORT_CTRL_MACTYPE_MASK, 672 mactype); 673 if (ret <= 0) 674 return ret; 675 676 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, 677 MV_V2_33X0_PORT_CTRL_SWRST); 678 } 679 680 static int mv3310_select_mactype(unsigned long *interfaces) 681 { 682 if (test_bit(PHY_INTERFACE_MODE_USXGMII, interfaces)) 683 return MV_V2_33X0_PORT_CTRL_MACTYPE_USXGMII; 684 else if (test_bit(PHY_INTERFACE_MODE_SGMII, interfaces) && 685 test_bit(PHY_INTERFACE_MODE_10GBASER, interfaces)) 686 return MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER; 687 else if (test_bit(PHY_INTERFACE_MODE_SGMII, interfaces) && 688 test_bit(PHY_INTERFACE_MODE_RXAUI, interfaces)) 689 return MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI; 690 else if (test_bit(PHY_INTERFACE_MODE_SGMII, interfaces) && 691 test_bit(PHY_INTERFACE_MODE_XAUI, interfaces)) 692 return MV_V2_3310_PORT_CTRL_MACTYPE_XAUI; 693 else if (test_bit(PHY_INTERFACE_MODE_10GBASER, interfaces)) 694 return MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH; 695 else if (test_bit(PHY_INTERFACE_MODE_RXAUI, interfaces)) 696 return MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH; 697 else if (test_bit(PHY_INTERFACE_MODE_XAUI, interfaces)) 698 return MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH; 699 else if (test_bit(PHY_INTERFACE_MODE_SGMII, interfaces)) 700 return MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER; 701 else 702 return -1; 703 } 704 705 static int mv2110_init_interface(struct phy_device *phydev, int mactype) 706 { 707 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); 708 709 priv->rate_match = false; 710 711 if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH) 712 priv->rate_match = true; 713 714 if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_USXGMII) 715 priv->const_interface = PHY_INTERFACE_MODE_USXGMII; 716 else if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH) 717 priv->const_interface = PHY_INTERFACE_MODE_10GBASER; 718 else if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER || 719 mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER_NO_SGMII_AN) 720 priv->const_interface = PHY_INTERFACE_MODE_NA; 721 else 722 return -EINVAL; 723 724 return 0; 725 } 726 727 static int mv3310_init_interface(struct phy_device *phydev, int mactype) 728 { 729 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); 730 731 priv->rate_match = false; 732 733 if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH || 734 mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH || 735 mactype == MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH) 736 priv->rate_match = true; 737 738 if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_USXGMII) 739 priv->const_interface = PHY_INTERFACE_MODE_USXGMII; 740 else if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH || 741 mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_NO_SGMII_AN || 742 mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER) 743 priv->const_interface = PHY_INTERFACE_MODE_10GBASER; 744 else if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH || 745 mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI) 746 priv->const_interface = PHY_INTERFACE_MODE_RXAUI; 747 else if (mactype == MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH || 748 mactype == MV_V2_3310_PORT_CTRL_MACTYPE_XAUI) 749 priv->const_interface = PHY_INTERFACE_MODE_XAUI; 750 else 751 return -EINVAL; 752 753 return 0; 754 } 755 756 static int mv3340_init_interface(struct phy_device *phydev, int mactype) 757 { 758 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); 759 int err = 0; 760 761 priv->rate_match = false; 762 763 if (mactype == MV_V2_3340_PORT_CTRL_MACTYPE_RXAUI_NO_SGMII_AN) 764 priv->const_interface = PHY_INTERFACE_MODE_RXAUI; 765 else 766 err = mv3310_init_interface(phydev, mactype); 767 768 return err; 769 } 770 771 static int mv3310_config_init(struct phy_device *phydev) 772 { 773 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); 774 const struct mv3310_chip *chip = to_mv3310_chip(phydev); 775 int err, mactype; 776 777 /* Check that the PHY interface type is compatible */ 778 if (!test_bit(phydev->interface, priv->supported_interfaces)) 779 return -ENODEV; 780 781 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; 782 783 /* Power up so reset works */ 784 err = mv3310_power_up(phydev); 785 if (err) 786 return err; 787 788 /* If host provided host supported interface modes, try to select the 789 * best one 790 */ 791 if (!phy_interface_empty(phydev->host_interfaces)) { 792 mactype = chip->select_mactype(phydev->host_interfaces); 793 if (mactype >= 0) { 794 phydev_info(phydev, "Changing MACTYPE to %i\n", 795 mactype); 796 err = chip->set_mactype(phydev, mactype); 797 if (err) 798 return err; 799 } 800 } 801 802 mactype = chip->get_mactype(phydev); 803 if (mactype < 0) 804 return mactype; 805 806 err = chip->init_interface(phydev, mactype); 807 if (err) { 808 phydev_err(phydev, "MACTYPE configuration invalid\n"); 809 return err; 810 } 811 812 /* Enable EDPD mode - saving 600mW */ 813 err = mv3310_set_edpd(phydev, ETHTOOL_PHY_EDPD_DFLT_TX_MSECS); 814 if (err) 815 return err; 816 817 /* Allow downshift */ 818 err = mv3310_set_downshift(phydev, DOWNSHIFT_DEV_DEFAULT_COUNT); 819 if (err && err != -EOPNOTSUPP) 820 return err; 821 822 return 0; 823 } 824 825 static int mv3310_get_features(struct phy_device *phydev) 826 { 827 int ret, val; 828 829 ret = genphy_c45_pma_read_abilities(phydev); 830 if (ret) 831 return ret; 832 833 if (mv3310_has_pma_ngbaset_quirk(phydev)) { 834 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, 835 MDIO_PMA_NG_EXTABLE); 836 if (val < 0) 837 return val; 838 839 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 840 phydev->supported, 841 val & MDIO_PMA_NG_EXTABLE_2_5GBT); 842 843 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 844 phydev->supported, 845 val & MDIO_PMA_NG_EXTABLE_5GBT); 846 } 847 848 return 0; 849 } 850 851 static int mv3310_config_mdix(struct phy_device *phydev) 852 { 853 u16 val; 854 int err; 855 856 switch (phydev->mdix_ctrl) { 857 case ETH_TP_MDI_AUTO: 858 val = MV_PCS_CSCR1_MDIX_AUTO; 859 break; 860 case ETH_TP_MDI_X: 861 val = MV_PCS_CSCR1_MDIX_MDIX; 862 break; 863 case ETH_TP_MDI: 864 val = MV_PCS_CSCR1_MDIX_MDI; 865 break; 866 default: 867 return -EINVAL; 868 } 869 870 err = phy_modify_mmd_changed(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1, 871 MV_PCS_CSCR1_MDIX_MASK, val); 872 if (err > 0) 873 err = mv3310_reset(phydev, MV_PCS_BASE_T); 874 875 return err; 876 } 877 878 static int mv3310_config_aneg(struct phy_device *phydev) 879 { 880 bool changed = false; 881 u16 reg; 882 int ret; 883 884 ret = mv3310_config_mdix(phydev); 885 if (ret < 0) 886 return ret; 887 888 if (phydev->autoneg == AUTONEG_DISABLE) 889 return genphy_c45_pma_setup_forced(phydev); 890 891 ret = genphy_c45_an_config_aneg(phydev); 892 if (ret < 0) 893 return ret; 894 if (ret > 0) 895 changed = true; 896 897 /* Clause 45 has no standardized support for 1000BaseT, therefore 898 * use vendor registers for this mode. 899 */ 900 reg = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising); 901 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MV_AN_CTRL1000, 902 ADVERTISE_1000FULL | ADVERTISE_1000HALF, reg); 903 if (ret < 0) 904 return ret; 905 if (ret > 0) 906 changed = true; 907 908 return genphy_c45_check_and_restart_aneg(phydev, changed); 909 } 910 911 static int mv3310_aneg_done(struct phy_device *phydev) 912 { 913 int val; 914 915 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1); 916 if (val < 0) 917 return val; 918 919 if (val & MDIO_STAT1_LSTATUS) 920 return 1; 921 922 return genphy_c45_aneg_done(phydev); 923 } 924 925 static void mv3310_update_interface(struct phy_device *phydev) 926 { 927 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); 928 929 if (!phydev->link) 930 return; 931 932 /* In all of the "* with Rate Matching" modes the PHY interface is fixed 933 * at 10Gb. The PHY adapts the rate to actual wire speed with help of 934 * internal 16KB buffer. 935 * 936 * In USXGMII mode the PHY interface mode is also fixed. 937 */ 938 if (priv->rate_match || 939 priv->const_interface == PHY_INTERFACE_MODE_USXGMII) { 940 phydev->interface = priv->const_interface; 941 return; 942 } 943 944 /* The PHY automatically switches its serdes interface (and active PHYXS 945 * instance) between Cisco SGMII, 2500BaseX, 5GBase-R and 10GBase-R / 946 * xaui / rxaui modes according to the speed. 947 * Florian suggests setting phydev->interface to communicate this to the 948 * MAC. Only do this if we are already in one of the above modes. 949 */ 950 switch (phydev->speed) { 951 case SPEED_10000: 952 phydev->interface = priv->const_interface; 953 break; 954 case SPEED_5000: 955 phydev->interface = PHY_INTERFACE_MODE_5GBASER; 956 break; 957 case SPEED_2500: 958 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 959 break; 960 case SPEED_1000: 961 case SPEED_100: 962 case SPEED_10: 963 phydev->interface = PHY_INTERFACE_MODE_SGMII; 964 break; 965 default: 966 break; 967 } 968 } 969 970 /* 10GBASE-ER,LR,LRM,SR do not support autonegotiation. */ 971 static int mv3310_read_status_10gbaser(struct phy_device *phydev) 972 { 973 phydev->link = 1; 974 phydev->speed = SPEED_10000; 975 phydev->duplex = DUPLEX_FULL; 976 phydev->port = PORT_FIBRE; 977 978 return 0; 979 } 980 981 static int mv3310_read_status_copper(struct phy_device *phydev) 982 { 983 int cssr1, speed, val; 984 985 val = genphy_c45_read_link(phydev); 986 if (val < 0) 987 return val; 988 989 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); 990 if (val < 0) 991 return val; 992 993 cssr1 = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_CSSR1); 994 if (cssr1 < 0) 995 return cssr1; 996 997 /* If the link settings are not resolved, mark the link down */ 998 if (!(cssr1 & MV_PCS_CSSR1_RESOLVED)) { 999 phydev->link = 0; 1000 return 0; 1001 } 1002 1003 /* Read the copper link settings */ 1004 speed = cssr1 & MV_PCS_CSSR1_SPD1_MASK; 1005 if (speed == MV_PCS_CSSR1_SPD1_SPD2) 1006 speed |= cssr1 & MV_PCS_CSSR1_SPD2_MASK; 1007 1008 switch (speed) { 1009 case MV_PCS_CSSR1_SPD1_SPD2 | MV_PCS_CSSR1_SPD2_10000: 1010 phydev->speed = SPEED_10000; 1011 break; 1012 1013 case MV_PCS_CSSR1_SPD1_SPD2 | MV_PCS_CSSR1_SPD2_5000: 1014 phydev->speed = SPEED_5000; 1015 break; 1016 1017 case MV_PCS_CSSR1_SPD1_SPD2 | MV_PCS_CSSR1_SPD2_2500: 1018 phydev->speed = SPEED_2500; 1019 break; 1020 1021 case MV_PCS_CSSR1_SPD1_1000: 1022 phydev->speed = SPEED_1000; 1023 break; 1024 1025 case MV_PCS_CSSR1_SPD1_100: 1026 phydev->speed = SPEED_100; 1027 break; 1028 1029 case MV_PCS_CSSR1_SPD1_10: 1030 phydev->speed = SPEED_10; 1031 break; 1032 } 1033 1034 phydev->duplex = cssr1 & MV_PCS_CSSR1_DUPLEX_FULL ? 1035 DUPLEX_FULL : DUPLEX_HALF; 1036 phydev->port = PORT_TP; 1037 phydev->mdix = cssr1 & MV_PCS_CSSR1_MDIX ? 1038 ETH_TP_MDI_X : ETH_TP_MDI; 1039 1040 if (val & MDIO_AN_STAT1_COMPLETE) { 1041 val = genphy_c45_read_lpa(phydev); 1042 if (val < 0) 1043 return val; 1044 1045 /* Read the link partner's 1G advertisement */ 1046 val = phy_read_mmd(phydev, MDIO_MMD_AN, MV_AN_STAT1000); 1047 if (val < 0) 1048 return val; 1049 1050 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val); 1051 1052 /* Update the pause status */ 1053 phy_resolve_aneg_pause(phydev); 1054 } 1055 1056 return 0; 1057 } 1058 1059 static int mv3310_read_status(struct phy_device *phydev) 1060 { 1061 int err, val; 1062 1063 phydev->speed = SPEED_UNKNOWN; 1064 phydev->duplex = DUPLEX_UNKNOWN; 1065 linkmode_zero(phydev->lp_advertising); 1066 phydev->link = 0; 1067 phydev->pause = 0; 1068 phydev->asym_pause = 0; 1069 phydev->mdix = ETH_TP_MDI_INVALID; 1070 1071 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1); 1072 if (val < 0) 1073 return val; 1074 1075 if (val & MDIO_STAT1_LSTATUS) 1076 err = mv3310_read_status_10gbaser(phydev); 1077 else 1078 err = mv3310_read_status_copper(phydev); 1079 if (err < 0) 1080 return err; 1081 1082 if (phydev->link) 1083 mv3310_update_interface(phydev); 1084 1085 return 0; 1086 } 1087 1088 static int mv3310_get_tunable(struct phy_device *phydev, 1089 struct ethtool_tunable *tuna, void *data) 1090 { 1091 switch (tuna->id) { 1092 case ETHTOOL_PHY_DOWNSHIFT: 1093 return mv3310_get_downshift(phydev, data); 1094 case ETHTOOL_PHY_EDPD: 1095 return mv3310_get_edpd(phydev, data); 1096 default: 1097 return -EOPNOTSUPP; 1098 } 1099 } 1100 1101 static int mv3310_set_tunable(struct phy_device *phydev, 1102 struct ethtool_tunable *tuna, const void *data) 1103 { 1104 switch (tuna->id) { 1105 case ETHTOOL_PHY_DOWNSHIFT: 1106 return mv3310_set_downshift(phydev, *(u8 *)data); 1107 case ETHTOOL_PHY_EDPD: 1108 return mv3310_set_edpd(phydev, *(u16 *)data); 1109 default: 1110 return -EOPNOTSUPP; 1111 } 1112 } 1113 1114 static bool mv3310_has_downshift(struct phy_device *phydev) 1115 { 1116 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); 1117 1118 /* Fails to downshift with firmware older than v0.3.5.0 */ 1119 return priv->firmware_ver >= MV_VERSION(0,3,5,0); 1120 } 1121 1122 static void mv3310_init_supported_interfaces(unsigned long *mask) 1123 { 1124 __set_bit(PHY_INTERFACE_MODE_SGMII, mask); 1125 __set_bit(PHY_INTERFACE_MODE_2500BASEX, mask); 1126 __set_bit(PHY_INTERFACE_MODE_5GBASER, mask); 1127 __set_bit(PHY_INTERFACE_MODE_XAUI, mask); 1128 __set_bit(PHY_INTERFACE_MODE_RXAUI, mask); 1129 __set_bit(PHY_INTERFACE_MODE_10GBASER, mask); 1130 __set_bit(PHY_INTERFACE_MODE_USXGMII, mask); 1131 } 1132 1133 static void mv3340_init_supported_interfaces(unsigned long *mask) 1134 { 1135 __set_bit(PHY_INTERFACE_MODE_SGMII, mask); 1136 __set_bit(PHY_INTERFACE_MODE_2500BASEX, mask); 1137 __set_bit(PHY_INTERFACE_MODE_5GBASER, mask); 1138 __set_bit(PHY_INTERFACE_MODE_RXAUI, mask); 1139 __set_bit(PHY_INTERFACE_MODE_10GBASER, mask); 1140 __set_bit(PHY_INTERFACE_MODE_USXGMII, mask); 1141 } 1142 1143 static void mv2110_init_supported_interfaces(unsigned long *mask) 1144 { 1145 __set_bit(PHY_INTERFACE_MODE_SGMII, mask); 1146 __set_bit(PHY_INTERFACE_MODE_2500BASEX, mask); 1147 __set_bit(PHY_INTERFACE_MODE_5GBASER, mask); 1148 __set_bit(PHY_INTERFACE_MODE_10GBASER, mask); 1149 __set_bit(PHY_INTERFACE_MODE_USXGMII, mask); 1150 } 1151 1152 static void mv2111_init_supported_interfaces(unsigned long *mask) 1153 { 1154 __set_bit(PHY_INTERFACE_MODE_SGMII, mask); 1155 __set_bit(PHY_INTERFACE_MODE_2500BASEX, mask); 1156 __set_bit(PHY_INTERFACE_MODE_10GBASER, mask); 1157 __set_bit(PHY_INTERFACE_MODE_USXGMII, mask); 1158 } 1159 1160 static const struct mv3310_chip mv3310_type = { 1161 .has_downshift = mv3310_has_downshift, 1162 .init_supported_interfaces = mv3310_init_supported_interfaces, 1163 .get_mactype = mv3310_get_mactype, 1164 .set_mactype = mv3310_set_mactype, 1165 .select_mactype = mv3310_select_mactype, 1166 .init_interface = mv3310_init_interface, 1167 1168 #ifdef CONFIG_HWMON 1169 .hwmon_read_temp_reg = mv3310_hwmon_read_temp_reg, 1170 #endif 1171 }; 1172 1173 static const struct mv3310_chip mv3340_type = { 1174 .has_downshift = mv3310_has_downshift, 1175 .init_supported_interfaces = mv3340_init_supported_interfaces, 1176 .get_mactype = mv3310_get_mactype, 1177 .set_mactype = mv3310_set_mactype, 1178 .select_mactype = mv3310_select_mactype, 1179 .init_interface = mv3340_init_interface, 1180 1181 #ifdef CONFIG_HWMON 1182 .hwmon_read_temp_reg = mv3310_hwmon_read_temp_reg, 1183 #endif 1184 }; 1185 1186 static const struct mv3310_chip mv2110_type = { 1187 .init_supported_interfaces = mv2110_init_supported_interfaces, 1188 .get_mactype = mv2110_get_mactype, 1189 .set_mactype = mv2110_set_mactype, 1190 .select_mactype = mv2110_select_mactype, 1191 .init_interface = mv2110_init_interface, 1192 1193 #ifdef CONFIG_HWMON 1194 .hwmon_read_temp_reg = mv2110_hwmon_read_temp_reg, 1195 #endif 1196 }; 1197 1198 static const struct mv3310_chip mv2111_type = { 1199 .init_supported_interfaces = mv2111_init_supported_interfaces, 1200 .get_mactype = mv2110_get_mactype, 1201 .set_mactype = mv2110_set_mactype, 1202 .select_mactype = mv2110_select_mactype, 1203 .init_interface = mv2110_init_interface, 1204 1205 #ifdef CONFIG_HWMON 1206 .hwmon_read_temp_reg = mv2110_hwmon_read_temp_reg, 1207 #endif 1208 }; 1209 1210 static int mv3310_get_number_of_ports(struct phy_device *phydev) 1211 { 1212 int ret; 1213 1214 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_PORT_INFO); 1215 if (ret < 0) 1216 return ret; 1217 1218 ret &= MV_PCS_PORT_INFO_NPORTS_MASK; 1219 ret >>= MV_PCS_PORT_INFO_NPORTS_SHIFT; 1220 1221 return ret + 1; 1222 } 1223 1224 static int mv3310_match_phy_device(struct phy_device *phydev) 1225 { 1226 if ((phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] & 1227 MARVELL_PHY_ID_MASK) != MARVELL_PHY_ID_88X3310) 1228 return 0; 1229 1230 return mv3310_get_number_of_ports(phydev) == 1; 1231 } 1232 1233 static int mv3340_match_phy_device(struct phy_device *phydev) 1234 { 1235 if ((phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] & 1236 MARVELL_PHY_ID_MASK) != MARVELL_PHY_ID_88X3310) 1237 return 0; 1238 1239 return mv3310_get_number_of_ports(phydev) == 4; 1240 } 1241 1242 static int mv211x_match_phy_device(struct phy_device *phydev, bool has_5g) 1243 { 1244 int val; 1245 1246 if ((phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] & 1247 MARVELL_PHY_ID_MASK) != MARVELL_PHY_ID_88E2110) 1248 return 0; 1249 1250 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_SPEED); 1251 if (val < 0) 1252 return val; 1253 1254 return !!(val & MDIO_PCS_SPEED_5G) == has_5g; 1255 } 1256 1257 static int mv2110_match_phy_device(struct phy_device *phydev) 1258 { 1259 return mv211x_match_phy_device(phydev, true); 1260 } 1261 1262 static int mv2111_match_phy_device(struct phy_device *phydev) 1263 { 1264 return mv211x_match_phy_device(phydev, false); 1265 } 1266 1267 static void mv3110_get_wol(struct phy_device *phydev, 1268 struct ethtool_wolinfo *wol) 1269 { 1270 int ret; 1271 1272 wol->supported = WAKE_MAGIC; 1273 wol->wolopts = 0; 1274 1275 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_WOL_CTRL); 1276 if (ret < 0) 1277 return; 1278 1279 if (ret & MV_V2_WOL_CTRL_MAGIC_PKT_EN) 1280 wol->wolopts |= WAKE_MAGIC; 1281 } 1282 1283 static int mv3110_set_wol(struct phy_device *phydev, 1284 struct ethtool_wolinfo *wol) 1285 { 1286 int ret; 1287 1288 if (wol->wolopts & WAKE_MAGIC) { 1289 /* Enable the WOL interrupt */ 1290 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, 1291 MV_V2_PORT_INTR_MASK, 1292 MV_V2_PORT_INTR_STS_WOL_EN); 1293 if (ret < 0) 1294 return ret; 1295 1296 /* Store the device address for the magic packet */ 1297 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, 1298 MV_V2_MAGIC_PKT_WORD2, 1299 ((phydev->attached_dev->dev_addr[5] << 8) | 1300 phydev->attached_dev->dev_addr[4])); 1301 if (ret < 0) 1302 return ret; 1303 1304 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, 1305 MV_V2_MAGIC_PKT_WORD1, 1306 ((phydev->attached_dev->dev_addr[3] << 8) | 1307 phydev->attached_dev->dev_addr[2])); 1308 if (ret < 0) 1309 return ret; 1310 1311 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, 1312 MV_V2_MAGIC_PKT_WORD0, 1313 ((phydev->attached_dev->dev_addr[1] << 8) | 1314 phydev->attached_dev->dev_addr[0])); 1315 if (ret < 0) 1316 return ret; 1317 1318 /* Clear WOL status and enable magic packet matching */ 1319 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, 1320 MV_V2_WOL_CTRL, 1321 MV_V2_WOL_CTRL_MAGIC_PKT_EN | 1322 MV_V2_WOL_CTRL_CLEAR_STS); 1323 if (ret < 0) 1324 return ret; 1325 } else { 1326 /* Disable magic packet matching & reset WOL status bit */ 1327 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, 1328 MV_V2_WOL_CTRL, 1329 MV_V2_WOL_CTRL_MAGIC_PKT_EN, 1330 MV_V2_WOL_CTRL_CLEAR_STS); 1331 if (ret < 0) 1332 return ret; 1333 } 1334 1335 /* Reset the clear WOL status bit as it does not self-clear */ 1336 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, 1337 MV_V2_WOL_CTRL, 1338 MV_V2_WOL_CTRL_CLEAR_STS); 1339 } 1340 1341 static struct phy_driver mv3310_drivers[] = { 1342 { 1343 .phy_id = MARVELL_PHY_ID_88X3310, 1344 .phy_id_mask = MARVELL_PHY_ID_MASK, 1345 .match_phy_device = mv3310_match_phy_device, 1346 .name = "mv88x3310", 1347 .driver_data = &mv3310_type, 1348 .get_features = mv3310_get_features, 1349 .config_init = mv3310_config_init, 1350 .probe = mv3310_probe, 1351 .suspend = mv3310_suspend, 1352 .resume = mv3310_resume, 1353 .config_aneg = mv3310_config_aneg, 1354 .aneg_done = mv3310_aneg_done, 1355 .read_status = mv3310_read_status, 1356 .get_tunable = mv3310_get_tunable, 1357 .set_tunable = mv3310_set_tunable, 1358 .remove = mv3310_remove, 1359 .set_loopback = genphy_c45_loopback, 1360 .get_wol = mv3110_get_wol, 1361 .set_wol = mv3110_set_wol, 1362 }, 1363 { 1364 .phy_id = MARVELL_PHY_ID_88X3310, 1365 .phy_id_mask = MARVELL_PHY_ID_MASK, 1366 .match_phy_device = mv3340_match_phy_device, 1367 .name = "mv88x3340", 1368 .driver_data = &mv3340_type, 1369 .get_features = mv3310_get_features, 1370 .config_init = mv3310_config_init, 1371 .probe = mv3310_probe, 1372 .suspend = mv3310_suspend, 1373 .resume = mv3310_resume, 1374 .config_aneg = mv3310_config_aneg, 1375 .aneg_done = mv3310_aneg_done, 1376 .read_status = mv3310_read_status, 1377 .get_tunable = mv3310_get_tunable, 1378 .set_tunable = mv3310_set_tunable, 1379 .remove = mv3310_remove, 1380 .set_loopback = genphy_c45_loopback, 1381 }, 1382 { 1383 .phy_id = MARVELL_PHY_ID_88E2110, 1384 .phy_id_mask = MARVELL_PHY_ID_MASK, 1385 .match_phy_device = mv2110_match_phy_device, 1386 .name = "mv88e2110", 1387 .driver_data = &mv2110_type, 1388 .probe = mv3310_probe, 1389 .suspend = mv3310_suspend, 1390 .resume = mv3310_resume, 1391 .config_init = mv3310_config_init, 1392 .config_aneg = mv3310_config_aneg, 1393 .aneg_done = mv3310_aneg_done, 1394 .read_status = mv3310_read_status, 1395 .get_tunable = mv3310_get_tunable, 1396 .set_tunable = mv3310_set_tunable, 1397 .remove = mv3310_remove, 1398 .set_loopback = genphy_c45_loopback, 1399 .get_wol = mv3110_get_wol, 1400 .set_wol = mv3110_set_wol, 1401 }, 1402 { 1403 .phy_id = MARVELL_PHY_ID_88E2110, 1404 .phy_id_mask = MARVELL_PHY_ID_MASK, 1405 .match_phy_device = mv2111_match_phy_device, 1406 .name = "mv88e2111", 1407 .driver_data = &mv2111_type, 1408 .probe = mv3310_probe, 1409 .suspend = mv3310_suspend, 1410 .resume = mv3310_resume, 1411 .config_init = mv3310_config_init, 1412 .config_aneg = mv3310_config_aneg, 1413 .aneg_done = mv3310_aneg_done, 1414 .read_status = mv3310_read_status, 1415 .get_tunable = mv3310_get_tunable, 1416 .set_tunable = mv3310_set_tunable, 1417 .remove = mv3310_remove, 1418 .set_loopback = genphy_c45_loopback, 1419 }, 1420 }; 1421 1422 module_phy_driver(mv3310_drivers); 1423 1424 static struct mdio_device_id __maybe_unused mv3310_tbl[] = { 1425 { MARVELL_PHY_ID_88X3310, MARVELL_PHY_ID_MASK }, 1426 { MARVELL_PHY_ID_88E2110, MARVELL_PHY_ID_MASK }, 1427 { }, 1428 }; 1429 MODULE_DEVICE_TABLE(mdio, mv3310_tbl); 1430 MODULE_DESCRIPTION("Marvell Alaska X/M multi-gigabit Ethernet PHY driver"); 1431 MODULE_LICENSE("GPL"); 1432