1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Marvell 10G 88x3310 PHY driver 4 * 5 * Based upon the ID registers, this PHY appears to be a mixture of IPs 6 * from two different companies. 7 * 8 * There appears to be several different data paths through the PHY which 9 * are automatically managed by the PHY. The following has been determined 10 * via observation and experimentation for a setup using single-lane Serdes: 11 * 12 * SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G) 13 * 10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G) 14 * 10GBASE-KR PHYXS -- BASE-R PCS -- Fiber 15 * 16 * With XAUI, observation shows: 17 * 18 * XAUI PHYXS -- <appropriate PCS as above> 19 * 20 * and no switching of the host interface mode occurs. 21 * 22 * If both the fiber and copper ports are connected, the first to gain 23 * link takes priority and the other port is completely locked out. 24 */ 25 #include <linux/ctype.h> 26 #include <linux/delay.h> 27 #include <linux/hwmon.h> 28 #include <linux/marvell_phy.h> 29 #include <linux/phy.h> 30 #include <linux/sfp.h> 31 32 #define MV_PHY_ALASKA_NBT_QUIRK_MASK 0xfffffffe 33 #define MV_PHY_ALASKA_NBT_QUIRK_REV (MARVELL_PHY_ID_88X3310 | 0xa) 34 35 enum { 36 MV_PMA_FW_VER0 = 0xc011, 37 MV_PMA_FW_VER1 = 0xc012, 38 MV_PMA_BOOT = 0xc050, 39 MV_PMA_BOOT_FATAL = BIT(0), 40 41 MV_PCS_BASE_T = 0x0000, 42 MV_PCS_BASE_R = 0x1000, 43 MV_PCS_1000BASEX = 0x2000, 44 45 MV_PCS_CSCR1 = 0x8000, 46 MV_PCS_CSCR1_ED_MASK = 0x0300, 47 MV_PCS_CSCR1_ED_OFF = 0x0000, 48 MV_PCS_CSCR1_ED_RX = 0x0200, 49 MV_PCS_CSCR1_ED_NLP = 0x0300, 50 MV_PCS_CSCR1_MDIX_MASK = 0x0060, 51 MV_PCS_CSCR1_MDIX_MDI = 0x0000, 52 MV_PCS_CSCR1_MDIX_MDIX = 0x0020, 53 MV_PCS_CSCR1_MDIX_AUTO = 0x0060, 54 55 MV_PCS_CSSR1 = 0x8008, 56 MV_PCS_CSSR1_SPD1_MASK = 0xc000, 57 MV_PCS_CSSR1_SPD1_SPD2 = 0xc000, 58 MV_PCS_CSSR1_SPD1_1000 = 0x8000, 59 MV_PCS_CSSR1_SPD1_100 = 0x4000, 60 MV_PCS_CSSR1_SPD1_10 = 0x0000, 61 MV_PCS_CSSR1_DUPLEX_FULL= BIT(13), 62 MV_PCS_CSSR1_RESOLVED = BIT(11), 63 MV_PCS_CSSR1_MDIX = BIT(6), 64 MV_PCS_CSSR1_SPD2_MASK = 0x000c, 65 MV_PCS_CSSR1_SPD2_5000 = 0x0008, 66 MV_PCS_CSSR1_SPD2_2500 = 0x0004, 67 MV_PCS_CSSR1_SPD2_10000 = 0x0000, 68 69 /* These registers appear at 0x800X and 0xa00X - the 0xa00X control 70 * registers appear to set themselves to the 0x800X when AN is 71 * restarted, but status registers appear readable from either. 72 */ 73 MV_AN_CTRL1000 = 0x8000, /* 1000base-T control register */ 74 MV_AN_STAT1000 = 0x8001, /* 1000base-T status register */ 75 76 /* Vendor2 MMD registers */ 77 MV_V2_PORT_CTRL = 0xf001, 78 MV_V2_PORT_CTRL_SWRST = BIT(15), 79 MV_V2_PORT_CTRL_PWRDOWN = BIT(11), 80 MV_V2_TEMP_CTRL = 0xf08a, 81 MV_V2_TEMP_CTRL_MASK = 0xc000, 82 MV_V2_TEMP_CTRL_SAMPLE = 0x0000, 83 MV_V2_TEMP_CTRL_DISABLE = 0xc000, 84 MV_V2_TEMP = 0xf08c, 85 MV_V2_TEMP_UNKNOWN = 0x9600, /* unknown function */ 86 }; 87 88 struct mv3310_priv { 89 u32 firmware_ver; 90 91 struct device *hwmon_dev; 92 char *hwmon_name; 93 }; 94 95 #ifdef CONFIG_HWMON 96 static umode_t mv3310_hwmon_is_visible(const void *data, 97 enum hwmon_sensor_types type, 98 u32 attr, int channel) 99 { 100 if (type == hwmon_chip && attr == hwmon_chip_update_interval) 101 return 0444; 102 if (type == hwmon_temp && attr == hwmon_temp_input) 103 return 0444; 104 return 0; 105 } 106 107 static int mv3310_hwmon_read(struct device *dev, enum hwmon_sensor_types type, 108 u32 attr, int channel, long *value) 109 { 110 struct phy_device *phydev = dev_get_drvdata(dev); 111 int temp; 112 113 if (type == hwmon_chip && attr == hwmon_chip_update_interval) { 114 *value = MSEC_PER_SEC; 115 return 0; 116 } 117 118 if (type == hwmon_temp && attr == hwmon_temp_input) { 119 temp = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP); 120 if (temp < 0) 121 return temp; 122 123 *value = ((temp & 0xff) - 75) * 1000; 124 125 return 0; 126 } 127 128 return -EOPNOTSUPP; 129 } 130 131 static const struct hwmon_ops mv3310_hwmon_ops = { 132 .is_visible = mv3310_hwmon_is_visible, 133 .read = mv3310_hwmon_read, 134 }; 135 136 static u32 mv3310_hwmon_chip_config[] = { 137 HWMON_C_REGISTER_TZ | HWMON_C_UPDATE_INTERVAL, 138 0, 139 }; 140 141 static const struct hwmon_channel_info mv3310_hwmon_chip = { 142 .type = hwmon_chip, 143 .config = mv3310_hwmon_chip_config, 144 }; 145 146 static u32 mv3310_hwmon_temp_config[] = { 147 HWMON_T_INPUT, 148 0, 149 }; 150 151 static const struct hwmon_channel_info mv3310_hwmon_temp = { 152 .type = hwmon_temp, 153 .config = mv3310_hwmon_temp_config, 154 }; 155 156 static const struct hwmon_channel_info *mv3310_hwmon_info[] = { 157 &mv3310_hwmon_chip, 158 &mv3310_hwmon_temp, 159 NULL, 160 }; 161 162 static const struct hwmon_chip_info mv3310_hwmon_chip_info = { 163 .ops = &mv3310_hwmon_ops, 164 .info = mv3310_hwmon_info, 165 }; 166 167 static int mv3310_hwmon_config(struct phy_device *phydev, bool enable) 168 { 169 u16 val; 170 int ret; 171 172 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP, 173 MV_V2_TEMP_UNKNOWN); 174 if (ret < 0) 175 return ret; 176 177 val = enable ? MV_V2_TEMP_CTRL_SAMPLE : MV_V2_TEMP_CTRL_DISABLE; 178 179 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP_CTRL, 180 MV_V2_TEMP_CTRL_MASK, val); 181 } 182 183 static void mv3310_hwmon_disable(void *data) 184 { 185 struct phy_device *phydev = data; 186 187 mv3310_hwmon_config(phydev, false); 188 } 189 190 static int mv3310_hwmon_probe(struct phy_device *phydev) 191 { 192 struct device *dev = &phydev->mdio.dev; 193 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); 194 int i, j, ret; 195 196 priv->hwmon_name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL); 197 if (!priv->hwmon_name) 198 return -ENODEV; 199 200 for (i = j = 0; priv->hwmon_name[i]; i++) { 201 if (isalnum(priv->hwmon_name[i])) { 202 if (i != j) 203 priv->hwmon_name[j] = priv->hwmon_name[i]; 204 j++; 205 } 206 } 207 priv->hwmon_name[j] = '\0'; 208 209 ret = mv3310_hwmon_config(phydev, true); 210 if (ret) 211 return ret; 212 213 ret = devm_add_action_or_reset(dev, mv3310_hwmon_disable, phydev); 214 if (ret) 215 return ret; 216 217 priv->hwmon_dev = devm_hwmon_device_register_with_info(dev, 218 priv->hwmon_name, phydev, 219 &mv3310_hwmon_chip_info, NULL); 220 221 return PTR_ERR_OR_ZERO(priv->hwmon_dev); 222 } 223 #else 224 static inline int mv3310_hwmon_config(struct phy_device *phydev, bool enable) 225 { 226 return 0; 227 } 228 229 static int mv3310_hwmon_probe(struct phy_device *phydev) 230 { 231 return 0; 232 } 233 #endif 234 235 static int mv3310_power_down(struct phy_device *phydev) 236 { 237 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, 238 MV_V2_PORT_CTRL_PWRDOWN); 239 } 240 241 static int mv3310_power_up(struct phy_device *phydev) 242 { 243 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); 244 int ret; 245 246 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, 247 MV_V2_PORT_CTRL_PWRDOWN); 248 249 if (priv->firmware_ver < 0x00030000) 250 return ret; 251 252 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, 253 MV_V2_PORT_CTRL_SWRST); 254 } 255 256 static int mv3310_reset(struct phy_device *phydev, u32 unit) 257 { 258 int val, err; 259 260 err = phy_modify_mmd(phydev, MDIO_MMD_PCS, unit + MDIO_CTRL1, 261 MDIO_CTRL1_RESET, MDIO_CTRL1_RESET); 262 if (err < 0) 263 return err; 264 265 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_PCS, 266 unit + MDIO_CTRL1, val, 267 !(val & MDIO_CTRL1_RESET), 268 5000, 100000, true); 269 } 270 271 static int mv3310_get_edpd(struct phy_device *phydev, u16 *edpd) 272 { 273 int val; 274 275 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1); 276 if (val < 0) 277 return val; 278 279 switch (val & MV_PCS_CSCR1_ED_MASK) { 280 case MV_PCS_CSCR1_ED_NLP: 281 *edpd = 1000; 282 break; 283 case MV_PCS_CSCR1_ED_RX: 284 *edpd = ETHTOOL_PHY_EDPD_NO_TX; 285 break; 286 default: 287 *edpd = ETHTOOL_PHY_EDPD_DISABLE; 288 break; 289 } 290 return 0; 291 } 292 293 static int mv3310_set_edpd(struct phy_device *phydev, u16 edpd) 294 { 295 u16 val; 296 int err; 297 298 switch (edpd) { 299 case 1000: 300 case ETHTOOL_PHY_EDPD_DFLT_TX_MSECS: 301 val = MV_PCS_CSCR1_ED_NLP; 302 break; 303 304 case ETHTOOL_PHY_EDPD_NO_TX: 305 val = MV_PCS_CSCR1_ED_RX; 306 break; 307 308 case ETHTOOL_PHY_EDPD_DISABLE: 309 val = MV_PCS_CSCR1_ED_OFF; 310 break; 311 312 default: 313 return -EINVAL; 314 } 315 316 err = phy_modify_mmd_changed(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1, 317 MV_PCS_CSCR1_ED_MASK, val); 318 if (err > 0) 319 err = mv3310_reset(phydev, MV_PCS_BASE_T); 320 321 return err; 322 } 323 324 static int mv3310_sfp_insert(void *upstream, const struct sfp_eeprom_id *id) 325 { 326 struct phy_device *phydev = upstream; 327 __ETHTOOL_DECLARE_LINK_MODE_MASK(support) = { 0, }; 328 phy_interface_t iface; 329 330 sfp_parse_support(phydev->sfp_bus, id, support); 331 iface = sfp_select_interface(phydev->sfp_bus, support); 332 333 if (iface != PHY_INTERFACE_MODE_10GBASER) { 334 dev_err(&phydev->mdio.dev, "incompatible SFP module inserted\n"); 335 return -EINVAL; 336 } 337 return 0; 338 } 339 340 static const struct sfp_upstream_ops mv3310_sfp_ops = { 341 .attach = phy_sfp_attach, 342 .detach = phy_sfp_detach, 343 .module_insert = mv3310_sfp_insert, 344 }; 345 346 static int mv3310_probe(struct phy_device *phydev) 347 { 348 struct mv3310_priv *priv; 349 u32 mmd_mask = MDIO_DEVS_PMAPMD | MDIO_DEVS_AN; 350 int ret; 351 352 if (!phydev->is_c45 || 353 (phydev->c45_ids.devices_in_package & mmd_mask) != mmd_mask) 354 return -ENODEV; 355 356 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_BOOT); 357 if (ret < 0) 358 return ret; 359 360 if (ret & MV_PMA_BOOT_FATAL) { 361 dev_warn(&phydev->mdio.dev, 362 "PHY failed to boot firmware, status=%04x\n", ret); 363 return -ENODEV; 364 } 365 366 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); 367 if (!priv) 368 return -ENOMEM; 369 370 dev_set_drvdata(&phydev->mdio.dev, priv); 371 372 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_FW_VER0); 373 if (ret < 0) 374 return ret; 375 376 priv->firmware_ver = ret << 16; 377 378 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_FW_VER1); 379 if (ret < 0) 380 return ret; 381 382 priv->firmware_ver |= ret; 383 384 phydev_info(phydev, "Firmware version %u.%u.%u.%u\n", 385 priv->firmware_ver >> 24, (priv->firmware_ver >> 16) & 255, 386 (priv->firmware_ver >> 8) & 255, priv->firmware_ver & 255); 387 388 /* Powering down the port when not in use saves about 600mW */ 389 ret = mv3310_power_down(phydev); 390 if (ret) 391 return ret; 392 393 ret = mv3310_hwmon_probe(phydev); 394 if (ret) 395 return ret; 396 397 return phy_sfp_probe(phydev, &mv3310_sfp_ops); 398 } 399 400 static int mv3310_suspend(struct phy_device *phydev) 401 { 402 return mv3310_power_down(phydev); 403 } 404 405 static int mv3310_resume(struct phy_device *phydev) 406 { 407 int ret; 408 409 ret = mv3310_power_up(phydev); 410 if (ret) 411 return ret; 412 413 return mv3310_hwmon_config(phydev, true); 414 } 415 416 /* Some PHYs in the Alaska family such as the 88X3310 and the 88E2010 417 * don't set bit 14 in PMA Extended Abilities (1.11), although they do 418 * support 2.5GBASET and 5GBASET. For these models, we can still read their 419 * 2.5G/5G extended abilities register (1.21). We detect these models based on 420 * the PMA device identifier, with a mask matching models known to have this 421 * issue 422 */ 423 static bool mv3310_has_pma_ngbaset_quirk(struct phy_device *phydev) 424 { 425 if (!(phydev->c45_ids.devices_in_package & MDIO_DEVS_PMAPMD)) 426 return false; 427 428 /* Only some revisions of the 88X3310 family PMA seem to be impacted */ 429 return (phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] & 430 MV_PHY_ALASKA_NBT_QUIRK_MASK) == MV_PHY_ALASKA_NBT_QUIRK_REV; 431 } 432 433 static int mv3310_config_init(struct phy_device *phydev) 434 { 435 int err; 436 437 /* Check that the PHY interface type is compatible */ 438 if (phydev->interface != PHY_INTERFACE_MODE_SGMII && 439 phydev->interface != PHY_INTERFACE_MODE_2500BASEX && 440 phydev->interface != PHY_INTERFACE_MODE_XAUI && 441 phydev->interface != PHY_INTERFACE_MODE_RXAUI && 442 phydev->interface != PHY_INTERFACE_MODE_10GBASER) 443 return -ENODEV; 444 445 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; 446 447 /* Power up so reset works */ 448 err = mv3310_power_up(phydev); 449 if (err) 450 return err; 451 452 /* Enable EDPD mode - saving 600mW */ 453 return mv3310_set_edpd(phydev, ETHTOOL_PHY_EDPD_DFLT_TX_MSECS); 454 } 455 456 static int mv3310_get_features(struct phy_device *phydev) 457 { 458 int ret, val; 459 460 ret = genphy_c45_pma_read_abilities(phydev); 461 if (ret) 462 return ret; 463 464 if (mv3310_has_pma_ngbaset_quirk(phydev)) { 465 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, 466 MDIO_PMA_NG_EXTABLE); 467 if (val < 0) 468 return val; 469 470 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 471 phydev->supported, 472 val & MDIO_PMA_NG_EXTABLE_2_5GBT); 473 474 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 475 phydev->supported, 476 val & MDIO_PMA_NG_EXTABLE_5GBT); 477 } 478 479 return 0; 480 } 481 482 static int mv3310_config_mdix(struct phy_device *phydev) 483 { 484 u16 val; 485 int err; 486 487 switch (phydev->mdix_ctrl) { 488 case ETH_TP_MDI_AUTO: 489 val = MV_PCS_CSCR1_MDIX_AUTO; 490 break; 491 case ETH_TP_MDI_X: 492 val = MV_PCS_CSCR1_MDIX_MDIX; 493 break; 494 case ETH_TP_MDI: 495 val = MV_PCS_CSCR1_MDIX_MDI; 496 break; 497 default: 498 return -EINVAL; 499 } 500 501 err = phy_modify_mmd_changed(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1, 502 MV_PCS_CSCR1_MDIX_MASK, val); 503 if (err > 0) 504 err = mv3310_reset(phydev, MV_PCS_BASE_T); 505 506 return err; 507 } 508 509 static int mv3310_config_aneg(struct phy_device *phydev) 510 { 511 bool changed = false; 512 u16 reg; 513 int ret; 514 515 ret = mv3310_config_mdix(phydev); 516 if (ret < 0) 517 return ret; 518 519 if (phydev->autoneg == AUTONEG_DISABLE) 520 return genphy_c45_pma_setup_forced(phydev); 521 522 ret = genphy_c45_an_config_aneg(phydev); 523 if (ret < 0) 524 return ret; 525 if (ret > 0) 526 changed = true; 527 528 /* Clause 45 has no standardized support for 1000BaseT, therefore 529 * use vendor registers for this mode. 530 */ 531 reg = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising); 532 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MV_AN_CTRL1000, 533 ADVERTISE_1000FULL | ADVERTISE_1000HALF, reg); 534 if (ret < 0) 535 return ret; 536 if (ret > 0) 537 changed = true; 538 539 return genphy_c45_check_and_restart_aneg(phydev, changed); 540 } 541 542 static int mv3310_aneg_done(struct phy_device *phydev) 543 { 544 int val; 545 546 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1); 547 if (val < 0) 548 return val; 549 550 if (val & MDIO_STAT1_LSTATUS) 551 return 1; 552 553 return genphy_c45_aneg_done(phydev); 554 } 555 556 static void mv3310_update_interface(struct phy_device *phydev) 557 { 558 if ((phydev->interface == PHY_INTERFACE_MODE_SGMII || 559 phydev->interface == PHY_INTERFACE_MODE_2500BASEX || 560 phydev->interface == PHY_INTERFACE_MODE_10GBASER) && 561 phydev->link) { 562 /* The PHY automatically switches its serdes interface (and 563 * active PHYXS instance) between Cisco SGMII, 10GBase-R and 564 * 2500BaseX modes according to the speed. Florian suggests 565 * setting phydev->interface to communicate this to the MAC. 566 * Only do this if we are already in one of the above modes. 567 */ 568 switch (phydev->speed) { 569 case SPEED_10000: 570 phydev->interface = PHY_INTERFACE_MODE_10GBASER; 571 break; 572 case SPEED_2500: 573 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 574 break; 575 case SPEED_1000: 576 case SPEED_100: 577 case SPEED_10: 578 phydev->interface = PHY_INTERFACE_MODE_SGMII; 579 break; 580 default: 581 break; 582 } 583 } 584 } 585 586 /* 10GBASE-ER,LR,LRM,SR do not support autonegotiation. */ 587 static int mv3310_read_status_10gbaser(struct phy_device *phydev) 588 { 589 phydev->link = 1; 590 phydev->speed = SPEED_10000; 591 phydev->duplex = DUPLEX_FULL; 592 593 return 0; 594 } 595 596 static int mv3310_read_status_copper(struct phy_device *phydev) 597 { 598 int cssr1, speed, val; 599 600 val = genphy_c45_read_link(phydev); 601 if (val < 0) 602 return val; 603 604 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); 605 if (val < 0) 606 return val; 607 608 cssr1 = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_CSSR1); 609 if (cssr1 < 0) 610 return val; 611 612 /* If the link settings are not resolved, mark the link down */ 613 if (!(cssr1 & MV_PCS_CSSR1_RESOLVED)) { 614 phydev->link = 0; 615 return 0; 616 } 617 618 /* Read the copper link settings */ 619 speed = cssr1 & MV_PCS_CSSR1_SPD1_MASK; 620 if (speed == MV_PCS_CSSR1_SPD1_SPD2) 621 speed |= cssr1 & MV_PCS_CSSR1_SPD2_MASK; 622 623 switch (speed) { 624 case MV_PCS_CSSR1_SPD1_SPD2 | MV_PCS_CSSR1_SPD2_10000: 625 phydev->speed = SPEED_10000; 626 break; 627 628 case MV_PCS_CSSR1_SPD1_SPD2 | MV_PCS_CSSR1_SPD2_5000: 629 phydev->speed = SPEED_5000; 630 break; 631 632 case MV_PCS_CSSR1_SPD1_SPD2 | MV_PCS_CSSR1_SPD2_2500: 633 phydev->speed = SPEED_2500; 634 break; 635 636 case MV_PCS_CSSR1_SPD1_1000: 637 phydev->speed = SPEED_1000; 638 break; 639 640 case MV_PCS_CSSR1_SPD1_100: 641 phydev->speed = SPEED_100; 642 break; 643 644 case MV_PCS_CSSR1_SPD1_10: 645 phydev->speed = SPEED_10; 646 break; 647 } 648 649 phydev->duplex = cssr1 & MV_PCS_CSSR1_DUPLEX_FULL ? 650 DUPLEX_FULL : DUPLEX_HALF; 651 phydev->mdix = cssr1 & MV_PCS_CSSR1_MDIX ? 652 ETH_TP_MDI_X : ETH_TP_MDI; 653 654 if (val & MDIO_AN_STAT1_COMPLETE) { 655 val = genphy_c45_read_lpa(phydev); 656 if (val < 0) 657 return val; 658 659 /* Read the link partner's 1G advertisement */ 660 val = phy_read_mmd(phydev, MDIO_MMD_AN, MV_AN_STAT1000); 661 if (val < 0) 662 return val; 663 664 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val); 665 666 /* Update the pause status */ 667 phy_resolve_aneg_pause(phydev); 668 } 669 670 return 0; 671 } 672 673 static int mv3310_read_status(struct phy_device *phydev) 674 { 675 int err, val; 676 677 phydev->speed = SPEED_UNKNOWN; 678 phydev->duplex = DUPLEX_UNKNOWN; 679 linkmode_zero(phydev->lp_advertising); 680 phydev->link = 0; 681 phydev->pause = 0; 682 phydev->asym_pause = 0; 683 phydev->mdix = ETH_TP_MDI_INVALID; 684 685 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1); 686 if (val < 0) 687 return val; 688 689 if (val & MDIO_STAT1_LSTATUS) 690 err = mv3310_read_status_10gbaser(phydev); 691 else 692 err = mv3310_read_status_copper(phydev); 693 if (err < 0) 694 return err; 695 696 if (phydev->link) 697 mv3310_update_interface(phydev); 698 699 return 0; 700 } 701 702 static int mv3310_get_tunable(struct phy_device *phydev, 703 struct ethtool_tunable *tuna, void *data) 704 { 705 switch (tuna->id) { 706 case ETHTOOL_PHY_EDPD: 707 return mv3310_get_edpd(phydev, data); 708 default: 709 return -EOPNOTSUPP; 710 } 711 } 712 713 static int mv3310_set_tunable(struct phy_device *phydev, 714 struct ethtool_tunable *tuna, const void *data) 715 { 716 switch (tuna->id) { 717 case ETHTOOL_PHY_EDPD: 718 return mv3310_set_edpd(phydev, *(u16 *)data); 719 default: 720 return -EOPNOTSUPP; 721 } 722 } 723 724 static struct phy_driver mv3310_drivers[] = { 725 { 726 .phy_id = MARVELL_PHY_ID_88X3310, 727 .phy_id_mask = MARVELL_PHY_ID_MASK, 728 .name = "mv88x3310", 729 .get_features = mv3310_get_features, 730 .soft_reset = genphy_no_soft_reset, 731 .config_init = mv3310_config_init, 732 .probe = mv3310_probe, 733 .suspend = mv3310_suspend, 734 .resume = mv3310_resume, 735 .config_aneg = mv3310_config_aneg, 736 .aneg_done = mv3310_aneg_done, 737 .read_status = mv3310_read_status, 738 .get_tunable = mv3310_get_tunable, 739 .set_tunable = mv3310_set_tunable, 740 }, 741 { 742 .phy_id = MARVELL_PHY_ID_88E2110, 743 .phy_id_mask = MARVELL_PHY_ID_MASK, 744 .name = "mv88x2110", 745 .probe = mv3310_probe, 746 .suspend = mv3310_suspend, 747 .resume = mv3310_resume, 748 .soft_reset = genphy_no_soft_reset, 749 .config_init = mv3310_config_init, 750 .config_aneg = mv3310_config_aneg, 751 .aneg_done = mv3310_aneg_done, 752 .read_status = mv3310_read_status, 753 .get_tunable = mv3310_get_tunable, 754 .set_tunable = mv3310_set_tunable, 755 }, 756 }; 757 758 module_phy_driver(mv3310_drivers); 759 760 static struct mdio_device_id __maybe_unused mv3310_tbl[] = { 761 { MARVELL_PHY_ID_88X3310, MARVELL_PHY_ID_MASK }, 762 { MARVELL_PHY_ID_88E2110, MARVELL_PHY_ID_MASK }, 763 { }, 764 }; 765 MODULE_DEVICE_TABLE(mdio, mv3310_tbl); 766 MODULE_DESCRIPTION("Marvell Alaska X 10Gigabit Ethernet PHY driver (MV88X3310)"); 767 MODULE_LICENSE("GPL"); 768