1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Marvell 10G 88x3310 PHY driver 4 * 5 * Based upon the ID registers, this PHY appears to be a mixture of IPs 6 * from two different companies. 7 * 8 * There appears to be several different data paths through the PHY which 9 * are automatically managed by the PHY. The following has been determined 10 * via observation and experimentation for a setup using single-lane Serdes: 11 * 12 * SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G) 13 * 10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G) 14 * 10GBASE-KR PHYXS -- BASE-R PCS -- Fiber 15 * 16 * With XAUI, observation shows: 17 * 18 * XAUI PHYXS -- <appropriate PCS as above> 19 * 20 * and no switching of the host interface mode occurs. 21 * 22 * If both the fiber and copper ports are connected, the first to gain 23 * link takes priority and the other port is completely locked out. 24 */ 25 #include <linux/ctype.h> 26 #include <linux/hwmon.h> 27 #include <linux/marvell_phy.h> 28 #include <linux/phy.h> 29 #include <linux/sfp.h> 30 31 #define MV_PHY_ALASKA_NBT_QUIRK_MASK 0xfffffffe 32 #define MV_PHY_ALASKA_NBT_QUIRK_REV (MARVELL_PHY_ID_88X3310 | 0xa) 33 34 enum { 35 MV_PMA_BOOT = 0xc050, 36 MV_PMA_BOOT_FATAL = BIT(0), 37 38 MV_PCS_BASE_T = 0x0000, 39 MV_PCS_BASE_R = 0x1000, 40 MV_PCS_1000BASEX = 0x2000, 41 42 MV_PCS_PAIRSWAP = 0x8182, 43 MV_PCS_PAIRSWAP_MASK = 0x0003, 44 MV_PCS_PAIRSWAP_AB = 0x0002, 45 MV_PCS_PAIRSWAP_NONE = 0x0003, 46 47 /* These registers appear at 0x800X and 0xa00X - the 0xa00X control 48 * registers appear to set themselves to the 0x800X when AN is 49 * restarted, but status registers appear readable from either. 50 */ 51 MV_AN_CTRL1000 = 0x8000, /* 1000base-T control register */ 52 MV_AN_STAT1000 = 0x8001, /* 1000base-T status register */ 53 54 /* Vendor2 MMD registers */ 55 MV_V2_PORT_CTRL = 0xf001, 56 MV_V2_PORT_CTRL_PWRDOWN = 0x0800, 57 MV_V2_TEMP_CTRL = 0xf08a, 58 MV_V2_TEMP_CTRL_MASK = 0xc000, 59 MV_V2_TEMP_CTRL_SAMPLE = 0x0000, 60 MV_V2_TEMP_CTRL_DISABLE = 0xc000, 61 MV_V2_TEMP = 0xf08c, 62 MV_V2_TEMP_UNKNOWN = 0x9600, /* unknown function */ 63 }; 64 65 struct mv3310_priv { 66 struct device *hwmon_dev; 67 char *hwmon_name; 68 }; 69 70 #ifdef CONFIG_HWMON 71 static umode_t mv3310_hwmon_is_visible(const void *data, 72 enum hwmon_sensor_types type, 73 u32 attr, int channel) 74 { 75 if (type == hwmon_chip && attr == hwmon_chip_update_interval) 76 return 0444; 77 if (type == hwmon_temp && attr == hwmon_temp_input) 78 return 0444; 79 return 0; 80 } 81 82 static int mv3310_hwmon_read(struct device *dev, enum hwmon_sensor_types type, 83 u32 attr, int channel, long *value) 84 { 85 struct phy_device *phydev = dev_get_drvdata(dev); 86 int temp; 87 88 if (type == hwmon_chip && attr == hwmon_chip_update_interval) { 89 *value = MSEC_PER_SEC; 90 return 0; 91 } 92 93 if (type == hwmon_temp && attr == hwmon_temp_input) { 94 temp = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP); 95 if (temp < 0) 96 return temp; 97 98 *value = ((temp & 0xff) - 75) * 1000; 99 100 return 0; 101 } 102 103 return -EOPNOTSUPP; 104 } 105 106 static const struct hwmon_ops mv3310_hwmon_ops = { 107 .is_visible = mv3310_hwmon_is_visible, 108 .read = mv3310_hwmon_read, 109 }; 110 111 static u32 mv3310_hwmon_chip_config[] = { 112 HWMON_C_REGISTER_TZ | HWMON_C_UPDATE_INTERVAL, 113 0, 114 }; 115 116 static const struct hwmon_channel_info mv3310_hwmon_chip = { 117 .type = hwmon_chip, 118 .config = mv3310_hwmon_chip_config, 119 }; 120 121 static u32 mv3310_hwmon_temp_config[] = { 122 HWMON_T_INPUT, 123 0, 124 }; 125 126 static const struct hwmon_channel_info mv3310_hwmon_temp = { 127 .type = hwmon_temp, 128 .config = mv3310_hwmon_temp_config, 129 }; 130 131 static const struct hwmon_channel_info *mv3310_hwmon_info[] = { 132 &mv3310_hwmon_chip, 133 &mv3310_hwmon_temp, 134 NULL, 135 }; 136 137 static const struct hwmon_chip_info mv3310_hwmon_chip_info = { 138 .ops = &mv3310_hwmon_ops, 139 .info = mv3310_hwmon_info, 140 }; 141 142 static int mv3310_hwmon_config(struct phy_device *phydev, bool enable) 143 { 144 u16 val; 145 int ret; 146 147 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP, 148 MV_V2_TEMP_UNKNOWN); 149 if (ret < 0) 150 return ret; 151 152 val = enable ? MV_V2_TEMP_CTRL_SAMPLE : MV_V2_TEMP_CTRL_DISABLE; 153 154 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP_CTRL, 155 MV_V2_TEMP_CTRL_MASK, val); 156 } 157 158 static void mv3310_hwmon_disable(void *data) 159 { 160 struct phy_device *phydev = data; 161 162 mv3310_hwmon_config(phydev, false); 163 } 164 165 static int mv3310_hwmon_probe(struct phy_device *phydev) 166 { 167 struct device *dev = &phydev->mdio.dev; 168 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); 169 int i, j, ret; 170 171 priv->hwmon_name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL); 172 if (!priv->hwmon_name) 173 return -ENODEV; 174 175 for (i = j = 0; priv->hwmon_name[i]; i++) { 176 if (isalnum(priv->hwmon_name[i])) { 177 if (i != j) 178 priv->hwmon_name[j] = priv->hwmon_name[i]; 179 j++; 180 } 181 } 182 priv->hwmon_name[j] = '\0'; 183 184 ret = mv3310_hwmon_config(phydev, true); 185 if (ret) 186 return ret; 187 188 ret = devm_add_action_or_reset(dev, mv3310_hwmon_disable, phydev); 189 if (ret) 190 return ret; 191 192 priv->hwmon_dev = devm_hwmon_device_register_with_info(dev, 193 priv->hwmon_name, phydev, 194 &mv3310_hwmon_chip_info, NULL); 195 196 return PTR_ERR_OR_ZERO(priv->hwmon_dev); 197 } 198 #else 199 static inline int mv3310_hwmon_config(struct phy_device *phydev, bool enable) 200 { 201 return 0; 202 } 203 204 static int mv3310_hwmon_probe(struct phy_device *phydev) 205 { 206 return 0; 207 } 208 #endif 209 210 static int mv3310_sfp_insert(void *upstream, const struct sfp_eeprom_id *id) 211 { 212 struct phy_device *phydev = upstream; 213 __ETHTOOL_DECLARE_LINK_MODE_MASK(support) = { 0, }; 214 phy_interface_t iface; 215 216 sfp_parse_support(phydev->sfp_bus, id, support); 217 iface = sfp_select_interface(phydev->sfp_bus, id, support); 218 219 if (iface != PHY_INTERFACE_MODE_10GKR) { 220 dev_err(&phydev->mdio.dev, "incompatible SFP module inserted\n"); 221 return -EINVAL; 222 } 223 return 0; 224 } 225 226 static const struct sfp_upstream_ops mv3310_sfp_ops = { 227 .attach = phy_sfp_attach, 228 .detach = phy_sfp_detach, 229 .module_insert = mv3310_sfp_insert, 230 }; 231 232 static int mv3310_probe(struct phy_device *phydev) 233 { 234 struct mv3310_priv *priv; 235 u32 mmd_mask = MDIO_DEVS_PMAPMD | MDIO_DEVS_AN; 236 int ret; 237 238 if (!phydev->is_c45 || 239 (phydev->c45_ids.devices_in_package & mmd_mask) != mmd_mask) 240 return -ENODEV; 241 242 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_BOOT); 243 if (ret < 0) 244 return ret; 245 246 if (ret & MV_PMA_BOOT_FATAL) { 247 dev_warn(&phydev->mdio.dev, 248 "PHY failed to boot firmware, status=%04x\n", ret); 249 return -ENODEV; 250 } 251 252 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); 253 if (!priv) 254 return -ENOMEM; 255 256 dev_set_drvdata(&phydev->mdio.dev, priv); 257 258 ret = mv3310_hwmon_probe(phydev); 259 if (ret) 260 return ret; 261 262 return phy_sfp_probe(phydev, &mv3310_sfp_ops); 263 } 264 265 static int mv3310_suspend(struct phy_device *phydev) 266 { 267 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, 268 MV_V2_PORT_CTRL_PWRDOWN); 269 } 270 271 static int mv3310_resume(struct phy_device *phydev) 272 { 273 int ret; 274 275 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, 276 MV_V2_PORT_CTRL_PWRDOWN); 277 if (ret) 278 return ret; 279 280 return mv3310_hwmon_config(phydev, true); 281 } 282 283 /* Some PHYs in the Alaska family such as the 88X3310 and the 88E2010 284 * don't set bit 14 in PMA Extended Abilities (1.11), although they do 285 * support 2.5GBASET and 5GBASET. For these models, we can still read their 286 * 2.5G/5G extended abilities register (1.21). We detect these models based on 287 * the PMA device identifier, with a mask matching models known to have this 288 * issue 289 */ 290 static bool mv3310_has_pma_ngbaset_quirk(struct phy_device *phydev) 291 { 292 if (!(phydev->c45_ids.devices_in_package & MDIO_DEVS_PMAPMD)) 293 return false; 294 295 /* Only some revisions of the 88X3310 family PMA seem to be impacted */ 296 return (phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] & 297 MV_PHY_ALASKA_NBT_QUIRK_MASK) == MV_PHY_ALASKA_NBT_QUIRK_REV; 298 } 299 300 static int mv3310_config_init(struct phy_device *phydev) 301 { 302 /* Check that the PHY interface type is compatible */ 303 if (phydev->interface != PHY_INTERFACE_MODE_SGMII && 304 phydev->interface != PHY_INTERFACE_MODE_2500BASEX && 305 phydev->interface != PHY_INTERFACE_MODE_XAUI && 306 phydev->interface != PHY_INTERFACE_MODE_RXAUI && 307 phydev->interface != PHY_INTERFACE_MODE_10GKR) 308 return -ENODEV; 309 310 return 0; 311 } 312 313 static int mv3310_get_features(struct phy_device *phydev) 314 { 315 int ret, val; 316 317 ret = genphy_c45_pma_read_abilities(phydev); 318 if (ret) 319 return ret; 320 321 if (mv3310_has_pma_ngbaset_quirk(phydev)) { 322 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, 323 MDIO_PMA_NG_EXTABLE); 324 if (val < 0) 325 return val; 326 327 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 328 phydev->supported, 329 val & MDIO_PMA_NG_EXTABLE_2_5GBT); 330 331 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 332 phydev->supported, 333 val & MDIO_PMA_NG_EXTABLE_5GBT); 334 } 335 336 return 0; 337 } 338 339 static int mv3310_config_aneg(struct phy_device *phydev) 340 { 341 bool changed = false; 342 u16 reg; 343 int ret; 344 345 /* We don't support manual MDI control */ 346 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; 347 348 if (phydev->autoneg == AUTONEG_DISABLE) 349 return genphy_c45_pma_setup_forced(phydev); 350 351 ret = genphy_c45_an_config_aneg(phydev); 352 if (ret < 0) 353 return ret; 354 if (ret > 0) 355 changed = true; 356 357 /* Clause 45 has no standardized support for 1000BaseT, therefore 358 * use vendor registers for this mode. 359 */ 360 reg = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising); 361 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MV_AN_CTRL1000, 362 ADVERTISE_1000FULL | ADVERTISE_1000HALF, reg); 363 if (ret < 0) 364 return ret; 365 if (ret > 0) 366 changed = true; 367 368 return genphy_c45_check_and_restart_aneg(phydev, changed); 369 } 370 371 static int mv3310_aneg_done(struct phy_device *phydev) 372 { 373 int val; 374 375 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1); 376 if (val < 0) 377 return val; 378 379 if (val & MDIO_STAT1_LSTATUS) 380 return 1; 381 382 return genphy_c45_aneg_done(phydev); 383 } 384 385 static void mv3310_update_interface(struct phy_device *phydev) 386 { 387 if ((phydev->interface == PHY_INTERFACE_MODE_SGMII || 388 phydev->interface == PHY_INTERFACE_MODE_2500BASEX || 389 phydev->interface == PHY_INTERFACE_MODE_10GKR) && phydev->link) { 390 /* The PHY automatically switches its serdes interface (and 391 * active PHYXS instance) between Cisco SGMII, 10GBase-KR and 392 * 2500BaseX modes according to the speed. Florian suggests 393 * setting phydev->interface to communicate this to the MAC. 394 * Only do this if we are already in one of the above modes. 395 */ 396 switch (phydev->speed) { 397 case SPEED_10000: 398 phydev->interface = PHY_INTERFACE_MODE_10GKR; 399 break; 400 case SPEED_2500: 401 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 402 break; 403 case SPEED_1000: 404 case SPEED_100: 405 case SPEED_10: 406 phydev->interface = PHY_INTERFACE_MODE_SGMII; 407 break; 408 default: 409 break; 410 } 411 } 412 } 413 414 /* 10GBASE-ER,LR,LRM,SR do not support autonegotiation. */ 415 static int mv3310_read_10gbr_status(struct phy_device *phydev) 416 { 417 phydev->link = 1; 418 phydev->speed = SPEED_10000; 419 phydev->duplex = DUPLEX_FULL; 420 421 mv3310_update_interface(phydev); 422 423 return 0; 424 } 425 426 static int mv3310_read_status(struct phy_device *phydev) 427 { 428 int val; 429 430 phydev->speed = SPEED_UNKNOWN; 431 phydev->duplex = DUPLEX_UNKNOWN; 432 linkmode_zero(phydev->lp_advertising); 433 phydev->link = 0; 434 phydev->pause = 0; 435 phydev->asym_pause = 0; 436 phydev->mdix = 0; 437 438 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1); 439 if (val < 0) 440 return val; 441 442 if (val & MDIO_STAT1_LSTATUS) 443 return mv3310_read_10gbr_status(phydev); 444 445 val = genphy_c45_read_link(phydev); 446 if (val < 0) 447 return val; 448 449 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); 450 if (val < 0) 451 return val; 452 453 if (val & MDIO_AN_STAT1_COMPLETE) { 454 val = genphy_c45_read_lpa(phydev); 455 if (val < 0) 456 return val; 457 458 /* Read the link partner's 1G advertisement */ 459 val = phy_read_mmd(phydev, MDIO_MMD_AN, MV_AN_STAT1000); 460 if (val < 0) 461 return val; 462 463 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val); 464 465 if (phydev->autoneg == AUTONEG_ENABLE) 466 phy_resolve_aneg_linkmode(phydev); 467 } 468 469 if (phydev->autoneg != AUTONEG_ENABLE) { 470 val = genphy_c45_read_pma(phydev); 471 if (val < 0) 472 return val; 473 } 474 475 if (phydev->speed == SPEED_10000) { 476 val = genphy_c45_read_mdix(phydev); 477 if (val < 0) 478 return val; 479 } else { 480 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_PAIRSWAP); 481 if (val < 0) 482 return val; 483 484 switch (val & MV_PCS_PAIRSWAP_MASK) { 485 case MV_PCS_PAIRSWAP_AB: 486 phydev->mdix = ETH_TP_MDI_X; 487 break; 488 case MV_PCS_PAIRSWAP_NONE: 489 phydev->mdix = ETH_TP_MDI; 490 break; 491 default: 492 phydev->mdix = ETH_TP_MDI_INVALID; 493 break; 494 } 495 } 496 497 mv3310_update_interface(phydev); 498 499 return 0; 500 } 501 502 static struct phy_driver mv3310_drivers[] = { 503 { 504 .phy_id = MARVELL_PHY_ID_88X3310, 505 .phy_id_mask = MARVELL_PHY_ID_MASK, 506 .name = "mv88x3310", 507 .get_features = mv3310_get_features, 508 .soft_reset = genphy_no_soft_reset, 509 .config_init = mv3310_config_init, 510 .probe = mv3310_probe, 511 .suspend = mv3310_suspend, 512 .resume = mv3310_resume, 513 .config_aneg = mv3310_config_aneg, 514 .aneg_done = mv3310_aneg_done, 515 .read_status = mv3310_read_status, 516 }, 517 { 518 .phy_id = MARVELL_PHY_ID_88E2110, 519 .phy_id_mask = MARVELL_PHY_ID_MASK, 520 .name = "mv88x2110", 521 .probe = mv3310_probe, 522 .suspend = mv3310_suspend, 523 .resume = mv3310_resume, 524 .soft_reset = genphy_no_soft_reset, 525 .config_init = mv3310_config_init, 526 .config_aneg = mv3310_config_aneg, 527 .aneg_done = mv3310_aneg_done, 528 .read_status = mv3310_read_status, 529 }, 530 }; 531 532 module_phy_driver(mv3310_drivers); 533 534 static struct mdio_device_id __maybe_unused mv3310_tbl[] = { 535 { MARVELL_PHY_ID_88X3310, MARVELL_PHY_ID_MASK }, 536 { MARVELL_PHY_ID_88E2110, MARVELL_PHY_ID_MASK }, 537 { }, 538 }; 539 MODULE_DEVICE_TABLE(mdio, mv3310_tbl); 540 MODULE_DESCRIPTION("Marvell Alaska X 10Gigabit Ethernet PHY driver (MV88X3310)"); 541 MODULE_LICENSE("GPL"); 542