1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Marvell 10G 88x3310 PHY driver 4 * 5 * Based upon the ID registers, this PHY appears to be a mixture of IPs 6 * from two different companies. 7 * 8 * There appears to be several different data paths through the PHY which 9 * are automatically managed by the PHY. The following has been determined 10 * via observation and experimentation for a setup using single-lane Serdes: 11 * 12 * SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G) 13 * 10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G) 14 * 10GBASE-KR PHYXS -- BASE-R PCS -- Fiber 15 * 16 * With XAUI, observation shows: 17 * 18 * XAUI PHYXS -- <appropriate PCS as above> 19 * 20 * and no switching of the host interface mode occurs. 21 * 22 * If both the fiber and copper ports are connected, the first to gain 23 * link takes priority and the other port is completely locked out. 24 */ 25 #include <linux/ctype.h> 26 #include <linux/delay.h> 27 #include <linux/hwmon.h> 28 #include <linux/marvell_phy.h> 29 #include <linux/phy.h> 30 #include <linux/sfp.h> 31 32 #define MV_PHY_ALASKA_NBT_QUIRK_MASK 0xfffffffe 33 #define MV_PHY_ALASKA_NBT_QUIRK_REV (MARVELL_PHY_ID_88X3310 | 0xa) 34 35 enum { 36 MV_PMA_FW_VER0 = 0xc011, 37 MV_PMA_FW_VER1 = 0xc012, 38 MV_PMA_BOOT = 0xc050, 39 MV_PMA_BOOT_FATAL = BIT(0), 40 41 MV_PCS_BASE_T = 0x0000, 42 MV_PCS_BASE_R = 0x1000, 43 MV_PCS_1000BASEX = 0x2000, 44 45 MV_PCS_CSCR1 = 0x8000, 46 MV_PCS_CSCR1_ED_MASK = 0x0300, 47 MV_PCS_CSCR1_ED_OFF = 0x0000, 48 MV_PCS_CSCR1_ED_RX = 0x0200, 49 MV_PCS_CSCR1_ED_NLP = 0x0300, 50 MV_PCS_CSCR1_MDIX_MASK = 0x0060, 51 MV_PCS_CSCR1_MDIX_MDI = 0x0000, 52 MV_PCS_CSCR1_MDIX_MDIX = 0x0020, 53 MV_PCS_CSCR1_MDIX_AUTO = 0x0060, 54 55 MV_PCS_CSSR1 = 0x8008, 56 MV_PCS_CSSR1_SPD1_MASK = 0xc000, 57 MV_PCS_CSSR1_SPD1_SPD2 = 0xc000, 58 MV_PCS_CSSR1_SPD1_1000 = 0x8000, 59 MV_PCS_CSSR1_SPD1_100 = 0x4000, 60 MV_PCS_CSSR1_SPD1_10 = 0x0000, 61 MV_PCS_CSSR1_DUPLEX_FULL= BIT(13), 62 MV_PCS_CSSR1_RESOLVED = BIT(11), 63 MV_PCS_CSSR1_MDIX = BIT(6), 64 MV_PCS_CSSR1_SPD2_MASK = 0x000c, 65 MV_PCS_CSSR1_SPD2_5000 = 0x0008, 66 MV_PCS_CSSR1_SPD2_2500 = 0x0004, 67 MV_PCS_CSSR1_SPD2_10000 = 0x0000, 68 69 /* Temperature read register (88E2110 only) */ 70 MV_PCS_TEMP = 0x8042, 71 72 /* These registers appear at 0x800X and 0xa00X - the 0xa00X control 73 * registers appear to set themselves to the 0x800X when AN is 74 * restarted, but status registers appear readable from either. 75 */ 76 MV_AN_CTRL1000 = 0x8000, /* 1000base-T control register */ 77 MV_AN_STAT1000 = 0x8001, /* 1000base-T status register */ 78 79 /* Vendor2 MMD registers */ 80 MV_V2_PORT_CTRL = 0xf001, 81 MV_V2_PORT_CTRL_SWRST = BIT(15), 82 MV_V2_PORT_CTRL_PWRDOWN = BIT(11), 83 MV_V2_PORT_MAC_TYPE_MASK = 0x7, 84 MV_V2_PORT_MAC_TYPE_RATE_MATCH = 0x6, 85 /* Temperature control/read registers (88X3310 only) */ 86 MV_V2_TEMP_CTRL = 0xf08a, 87 MV_V2_TEMP_CTRL_MASK = 0xc000, 88 MV_V2_TEMP_CTRL_SAMPLE = 0x0000, 89 MV_V2_TEMP_CTRL_DISABLE = 0xc000, 90 MV_V2_TEMP = 0xf08c, 91 MV_V2_TEMP_UNKNOWN = 0x9600, /* unknown function */ 92 }; 93 94 struct mv3310_priv { 95 u32 firmware_ver; 96 bool rate_match; 97 98 struct device *hwmon_dev; 99 char *hwmon_name; 100 }; 101 102 #ifdef CONFIG_HWMON 103 static umode_t mv3310_hwmon_is_visible(const void *data, 104 enum hwmon_sensor_types type, 105 u32 attr, int channel) 106 { 107 if (type == hwmon_chip && attr == hwmon_chip_update_interval) 108 return 0444; 109 if (type == hwmon_temp && attr == hwmon_temp_input) 110 return 0444; 111 return 0; 112 } 113 114 static int mv3310_hwmon_read_temp_reg(struct phy_device *phydev) 115 { 116 return phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP); 117 } 118 119 static int mv2110_hwmon_read_temp_reg(struct phy_device *phydev) 120 { 121 return phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_TEMP); 122 } 123 124 static int mv10g_hwmon_read_temp_reg(struct phy_device *phydev) 125 { 126 if (phydev->drv->phy_id == MARVELL_PHY_ID_88X3310) 127 return mv3310_hwmon_read_temp_reg(phydev); 128 else /* MARVELL_PHY_ID_88E2110 */ 129 return mv2110_hwmon_read_temp_reg(phydev); 130 } 131 132 static int mv3310_hwmon_read(struct device *dev, enum hwmon_sensor_types type, 133 u32 attr, int channel, long *value) 134 { 135 struct phy_device *phydev = dev_get_drvdata(dev); 136 int temp; 137 138 if (type == hwmon_chip && attr == hwmon_chip_update_interval) { 139 *value = MSEC_PER_SEC; 140 return 0; 141 } 142 143 if (type == hwmon_temp && attr == hwmon_temp_input) { 144 temp = mv10g_hwmon_read_temp_reg(phydev); 145 if (temp < 0) 146 return temp; 147 148 *value = ((temp & 0xff) - 75) * 1000; 149 150 return 0; 151 } 152 153 return -EOPNOTSUPP; 154 } 155 156 static const struct hwmon_ops mv3310_hwmon_ops = { 157 .is_visible = mv3310_hwmon_is_visible, 158 .read = mv3310_hwmon_read, 159 }; 160 161 static u32 mv3310_hwmon_chip_config[] = { 162 HWMON_C_REGISTER_TZ | HWMON_C_UPDATE_INTERVAL, 163 0, 164 }; 165 166 static const struct hwmon_channel_info mv3310_hwmon_chip = { 167 .type = hwmon_chip, 168 .config = mv3310_hwmon_chip_config, 169 }; 170 171 static u32 mv3310_hwmon_temp_config[] = { 172 HWMON_T_INPUT, 173 0, 174 }; 175 176 static const struct hwmon_channel_info mv3310_hwmon_temp = { 177 .type = hwmon_temp, 178 .config = mv3310_hwmon_temp_config, 179 }; 180 181 static const struct hwmon_channel_info *mv3310_hwmon_info[] = { 182 &mv3310_hwmon_chip, 183 &mv3310_hwmon_temp, 184 NULL, 185 }; 186 187 static const struct hwmon_chip_info mv3310_hwmon_chip_info = { 188 .ops = &mv3310_hwmon_ops, 189 .info = mv3310_hwmon_info, 190 }; 191 192 static int mv3310_hwmon_config(struct phy_device *phydev, bool enable) 193 { 194 u16 val; 195 int ret; 196 197 if (phydev->drv->phy_id != MARVELL_PHY_ID_88X3310) 198 return 0; 199 200 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP, 201 MV_V2_TEMP_UNKNOWN); 202 if (ret < 0) 203 return ret; 204 205 val = enable ? MV_V2_TEMP_CTRL_SAMPLE : MV_V2_TEMP_CTRL_DISABLE; 206 207 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP_CTRL, 208 MV_V2_TEMP_CTRL_MASK, val); 209 } 210 211 static void mv3310_hwmon_disable(void *data) 212 { 213 struct phy_device *phydev = data; 214 215 mv3310_hwmon_config(phydev, false); 216 } 217 218 static int mv3310_hwmon_probe(struct phy_device *phydev) 219 { 220 struct device *dev = &phydev->mdio.dev; 221 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); 222 int i, j, ret; 223 224 priv->hwmon_name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL); 225 if (!priv->hwmon_name) 226 return -ENODEV; 227 228 for (i = j = 0; priv->hwmon_name[i]; i++) { 229 if (isalnum(priv->hwmon_name[i])) { 230 if (i != j) 231 priv->hwmon_name[j] = priv->hwmon_name[i]; 232 j++; 233 } 234 } 235 priv->hwmon_name[j] = '\0'; 236 237 ret = mv3310_hwmon_config(phydev, true); 238 if (ret) 239 return ret; 240 241 ret = devm_add_action_or_reset(dev, mv3310_hwmon_disable, phydev); 242 if (ret) 243 return ret; 244 245 priv->hwmon_dev = devm_hwmon_device_register_with_info(dev, 246 priv->hwmon_name, phydev, 247 &mv3310_hwmon_chip_info, NULL); 248 249 return PTR_ERR_OR_ZERO(priv->hwmon_dev); 250 } 251 #else 252 static inline int mv3310_hwmon_config(struct phy_device *phydev, bool enable) 253 { 254 return 0; 255 } 256 257 static int mv3310_hwmon_probe(struct phy_device *phydev) 258 { 259 return 0; 260 } 261 #endif 262 263 static int mv3310_power_down(struct phy_device *phydev) 264 { 265 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, 266 MV_V2_PORT_CTRL_PWRDOWN); 267 } 268 269 static int mv3310_power_up(struct phy_device *phydev) 270 { 271 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); 272 int ret; 273 274 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, 275 MV_V2_PORT_CTRL_PWRDOWN); 276 277 if (phydev->drv->phy_id != MARVELL_PHY_ID_88X3310 || 278 priv->firmware_ver < 0x00030000) 279 return ret; 280 281 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, 282 MV_V2_PORT_CTRL_SWRST); 283 } 284 285 static int mv3310_reset(struct phy_device *phydev, u32 unit) 286 { 287 int val, err; 288 289 err = phy_modify_mmd(phydev, MDIO_MMD_PCS, unit + MDIO_CTRL1, 290 MDIO_CTRL1_RESET, MDIO_CTRL1_RESET); 291 if (err < 0) 292 return err; 293 294 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_PCS, 295 unit + MDIO_CTRL1, val, 296 !(val & MDIO_CTRL1_RESET), 297 5000, 100000, true); 298 } 299 300 static int mv3310_get_edpd(struct phy_device *phydev, u16 *edpd) 301 { 302 int val; 303 304 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1); 305 if (val < 0) 306 return val; 307 308 switch (val & MV_PCS_CSCR1_ED_MASK) { 309 case MV_PCS_CSCR1_ED_NLP: 310 *edpd = 1000; 311 break; 312 case MV_PCS_CSCR1_ED_RX: 313 *edpd = ETHTOOL_PHY_EDPD_NO_TX; 314 break; 315 default: 316 *edpd = ETHTOOL_PHY_EDPD_DISABLE; 317 break; 318 } 319 return 0; 320 } 321 322 static int mv3310_set_edpd(struct phy_device *phydev, u16 edpd) 323 { 324 u16 val; 325 int err; 326 327 switch (edpd) { 328 case 1000: 329 case ETHTOOL_PHY_EDPD_DFLT_TX_MSECS: 330 val = MV_PCS_CSCR1_ED_NLP; 331 break; 332 333 case ETHTOOL_PHY_EDPD_NO_TX: 334 val = MV_PCS_CSCR1_ED_RX; 335 break; 336 337 case ETHTOOL_PHY_EDPD_DISABLE: 338 val = MV_PCS_CSCR1_ED_OFF; 339 break; 340 341 default: 342 return -EINVAL; 343 } 344 345 err = phy_modify_mmd_changed(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1, 346 MV_PCS_CSCR1_ED_MASK, val); 347 if (err > 0) 348 err = mv3310_reset(phydev, MV_PCS_BASE_T); 349 350 return err; 351 } 352 353 static int mv3310_sfp_insert(void *upstream, const struct sfp_eeprom_id *id) 354 { 355 struct phy_device *phydev = upstream; 356 __ETHTOOL_DECLARE_LINK_MODE_MASK(support) = { 0, }; 357 phy_interface_t iface; 358 359 sfp_parse_support(phydev->sfp_bus, id, support); 360 iface = sfp_select_interface(phydev->sfp_bus, support); 361 362 if (iface != PHY_INTERFACE_MODE_10GBASER) { 363 dev_err(&phydev->mdio.dev, "incompatible SFP module inserted\n"); 364 return -EINVAL; 365 } 366 return 0; 367 } 368 369 static const struct sfp_upstream_ops mv3310_sfp_ops = { 370 .attach = phy_sfp_attach, 371 .detach = phy_sfp_detach, 372 .module_insert = mv3310_sfp_insert, 373 }; 374 375 static int mv3310_probe(struct phy_device *phydev) 376 { 377 struct mv3310_priv *priv; 378 u32 mmd_mask = MDIO_DEVS_PMAPMD | MDIO_DEVS_AN; 379 int ret; 380 381 if (!phydev->is_c45 || 382 (phydev->c45_ids.devices_in_package & mmd_mask) != mmd_mask) 383 return -ENODEV; 384 385 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_BOOT); 386 if (ret < 0) 387 return ret; 388 389 if (ret & MV_PMA_BOOT_FATAL) { 390 dev_warn(&phydev->mdio.dev, 391 "PHY failed to boot firmware, status=%04x\n", ret); 392 return -ENODEV; 393 } 394 395 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); 396 if (!priv) 397 return -ENOMEM; 398 399 dev_set_drvdata(&phydev->mdio.dev, priv); 400 401 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_FW_VER0); 402 if (ret < 0) 403 return ret; 404 405 priv->firmware_ver = ret << 16; 406 407 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_FW_VER1); 408 if (ret < 0) 409 return ret; 410 411 priv->firmware_ver |= ret; 412 413 phydev_info(phydev, "Firmware version %u.%u.%u.%u\n", 414 priv->firmware_ver >> 24, (priv->firmware_ver >> 16) & 255, 415 (priv->firmware_ver >> 8) & 255, priv->firmware_ver & 255); 416 417 /* Powering down the port when not in use saves about 600mW */ 418 ret = mv3310_power_down(phydev); 419 if (ret) 420 return ret; 421 422 ret = mv3310_hwmon_probe(phydev); 423 if (ret) 424 return ret; 425 426 return phy_sfp_probe(phydev, &mv3310_sfp_ops); 427 } 428 429 static int mv3310_suspend(struct phy_device *phydev) 430 { 431 return mv3310_power_down(phydev); 432 } 433 434 static int mv3310_resume(struct phy_device *phydev) 435 { 436 int ret; 437 438 ret = mv3310_power_up(phydev); 439 if (ret) 440 return ret; 441 442 return mv3310_hwmon_config(phydev, true); 443 } 444 445 /* Some PHYs in the Alaska family such as the 88X3310 and the 88E2010 446 * don't set bit 14 in PMA Extended Abilities (1.11), although they do 447 * support 2.5GBASET and 5GBASET. For these models, we can still read their 448 * 2.5G/5G extended abilities register (1.21). We detect these models based on 449 * the PMA device identifier, with a mask matching models known to have this 450 * issue 451 */ 452 static bool mv3310_has_pma_ngbaset_quirk(struct phy_device *phydev) 453 { 454 if (!(phydev->c45_ids.devices_in_package & MDIO_DEVS_PMAPMD)) 455 return false; 456 457 /* Only some revisions of the 88X3310 family PMA seem to be impacted */ 458 return (phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] & 459 MV_PHY_ALASKA_NBT_QUIRK_MASK) == MV_PHY_ALASKA_NBT_QUIRK_REV; 460 } 461 462 static int mv3310_config_init(struct phy_device *phydev) 463 { 464 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); 465 int err; 466 int val; 467 468 /* Check that the PHY interface type is compatible */ 469 if (phydev->interface != PHY_INTERFACE_MODE_SGMII && 470 phydev->interface != PHY_INTERFACE_MODE_2500BASEX && 471 phydev->interface != PHY_INTERFACE_MODE_XAUI && 472 phydev->interface != PHY_INTERFACE_MODE_RXAUI && 473 phydev->interface != PHY_INTERFACE_MODE_10GBASER) 474 return -ENODEV; 475 476 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; 477 478 /* Power up so reset works */ 479 err = mv3310_power_up(phydev); 480 if (err) 481 return err; 482 483 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL); 484 if (val < 0) 485 return val; 486 priv->rate_match = ((val & MV_V2_PORT_MAC_TYPE_MASK) == 487 MV_V2_PORT_MAC_TYPE_RATE_MATCH); 488 489 /* Enable EDPD mode - saving 600mW */ 490 return mv3310_set_edpd(phydev, ETHTOOL_PHY_EDPD_DFLT_TX_MSECS); 491 } 492 493 static int mv3310_get_features(struct phy_device *phydev) 494 { 495 int ret, val; 496 497 ret = genphy_c45_pma_read_abilities(phydev); 498 if (ret) 499 return ret; 500 501 if (mv3310_has_pma_ngbaset_quirk(phydev)) { 502 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, 503 MDIO_PMA_NG_EXTABLE); 504 if (val < 0) 505 return val; 506 507 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 508 phydev->supported, 509 val & MDIO_PMA_NG_EXTABLE_2_5GBT); 510 511 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 512 phydev->supported, 513 val & MDIO_PMA_NG_EXTABLE_5GBT); 514 } 515 516 return 0; 517 } 518 519 static int mv3310_config_mdix(struct phy_device *phydev) 520 { 521 u16 val; 522 int err; 523 524 switch (phydev->mdix_ctrl) { 525 case ETH_TP_MDI_AUTO: 526 val = MV_PCS_CSCR1_MDIX_AUTO; 527 break; 528 case ETH_TP_MDI_X: 529 val = MV_PCS_CSCR1_MDIX_MDIX; 530 break; 531 case ETH_TP_MDI: 532 val = MV_PCS_CSCR1_MDIX_MDI; 533 break; 534 default: 535 return -EINVAL; 536 } 537 538 err = phy_modify_mmd_changed(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1, 539 MV_PCS_CSCR1_MDIX_MASK, val); 540 if (err > 0) 541 err = mv3310_reset(phydev, MV_PCS_BASE_T); 542 543 return err; 544 } 545 546 static int mv3310_config_aneg(struct phy_device *phydev) 547 { 548 bool changed = false; 549 u16 reg; 550 int ret; 551 552 ret = mv3310_config_mdix(phydev); 553 if (ret < 0) 554 return ret; 555 556 if (phydev->autoneg == AUTONEG_DISABLE) 557 return genphy_c45_pma_setup_forced(phydev); 558 559 ret = genphy_c45_an_config_aneg(phydev); 560 if (ret < 0) 561 return ret; 562 if (ret > 0) 563 changed = true; 564 565 /* Clause 45 has no standardized support for 1000BaseT, therefore 566 * use vendor registers for this mode. 567 */ 568 reg = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising); 569 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MV_AN_CTRL1000, 570 ADVERTISE_1000FULL | ADVERTISE_1000HALF, reg); 571 if (ret < 0) 572 return ret; 573 if (ret > 0) 574 changed = true; 575 576 return genphy_c45_check_and_restart_aneg(phydev, changed); 577 } 578 579 static int mv3310_aneg_done(struct phy_device *phydev) 580 { 581 int val; 582 583 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1); 584 if (val < 0) 585 return val; 586 587 if (val & MDIO_STAT1_LSTATUS) 588 return 1; 589 590 return genphy_c45_aneg_done(phydev); 591 } 592 593 static void mv3310_update_interface(struct phy_device *phydev) 594 { 595 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); 596 597 /* In "XFI with Rate Matching" mode the PHY interface is fixed at 598 * 10Gb. The PHY adapts the rate to actual wire speed with help of 599 * internal 16KB buffer. 600 */ 601 if (priv->rate_match) { 602 phydev->interface = PHY_INTERFACE_MODE_10GBASER; 603 return; 604 } 605 606 if ((phydev->interface == PHY_INTERFACE_MODE_SGMII || 607 phydev->interface == PHY_INTERFACE_MODE_2500BASEX || 608 phydev->interface == PHY_INTERFACE_MODE_10GBASER) && 609 phydev->link) { 610 /* The PHY automatically switches its serdes interface (and 611 * active PHYXS instance) between Cisco SGMII, 10GBase-R and 612 * 2500BaseX modes according to the speed. Florian suggests 613 * setting phydev->interface to communicate this to the MAC. 614 * Only do this if we are already in one of the above modes. 615 */ 616 switch (phydev->speed) { 617 case SPEED_10000: 618 phydev->interface = PHY_INTERFACE_MODE_10GBASER; 619 break; 620 case SPEED_2500: 621 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 622 break; 623 case SPEED_1000: 624 case SPEED_100: 625 case SPEED_10: 626 phydev->interface = PHY_INTERFACE_MODE_SGMII; 627 break; 628 default: 629 break; 630 } 631 } 632 } 633 634 /* 10GBASE-ER,LR,LRM,SR do not support autonegotiation. */ 635 static int mv3310_read_status_10gbaser(struct phy_device *phydev) 636 { 637 phydev->link = 1; 638 phydev->speed = SPEED_10000; 639 phydev->duplex = DUPLEX_FULL; 640 641 return 0; 642 } 643 644 static int mv3310_read_status_copper(struct phy_device *phydev) 645 { 646 int cssr1, speed, val; 647 648 val = genphy_c45_read_link(phydev); 649 if (val < 0) 650 return val; 651 652 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); 653 if (val < 0) 654 return val; 655 656 cssr1 = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_CSSR1); 657 if (cssr1 < 0) 658 return val; 659 660 /* If the link settings are not resolved, mark the link down */ 661 if (!(cssr1 & MV_PCS_CSSR1_RESOLVED)) { 662 phydev->link = 0; 663 return 0; 664 } 665 666 /* Read the copper link settings */ 667 speed = cssr1 & MV_PCS_CSSR1_SPD1_MASK; 668 if (speed == MV_PCS_CSSR1_SPD1_SPD2) 669 speed |= cssr1 & MV_PCS_CSSR1_SPD2_MASK; 670 671 switch (speed) { 672 case MV_PCS_CSSR1_SPD1_SPD2 | MV_PCS_CSSR1_SPD2_10000: 673 phydev->speed = SPEED_10000; 674 break; 675 676 case MV_PCS_CSSR1_SPD1_SPD2 | MV_PCS_CSSR1_SPD2_5000: 677 phydev->speed = SPEED_5000; 678 break; 679 680 case MV_PCS_CSSR1_SPD1_SPD2 | MV_PCS_CSSR1_SPD2_2500: 681 phydev->speed = SPEED_2500; 682 break; 683 684 case MV_PCS_CSSR1_SPD1_1000: 685 phydev->speed = SPEED_1000; 686 break; 687 688 case MV_PCS_CSSR1_SPD1_100: 689 phydev->speed = SPEED_100; 690 break; 691 692 case MV_PCS_CSSR1_SPD1_10: 693 phydev->speed = SPEED_10; 694 break; 695 } 696 697 phydev->duplex = cssr1 & MV_PCS_CSSR1_DUPLEX_FULL ? 698 DUPLEX_FULL : DUPLEX_HALF; 699 phydev->mdix = cssr1 & MV_PCS_CSSR1_MDIX ? 700 ETH_TP_MDI_X : ETH_TP_MDI; 701 702 if (val & MDIO_AN_STAT1_COMPLETE) { 703 val = genphy_c45_read_lpa(phydev); 704 if (val < 0) 705 return val; 706 707 /* Read the link partner's 1G advertisement */ 708 val = phy_read_mmd(phydev, MDIO_MMD_AN, MV_AN_STAT1000); 709 if (val < 0) 710 return val; 711 712 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val); 713 714 /* Update the pause status */ 715 phy_resolve_aneg_pause(phydev); 716 } 717 718 return 0; 719 } 720 721 static int mv3310_read_status(struct phy_device *phydev) 722 { 723 int err, val; 724 725 phydev->speed = SPEED_UNKNOWN; 726 phydev->duplex = DUPLEX_UNKNOWN; 727 linkmode_zero(phydev->lp_advertising); 728 phydev->link = 0; 729 phydev->pause = 0; 730 phydev->asym_pause = 0; 731 phydev->mdix = ETH_TP_MDI_INVALID; 732 733 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1); 734 if (val < 0) 735 return val; 736 737 if (val & MDIO_STAT1_LSTATUS) 738 err = mv3310_read_status_10gbaser(phydev); 739 else 740 err = mv3310_read_status_copper(phydev); 741 if (err < 0) 742 return err; 743 744 if (phydev->link) 745 mv3310_update_interface(phydev); 746 747 return 0; 748 } 749 750 static int mv3310_get_tunable(struct phy_device *phydev, 751 struct ethtool_tunable *tuna, void *data) 752 { 753 switch (tuna->id) { 754 case ETHTOOL_PHY_EDPD: 755 return mv3310_get_edpd(phydev, data); 756 default: 757 return -EOPNOTSUPP; 758 } 759 } 760 761 static int mv3310_set_tunable(struct phy_device *phydev, 762 struct ethtool_tunable *tuna, const void *data) 763 { 764 switch (tuna->id) { 765 case ETHTOOL_PHY_EDPD: 766 return mv3310_set_edpd(phydev, *(u16 *)data); 767 default: 768 return -EOPNOTSUPP; 769 } 770 } 771 772 static struct phy_driver mv3310_drivers[] = { 773 { 774 .phy_id = MARVELL_PHY_ID_88X3310, 775 .phy_id_mask = MARVELL_PHY_ID_MASK, 776 .name = "mv88x3310", 777 .get_features = mv3310_get_features, 778 .config_init = mv3310_config_init, 779 .probe = mv3310_probe, 780 .suspend = mv3310_suspend, 781 .resume = mv3310_resume, 782 .config_aneg = mv3310_config_aneg, 783 .aneg_done = mv3310_aneg_done, 784 .read_status = mv3310_read_status, 785 .get_tunable = mv3310_get_tunable, 786 .set_tunable = mv3310_set_tunable, 787 }, 788 { 789 .phy_id = MARVELL_PHY_ID_88E2110, 790 .phy_id_mask = MARVELL_PHY_ID_MASK, 791 .name = "mv88x2110", 792 .probe = mv3310_probe, 793 .suspend = mv3310_suspend, 794 .resume = mv3310_resume, 795 .config_init = mv3310_config_init, 796 .config_aneg = mv3310_config_aneg, 797 .aneg_done = mv3310_aneg_done, 798 .read_status = mv3310_read_status, 799 .get_tunable = mv3310_get_tunable, 800 .set_tunable = mv3310_set_tunable, 801 }, 802 }; 803 804 module_phy_driver(mv3310_drivers); 805 806 static struct mdio_device_id __maybe_unused mv3310_tbl[] = { 807 { MARVELL_PHY_ID_88X3310, MARVELL_PHY_ID_MASK }, 808 { MARVELL_PHY_ID_88E2110, MARVELL_PHY_ID_MASK }, 809 { }, 810 }; 811 MODULE_DEVICE_TABLE(mdio, mv3310_tbl); 812 MODULE_DESCRIPTION("Marvell Alaska X 10Gigabit Ethernet PHY driver (MV88X3310)"); 813 MODULE_LICENSE("GPL"); 814