1 /* 2 * Marvell 10G 88x3310 PHY driver 3 * 4 * Based upon the ID registers, this PHY appears to be a mixture of IPs 5 * from two different companies. 6 * 7 * There appears to be several different data paths through the PHY which 8 * are automatically managed by the PHY. The following has been determined 9 * via observation and experimentation for a setup using single-lane Serdes: 10 * 11 * SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G) 12 * 10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G) 13 * 10GBASE-KR PHYXS -- BASE-R PCS -- Fiber 14 * 15 * With XAUI, observation shows: 16 * 17 * XAUI PHYXS -- <appropriate PCS as above> 18 * 19 * and no switching of the host interface mode occurs. 20 * 21 * If both the fiber and copper ports are connected, the first to gain 22 * link takes priority and the other port is completely locked out. 23 */ 24 #include <linux/ctype.h> 25 #include <linux/hwmon.h> 26 #include <linux/marvell_phy.h> 27 #include <linux/phy.h> 28 29 enum { 30 MV_PCS_BASE_T = 0x0000, 31 MV_PCS_BASE_R = 0x1000, 32 MV_PCS_1000BASEX = 0x2000, 33 34 MV_PCS_PAIRSWAP = 0x8182, 35 MV_PCS_PAIRSWAP_MASK = 0x0003, 36 MV_PCS_PAIRSWAP_AB = 0x0002, 37 MV_PCS_PAIRSWAP_NONE = 0x0003, 38 39 /* These registers appear at 0x800X and 0xa00X - the 0xa00X control 40 * registers appear to set themselves to the 0x800X when AN is 41 * restarted, but status registers appear readable from either. 42 */ 43 MV_AN_CTRL1000 = 0x8000, /* 1000base-T control register */ 44 MV_AN_STAT1000 = 0x8001, /* 1000base-T status register */ 45 46 /* Vendor2 MMD registers */ 47 MV_V2_TEMP_CTRL = 0xf08a, 48 MV_V2_TEMP_CTRL_MASK = 0xc000, 49 MV_V2_TEMP_CTRL_SAMPLE = 0x0000, 50 MV_V2_TEMP_CTRL_DISABLE = 0xc000, 51 MV_V2_TEMP = 0xf08c, 52 MV_V2_TEMP_UNKNOWN = 0x9600, /* unknown function */ 53 }; 54 55 struct mv3310_priv { 56 struct device *hwmon_dev; 57 char *hwmon_name; 58 }; 59 60 static int mv3310_modify(struct phy_device *phydev, int devad, u16 reg, 61 u16 mask, u16 bits) 62 { 63 int old, val, ret; 64 65 old = phy_read_mmd(phydev, devad, reg); 66 if (old < 0) 67 return old; 68 69 val = (old & ~mask) | (bits & mask); 70 if (val == old) 71 return 0; 72 73 ret = phy_write_mmd(phydev, devad, reg, val); 74 75 return ret < 0 ? ret : 1; 76 } 77 78 #ifdef CONFIG_HWMON 79 static umode_t mv3310_hwmon_is_visible(const void *data, 80 enum hwmon_sensor_types type, 81 u32 attr, int channel) 82 { 83 if (type == hwmon_chip && attr == hwmon_chip_update_interval) 84 return 0444; 85 if (type == hwmon_temp && attr == hwmon_temp_input) 86 return 0444; 87 return 0; 88 } 89 90 static int mv3310_hwmon_read(struct device *dev, enum hwmon_sensor_types type, 91 u32 attr, int channel, long *value) 92 { 93 struct phy_device *phydev = dev_get_drvdata(dev); 94 int temp; 95 96 if (type == hwmon_chip && attr == hwmon_chip_update_interval) { 97 *value = MSEC_PER_SEC; 98 return 0; 99 } 100 101 if (type == hwmon_temp && attr == hwmon_temp_input) { 102 temp = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP); 103 if (temp < 0) 104 return temp; 105 106 *value = ((temp & 0xff) - 75) * 1000; 107 108 return 0; 109 } 110 111 return -EOPNOTSUPP; 112 } 113 114 static const struct hwmon_ops mv3310_hwmon_ops = { 115 .is_visible = mv3310_hwmon_is_visible, 116 .read = mv3310_hwmon_read, 117 }; 118 119 static u32 mv3310_hwmon_chip_config[] = { 120 HWMON_C_REGISTER_TZ | HWMON_C_UPDATE_INTERVAL, 121 0, 122 }; 123 124 static const struct hwmon_channel_info mv3310_hwmon_chip = { 125 .type = hwmon_chip, 126 .config = mv3310_hwmon_chip_config, 127 }; 128 129 static u32 mv3310_hwmon_temp_config[] = { 130 HWMON_T_INPUT, 131 0, 132 }; 133 134 static const struct hwmon_channel_info mv3310_hwmon_temp = { 135 .type = hwmon_temp, 136 .config = mv3310_hwmon_temp_config, 137 }; 138 139 static const struct hwmon_channel_info *mv3310_hwmon_info[] = { 140 &mv3310_hwmon_chip, 141 &mv3310_hwmon_temp, 142 NULL, 143 }; 144 145 static const struct hwmon_chip_info mv3310_hwmon_chip_info = { 146 .ops = &mv3310_hwmon_ops, 147 .info = mv3310_hwmon_info, 148 }; 149 150 static int mv3310_hwmon_config(struct phy_device *phydev, bool enable) 151 { 152 u16 val; 153 int ret; 154 155 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP, 156 MV_V2_TEMP_UNKNOWN); 157 if (ret < 0) 158 return ret; 159 160 val = enable ? MV_V2_TEMP_CTRL_SAMPLE : MV_V2_TEMP_CTRL_DISABLE; 161 ret = mv3310_modify(phydev, MDIO_MMD_VEND2, MV_V2_TEMP_CTRL, 162 MV_V2_TEMP_CTRL_MASK, val); 163 164 return ret < 0 ? ret : 0; 165 } 166 167 static void mv3310_hwmon_disable(void *data) 168 { 169 struct phy_device *phydev = data; 170 171 mv3310_hwmon_config(phydev, false); 172 } 173 174 static int mv3310_hwmon_probe(struct phy_device *phydev) 175 { 176 struct device *dev = &phydev->mdio.dev; 177 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); 178 int i, j, ret; 179 180 priv->hwmon_name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL); 181 if (!priv->hwmon_name) 182 return -ENODEV; 183 184 for (i = j = 0; priv->hwmon_name[i]; i++) { 185 if (isalnum(priv->hwmon_name[i])) { 186 if (i != j) 187 priv->hwmon_name[j] = priv->hwmon_name[i]; 188 j++; 189 } 190 } 191 priv->hwmon_name[j] = '\0'; 192 193 ret = mv3310_hwmon_config(phydev, true); 194 if (ret) 195 return ret; 196 197 ret = devm_add_action_or_reset(dev, mv3310_hwmon_disable, phydev); 198 if (ret) 199 return ret; 200 201 priv->hwmon_dev = devm_hwmon_device_register_with_info(dev, 202 priv->hwmon_name, phydev, 203 &mv3310_hwmon_chip_info, NULL); 204 205 return PTR_ERR_OR_ZERO(priv->hwmon_dev); 206 } 207 #else 208 static inline int mv3310_hwmon_config(struct phy_device *phydev, bool enable) 209 { 210 return 0; 211 } 212 213 static int mv3310_hwmon_probe(struct phy_device *phydev) 214 { 215 return 0; 216 } 217 #endif 218 219 static int mv3310_probe(struct phy_device *phydev) 220 { 221 struct mv3310_priv *priv; 222 u32 mmd_mask = MDIO_DEVS_PMAPMD | MDIO_DEVS_AN; 223 int ret; 224 225 if (!phydev->is_c45 || 226 (phydev->c45_ids.devices_in_package & mmd_mask) != mmd_mask) 227 return -ENODEV; 228 229 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); 230 if (!priv) 231 return -ENOMEM; 232 233 dev_set_drvdata(&phydev->mdio.dev, priv); 234 235 ret = mv3310_hwmon_probe(phydev); 236 if (ret) 237 return ret; 238 239 return 0; 240 } 241 242 static int mv3310_suspend(struct phy_device *phydev) 243 { 244 return 0; 245 } 246 247 static int mv3310_resume(struct phy_device *phydev) 248 { 249 return mv3310_hwmon_config(phydev, true); 250 } 251 252 static int mv3310_config_init(struct phy_device *phydev) 253 { 254 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported) = { 0, }; 255 int val; 256 257 /* Check that the PHY interface type is compatible */ 258 if (phydev->interface != PHY_INTERFACE_MODE_SGMII && 259 phydev->interface != PHY_INTERFACE_MODE_XAUI && 260 phydev->interface != PHY_INTERFACE_MODE_RXAUI && 261 phydev->interface != PHY_INTERFACE_MODE_10GKR) 262 return -ENODEV; 263 264 __set_bit(ETHTOOL_LINK_MODE_Pause_BIT, supported); 265 __set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, supported); 266 267 if (phydev->c45_ids.devices_in_package & MDIO_DEVS_AN) { 268 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); 269 if (val < 0) 270 return val; 271 272 if (val & MDIO_AN_STAT1_ABLE) 273 __set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, supported); 274 } 275 276 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT2); 277 if (val < 0) 278 return val; 279 280 /* Ethtool does not support the WAN mode bits */ 281 if (val & (MDIO_PMA_STAT2_10GBSR | MDIO_PMA_STAT2_10GBLR | 282 MDIO_PMA_STAT2_10GBER | MDIO_PMA_STAT2_10GBLX4 | 283 MDIO_PMA_STAT2_10GBSW | MDIO_PMA_STAT2_10GBLW | 284 MDIO_PMA_STAT2_10GBEW)) 285 __set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, supported); 286 if (val & MDIO_PMA_STAT2_10GBSR) 287 __set_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, supported); 288 if (val & MDIO_PMA_STAT2_10GBLR) 289 __set_bit(ETHTOOL_LINK_MODE_10000baseLR_Full_BIT, supported); 290 if (val & MDIO_PMA_STAT2_10GBER) 291 __set_bit(ETHTOOL_LINK_MODE_10000baseER_Full_BIT, supported); 292 293 if (val & MDIO_PMA_STAT2_EXTABLE) { 294 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE); 295 if (val < 0) 296 return val; 297 298 if (val & (MDIO_PMA_EXTABLE_10GBT | MDIO_PMA_EXTABLE_1000BT | 299 MDIO_PMA_EXTABLE_100BTX | MDIO_PMA_EXTABLE_10BT)) 300 __set_bit(ETHTOOL_LINK_MODE_TP_BIT, supported); 301 if (val & MDIO_PMA_EXTABLE_10GBLRM) 302 __set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, supported); 303 if (val & (MDIO_PMA_EXTABLE_10GBKX4 | MDIO_PMA_EXTABLE_10GBKR | 304 MDIO_PMA_EXTABLE_1000BKX)) 305 __set_bit(ETHTOOL_LINK_MODE_Backplane_BIT, supported); 306 if (val & MDIO_PMA_EXTABLE_10GBLRM) 307 __set_bit(ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT, 308 supported); 309 if (val & MDIO_PMA_EXTABLE_10GBT) 310 __set_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 311 supported); 312 if (val & MDIO_PMA_EXTABLE_10GBKX4) 313 __set_bit(ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT, 314 supported); 315 if (val & MDIO_PMA_EXTABLE_10GBKR) 316 __set_bit(ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, 317 supported); 318 if (val & MDIO_PMA_EXTABLE_1000BT) 319 __set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 320 supported); 321 if (val & MDIO_PMA_EXTABLE_1000BKX) 322 __set_bit(ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, 323 supported); 324 if (val & MDIO_PMA_EXTABLE_100BTX) { 325 __set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, 326 supported); 327 __set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, 328 supported); 329 } 330 if (val & MDIO_PMA_EXTABLE_10BT) { 331 __set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, 332 supported); 333 __set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, 334 supported); 335 } 336 } 337 338 linkmode_copy(phydev->supported, supported); 339 linkmode_and(phydev->advertising, phydev->advertising, 340 phydev->supported); 341 342 return 0; 343 } 344 345 static int mv3310_config_aneg(struct phy_device *phydev) 346 { 347 bool changed = false; 348 u16 reg; 349 int ret; 350 351 /* We don't support manual MDI control */ 352 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; 353 354 if (phydev->autoneg == AUTONEG_DISABLE) { 355 ret = genphy_c45_pma_setup_forced(phydev); 356 if (ret < 0) 357 return ret; 358 359 return genphy_c45_an_disable_aneg(phydev); 360 } 361 362 linkmode_and(phydev->advertising, phydev->advertising, 363 phydev->supported); 364 365 ret = mv3310_modify(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE, 366 ADVERTISE_ALL | ADVERTISE_100BASE4 | 367 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM, 368 linkmode_adv_to_mii_adv_t(phydev->advertising)); 369 if (ret < 0) 370 return ret; 371 if (ret > 0) 372 changed = true; 373 374 reg = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising); 375 ret = mv3310_modify(phydev, MDIO_MMD_AN, MV_AN_CTRL1000, 376 ADVERTISE_1000FULL | ADVERTISE_1000HALF, reg); 377 if (ret < 0) 378 return ret; 379 if (ret > 0) 380 changed = true; 381 382 /* 10G control register */ 383 if (linkmode_test_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 384 phydev->advertising)) 385 reg = MDIO_AN_10GBT_CTRL_ADV10G; 386 else 387 reg = 0; 388 389 ret = mv3310_modify(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, 390 MDIO_AN_10GBT_CTRL_ADV10G, reg); 391 if (ret < 0) 392 return ret; 393 if (ret > 0) 394 changed = true; 395 396 if (changed) 397 ret = genphy_c45_restart_aneg(phydev); 398 399 return ret; 400 } 401 402 static int mv3310_aneg_done(struct phy_device *phydev) 403 { 404 int val; 405 406 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1); 407 if (val < 0) 408 return val; 409 410 if (val & MDIO_STAT1_LSTATUS) 411 return 1; 412 413 return genphy_c45_aneg_done(phydev); 414 } 415 416 static void mv3310_update_interface(struct phy_device *phydev) 417 { 418 if ((phydev->interface == PHY_INTERFACE_MODE_SGMII || 419 phydev->interface == PHY_INTERFACE_MODE_10GKR) && phydev->link) { 420 /* The PHY automatically switches its serdes interface (and 421 * active PHYXS instance) between Cisco SGMII and 10GBase-KR 422 * modes according to the speed. Florian suggests setting 423 * phydev->interface to communicate this to the MAC. Only do 424 * this if we are already in either SGMII or 10GBase-KR mode. 425 */ 426 if (phydev->speed == SPEED_10000) 427 phydev->interface = PHY_INTERFACE_MODE_10GKR; 428 else if (phydev->speed >= SPEED_10 && 429 phydev->speed < SPEED_10000) 430 phydev->interface = PHY_INTERFACE_MODE_SGMII; 431 } 432 } 433 434 /* 10GBASE-ER,LR,LRM,SR do not support autonegotiation. */ 435 static int mv3310_read_10gbr_status(struct phy_device *phydev) 436 { 437 phydev->link = 1; 438 phydev->speed = SPEED_10000; 439 phydev->duplex = DUPLEX_FULL; 440 441 mv3310_update_interface(phydev); 442 443 return 0; 444 } 445 446 static int mv3310_read_status(struct phy_device *phydev) 447 { 448 u32 mmd_mask = phydev->c45_ids.devices_in_package; 449 int val; 450 451 /* The vendor devads do not report link status. Avoid the PHYXS 452 * instance as there are three, and its status depends on the MAC 453 * being appropriately configured for the negotiated speed. 454 */ 455 mmd_mask &= ~(BIT(MDIO_MMD_VEND1) | BIT(MDIO_MMD_VEND2) | 456 BIT(MDIO_MMD_PHYXS)); 457 458 phydev->speed = SPEED_UNKNOWN; 459 phydev->duplex = DUPLEX_UNKNOWN; 460 linkmode_zero(phydev->lp_advertising); 461 phydev->link = 0; 462 phydev->pause = 0; 463 phydev->asym_pause = 0; 464 phydev->mdix = 0; 465 466 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1); 467 if (val < 0) 468 return val; 469 470 if (val & MDIO_STAT1_LSTATUS) 471 return mv3310_read_10gbr_status(phydev); 472 473 val = genphy_c45_read_link(phydev, mmd_mask); 474 if (val < 0) 475 return val; 476 477 phydev->link = val > 0 ? 1 : 0; 478 479 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); 480 if (val < 0) 481 return val; 482 483 if (val & MDIO_AN_STAT1_COMPLETE) { 484 val = genphy_c45_read_lpa(phydev); 485 if (val < 0) 486 return val; 487 488 /* Read the link partner's 1G advertisement */ 489 val = phy_read_mmd(phydev, MDIO_MMD_AN, MV_AN_STAT1000); 490 if (val < 0) 491 return val; 492 493 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val); 494 495 if (phydev->autoneg == AUTONEG_ENABLE) 496 phy_resolve_aneg_linkmode(phydev); 497 } 498 499 if (phydev->autoneg != AUTONEG_ENABLE) { 500 val = genphy_c45_read_pma(phydev); 501 if (val < 0) 502 return val; 503 } 504 505 if (phydev->speed == SPEED_10000) { 506 val = genphy_c45_read_mdix(phydev); 507 if (val < 0) 508 return val; 509 } else { 510 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_PAIRSWAP); 511 if (val < 0) 512 return val; 513 514 switch (val & MV_PCS_PAIRSWAP_MASK) { 515 case MV_PCS_PAIRSWAP_AB: 516 phydev->mdix = ETH_TP_MDI_X; 517 break; 518 case MV_PCS_PAIRSWAP_NONE: 519 phydev->mdix = ETH_TP_MDI; 520 break; 521 default: 522 phydev->mdix = ETH_TP_MDI_INVALID; 523 break; 524 } 525 } 526 527 mv3310_update_interface(phydev); 528 529 return 0; 530 } 531 532 static struct phy_driver mv3310_drivers[] = { 533 { 534 .phy_id = 0x002b09aa, 535 .phy_id_mask = MARVELL_PHY_ID_MASK, 536 .name = "mv88x3310", 537 .features = PHY_10GBIT_FEATURES, 538 .soft_reset = gen10g_no_soft_reset, 539 .config_init = mv3310_config_init, 540 .probe = mv3310_probe, 541 .suspend = mv3310_suspend, 542 .resume = mv3310_resume, 543 .config_aneg = mv3310_config_aneg, 544 .aneg_done = mv3310_aneg_done, 545 .read_status = mv3310_read_status, 546 }, 547 }; 548 549 module_phy_driver(mv3310_drivers); 550 551 static struct mdio_device_id __maybe_unused mv3310_tbl[] = { 552 { 0x002b09aa, MARVELL_PHY_ID_MASK }, 553 { }, 554 }; 555 MODULE_DEVICE_TABLE(mdio, mv3310_tbl); 556 MODULE_DESCRIPTION("Marvell Alaska X 10Gigabit Ethernet PHY driver (MV88X3310)"); 557 MODULE_LICENSE("GPL"); 558