1 /* 2 * Marvell 10G 88x3310 PHY driver 3 * 4 * Based upon the ID registers, this PHY appears to be a mixture of IPs 5 * from two different companies. 6 * 7 * There appears to be several different data paths through the PHY which 8 * are automatically managed by the PHY. The following has been determined 9 * via observation and experimentation for a setup using single-lane Serdes: 10 * 11 * SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G) 12 * 10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G) 13 * 10GBASE-KR PHYXS -- BASE-R PCS -- Fiber 14 * 15 * With XAUI, observation shows: 16 * 17 * XAUI PHYXS -- <appropriate PCS as above> 18 * 19 * and no switching of the host interface mode occurs. 20 * 21 * If both the fiber and copper ports are connected, the first to gain 22 * link takes priority and the other port is completely locked out. 23 */ 24 #include <linux/ctype.h> 25 #include <linux/hwmon.h> 26 #include <linux/marvell_phy.h> 27 #include <linux/phy.h> 28 29 #define MDIO_AN_10GBT_CTRL_ADV_NBT_MASK 0x01e0 30 31 enum { 32 MV_PCS_BASE_T = 0x0000, 33 MV_PCS_BASE_R = 0x1000, 34 MV_PCS_1000BASEX = 0x2000, 35 36 MV_PCS_PAIRSWAP = 0x8182, 37 MV_PCS_PAIRSWAP_MASK = 0x0003, 38 MV_PCS_PAIRSWAP_AB = 0x0002, 39 MV_PCS_PAIRSWAP_NONE = 0x0003, 40 41 /* These registers appear at 0x800X and 0xa00X - the 0xa00X control 42 * registers appear to set themselves to the 0x800X when AN is 43 * restarted, but status registers appear readable from either. 44 */ 45 MV_AN_CTRL1000 = 0x8000, /* 1000base-T control register */ 46 MV_AN_STAT1000 = 0x8001, /* 1000base-T status register */ 47 48 /* Vendor2 MMD registers */ 49 MV_V2_TEMP_CTRL = 0xf08a, 50 MV_V2_TEMP_CTRL_MASK = 0xc000, 51 MV_V2_TEMP_CTRL_SAMPLE = 0x0000, 52 MV_V2_TEMP_CTRL_DISABLE = 0xc000, 53 MV_V2_TEMP = 0xf08c, 54 MV_V2_TEMP_UNKNOWN = 0x9600, /* unknown function */ 55 }; 56 57 struct mv3310_priv { 58 struct device *hwmon_dev; 59 char *hwmon_name; 60 }; 61 62 static int mv3310_modify(struct phy_device *phydev, int devad, u16 reg, 63 u16 mask, u16 bits) 64 { 65 int old, val, ret; 66 67 old = phy_read_mmd(phydev, devad, reg); 68 if (old < 0) 69 return old; 70 71 val = (old & ~mask) | (bits & mask); 72 if (val == old) 73 return 0; 74 75 ret = phy_write_mmd(phydev, devad, reg, val); 76 77 return ret < 0 ? ret : 1; 78 } 79 80 #ifdef CONFIG_HWMON 81 static umode_t mv3310_hwmon_is_visible(const void *data, 82 enum hwmon_sensor_types type, 83 u32 attr, int channel) 84 { 85 if (type == hwmon_chip && attr == hwmon_chip_update_interval) 86 return 0444; 87 if (type == hwmon_temp && attr == hwmon_temp_input) 88 return 0444; 89 return 0; 90 } 91 92 static int mv3310_hwmon_read(struct device *dev, enum hwmon_sensor_types type, 93 u32 attr, int channel, long *value) 94 { 95 struct phy_device *phydev = dev_get_drvdata(dev); 96 int temp; 97 98 if (type == hwmon_chip && attr == hwmon_chip_update_interval) { 99 *value = MSEC_PER_SEC; 100 return 0; 101 } 102 103 if (type == hwmon_temp && attr == hwmon_temp_input) { 104 temp = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP); 105 if (temp < 0) 106 return temp; 107 108 *value = ((temp & 0xff) - 75) * 1000; 109 110 return 0; 111 } 112 113 return -EOPNOTSUPP; 114 } 115 116 static const struct hwmon_ops mv3310_hwmon_ops = { 117 .is_visible = mv3310_hwmon_is_visible, 118 .read = mv3310_hwmon_read, 119 }; 120 121 static u32 mv3310_hwmon_chip_config[] = { 122 HWMON_C_REGISTER_TZ | HWMON_C_UPDATE_INTERVAL, 123 0, 124 }; 125 126 static const struct hwmon_channel_info mv3310_hwmon_chip = { 127 .type = hwmon_chip, 128 .config = mv3310_hwmon_chip_config, 129 }; 130 131 static u32 mv3310_hwmon_temp_config[] = { 132 HWMON_T_INPUT, 133 0, 134 }; 135 136 static const struct hwmon_channel_info mv3310_hwmon_temp = { 137 .type = hwmon_temp, 138 .config = mv3310_hwmon_temp_config, 139 }; 140 141 static const struct hwmon_channel_info *mv3310_hwmon_info[] = { 142 &mv3310_hwmon_chip, 143 &mv3310_hwmon_temp, 144 NULL, 145 }; 146 147 static const struct hwmon_chip_info mv3310_hwmon_chip_info = { 148 .ops = &mv3310_hwmon_ops, 149 .info = mv3310_hwmon_info, 150 }; 151 152 static int mv3310_hwmon_config(struct phy_device *phydev, bool enable) 153 { 154 u16 val; 155 int ret; 156 157 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP, 158 MV_V2_TEMP_UNKNOWN); 159 if (ret < 0) 160 return ret; 161 162 val = enable ? MV_V2_TEMP_CTRL_SAMPLE : MV_V2_TEMP_CTRL_DISABLE; 163 ret = mv3310_modify(phydev, MDIO_MMD_VEND2, MV_V2_TEMP_CTRL, 164 MV_V2_TEMP_CTRL_MASK, val); 165 166 return ret < 0 ? ret : 0; 167 } 168 169 static void mv3310_hwmon_disable(void *data) 170 { 171 struct phy_device *phydev = data; 172 173 mv3310_hwmon_config(phydev, false); 174 } 175 176 static int mv3310_hwmon_probe(struct phy_device *phydev) 177 { 178 struct device *dev = &phydev->mdio.dev; 179 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); 180 int i, j, ret; 181 182 priv->hwmon_name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL); 183 if (!priv->hwmon_name) 184 return -ENODEV; 185 186 for (i = j = 0; priv->hwmon_name[i]; i++) { 187 if (isalnum(priv->hwmon_name[i])) { 188 if (i != j) 189 priv->hwmon_name[j] = priv->hwmon_name[i]; 190 j++; 191 } 192 } 193 priv->hwmon_name[j] = '\0'; 194 195 ret = mv3310_hwmon_config(phydev, true); 196 if (ret) 197 return ret; 198 199 ret = devm_add_action_or_reset(dev, mv3310_hwmon_disable, phydev); 200 if (ret) 201 return ret; 202 203 priv->hwmon_dev = devm_hwmon_device_register_with_info(dev, 204 priv->hwmon_name, phydev, 205 &mv3310_hwmon_chip_info, NULL); 206 207 return PTR_ERR_OR_ZERO(priv->hwmon_dev); 208 } 209 #else 210 static inline int mv3310_hwmon_config(struct phy_device *phydev, bool enable) 211 { 212 return 0; 213 } 214 215 static int mv3310_hwmon_probe(struct phy_device *phydev) 216 { 217 return 0; 218 } 219 #endif 220 221 static int mv3310_probe(struct phy_device *phydev) 222 { 223 struct mv3310_priv *priv; 224 u32 mmd_mask = MDIO_DEVS_PMAPMD | MDIO_DEVS_AN; 225 int ret; 226 227 if (!phydev->is_c45 || 228 (phydev->c45_ids.devices_in_package & mmd_mask) != mmd_mask) 229 return -ENODEV; 230 231 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); 232 if (!priv) 233 return -ENOMEM; 234 235 dev_set_drvdata(&phydev->mdio.dev, priv); 236 237 ret = mv3310_hwmon_probe(phydev); 238 if (ret) 239 return ret; 240 241 return 0; 242 } 243 244 static int mv3310_suspend(struct phy_device *phydev) 245 { 246 return 0; 247 } 248 249 static int mv3310_resume(struct phy_device *phydev) 250 { 251 return mv3310_hwmon_config(phydev, true); 252 } 253 254 static int mv3310_config_init(struct phy_device *phydev) 255 { 256 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported) = { 0, }; 257 int val; 258 259 /* Check that the PHY interface type is compatible */ 260 if (phydev->interface != PHY_INTERFACE_MODE_SGMII && 261 phydev->interface != PHY_INTERFACE_MODE_XAUI && 262 phydev->interface != PHY_INTERFACE_MODE_RXAUI && 263 phydev->interface != PHY_INTERFACE_MODE_10GKR) 264 return -ENODEV; 265 266 __set_bit(ETHTOOL_LINK_MODE_Pause_BIT, supported); 267 __set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, supported); 268 269 if (phydev->c45_ids.devices_in_package & MDIO_DEVS_AN) { 270 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); 271 if (val < 0) 272 return val; 273 274 if (val & MDIO_AN_STAT1_ABLE) 275 __set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, supported); 276 } 277 278 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT2); 279 if (val < 0) 280 return val; 281 282 /* Ethtool does not support the WAN mode bits */ 283 if (val & (MDIO_PMA_STAT2_10GBSR | MDIO_PMA_STAT2_10GBLR | 284 MDIO_PMA_STAT2_10GBER | MDIO_PMA_STAT2_10GBLX4 | 285 MDIO_PMA_STAT2_10GBSW | MDIO_PMA_STAT2_10GBLW | 286 MDIO_PMA_STAT2_10GBEW)) 287 __set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, supported); 288 if (val & MDIO_PMA_STAT2_10GBSR) 289 __set_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, supported); 290 if (val & MDIO_PMA_STAT2_10GBLR) 291 __set_bit(ETHTOOL_LINK_MODE_10000baseLR_Full_BIT, supported); 292 if (val & MDIO_PMA_STAT2_10GBER) 293 __set_bit(ETHTOOL_LINK_MODE_10000baseER_Full_BIT, supported); 294 295 if (val & MDIO_PMA_STAT2_EXTABLE) { 296 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE); 297 if (val < 0) 298 return val; 299 300 if (val & (MDIO_PMA_EXTABLE_10GBT | MDIO_PMA_EXTABLE_1000BT | 301 MDIO_PMA_EXTABLE_100BTX | MDIO_PMA_EXTABLE_10BT)) 302 __set_bit(ETHTOOL_LINK_MODE_TP_BIT, supported); 303 if (val & MDIO_PMA_EXTABLE_10GBLRM) 304 __set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, supported); 305 if (val & (MDIO_PMA_EXTABLE_10GBKX4 | MDIO_PMA_EXTABLE_10GBKR | 306 MDIO_PMA_EXTABLE_1000BKX)) 307 __set_bit(ETHTOOL_LINK_MODE_Backplane_BIT, supported); 308 if (val & MDIO_PMA_EXTABLE_10GBLRM) 309 __set_bit(ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT, 310 supported); 311 if (val & MDIO_PMA_EXTABLE_10GBT) 312 __set_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 313 supported); 314 if (val & MDIO_PMA_EXTABLE_10GBKX4) 315 __set_bit(ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT, 316 supported); 317 if (val & MDIO_PMA_EXTABLE_10GBKR) 318 __set_bit(ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, 319 supported); 320 if (val & MDIO_PMA_EXTABLE_1000BT) 321 __set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 322 supported); 323 if (val & MDIO_PMA_EXTABLE_1000BKX) 324 __set_bit(ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, 325 supported); 326 if (val & MDIO_PMA_EXTABLE_100BTX) { 327 __set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, 328 supported); 329 __set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, 330 supported); 331 } 332 if (val & MDIO_PMA_EXTABLE_10BT) { 333 __set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, 334 supported); 335 __set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, 336 supported); 337 } 338 } 339 340 linkmode_copy(phydev->supported, supported); 341 linkmode_and(phydev->advertising, phydev->advertising, 342 phydev->supported); 343 344 return 0; 345 } 346 347 static int mv3310_config_aneg(struct phy_device *phydev) 348 { 349 bool changed = false; 350 u16 reg; 351 int ret; 352 353 /* We don't support manual MDI control */ 354 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; 355 356 if (phydev->autoneg == AUTONEG_DISABLE) { 357 ret = genphy_c45_pma_setup_forced(phydev); 358 if (ret < 0) 359 return ret; 360 361 return genphy_c45_an_disable_aneg(phydev); 362 } 363 364 linkmode_and(phydev->advertising, phydev->advertising, 365 phydev->supported); 366 367 ret = mv3310_modify(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE, 368 ADVERTISE_ALL | ADVERTISE_100BASE4 | 369 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM, 370 linkmode_adv_to_mii_adv_t(phydev->advertising)); 371 if (ret < 0) 372 return ret; 373 if (ret > 0) 374 changed = true; 375 376 reg = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising); 377 ret = mv3310_modify(phydev, MDIO_MMD_AN, MV_AN_CTRL1000, 378 ADVERTISE_1000FULL | ADVERTISE_1000HALF, reg); 379 if (ret < 0) 380 return ret; 381 if (ret > 0) 382 changed = true; 383 384 /* 10G control register */ 385 if (linkmode_test_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 386 phydev->advertising)) 387 reg = MDIO_AN_10GBT_CTRL_ADV10G; 388 else 389 reg = 0; 390 391 /* Make sure we clear unsupported 2.5G/5G advertising */ 392 ret = mv3310_modify(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, 393 MDIO_AN_10GBT_CTRL_ADV10G | 394 MDIO_AN_10GBT_CTRL_ADV_NBT_MASK, reg); 395 if (ret < 0) 396 return ret; 397 if (ret > 0) 398 changed = true; 399 400 if (changed) 401 ret = genphy_c45_restart_aneg(phydev); 402 403 return ret; 404 } 405 406 static int mv3310_aneg_done(struct phy_device *phydev) 407 { 408 int val; 409 410 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1); 411 if (val < 0) 412 return val; 413 414 if (val & MDIO_STAT1_LSTATUS) 415 return 1; 416 417 return genphy_c45_aneg_done(phydev); 418 } 419 420 static void mv3310_update_interface(struct phy_device *phydev) 421 { 422 if ((phydev->interface == PHY_INTERFACE_MODE_SGMII || 423 phydev->interface == PHY_INTERFACE_MODE_10GKR) && phydev->link) { 424 /* The PHY automatically switches its serdes interface (and 425 * active PHYXS instance) between Cisco SGMII and 10GBase-KR 426 * modes according to the speed. Florian suggests setting 427 * phydev->interface to communicate this to the MAC. Only do 428 * this if we are already in either SGMII or 10GBase-KR mode. 429 */ 430 if (phydev->speed == SPEED_10000) 431 phydev->interface = PHY_INTERFACE_MODE_10GKR; 432 else if (phydev->speed >= SPEED_10 && 433 phydev->speed < SPEED_10000) 434 phydev->interface = PHY_INTERFACE_MODE_SGMII; 435 } 436 } 437 438 /* 10GBASE-ER,LR,LRM,SR do not support autonegotiation. */ 439 static int mv3310_read_10gbr_status(struct phy_device *phydev) 440 { 441 phydev->link = 1; 442 phydev->speed = SPEED_10000; 443 phydev->duplex = DUPLEX_FULL; 444 445 mv3310_update_interface(phydev); 446 447 return 0; 448 } 449 450 static int mv3310_read_status(struct phy_device *phydev) 451 { 452 u32 mmd_mask = phydev->c45_ids.devices_in_package; 453 int val; 454 455 /* The vendor devads do not report link status. Avoid the PHYXS 456 * instance as there are three, and its status depends on the MAC 457 * being appropriately configured for the negotiated speed. 458 */ 459 mmd_mask &= ~(BIT(MDIO_MMD_VEND1) | BIT(MDIO_MMD_VEND2) | 460 BIT(MDIO_MMD_PHYXS)); 461 462 phydev->speed = SPEED_UNKNOWN; 463 phydev->duplex = DUPLEX_UNKNOWN; 464 linkmode_zero(phydev->lp_advertising); 465 phydev->link = 0; 466 phydev->pause = 0; 467 phydev->asym_pause = 0; 468 phydev->mdix = 0; 469 470 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1); 471 if (val < 0) 472 return val; 473 474 if (val & MDIO_STAT1_LSTATUS) 475 return mv3310_read_10gbr_status(phydev); 476 477 val = genphy_c45_read_link(phydev, mmd_mask); 478 if (val < 0) 479 return val; 480 481 phydev->link = val > 0 ? 1 : 0; 482 483 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); 484 if (val < 0) 485 return val; 486 487 if (val & MDIO_AN_STAT1_COMPLETE) { 488 val = genphy_c45_read_lpa(phydev); 489 if (val < 0) 490 return val; 491 492 /* Read the link partner's 1G advertisement */ 493 val = phy_read_mmd(phydev, MDIO_MMD_AN, MV_AN_STAT1000); 494 if (val < 0) 495 return val; 496 497 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val); 498 499 if (phydev->autoneg == AUTONEG_ENABLE) 500 phy_resolve_aneg_linkmode(phydev); 501 } 502 503 if (phydev->autoneg != AUTONEG_ENABLE) { 504 val = genphy_c45_read_pma(phydev); 505 if (val < 0) 506 return val; 507 } 508 509 if (phydev->speed == SPEED_10000) { 510 val = genphy_c45_read_mdix(phydev); 511 if (val < 0) 512 return val; 513 } else { 514 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_PAIRSWAP); 515 if (val < 0) 516 return val; 517 518 switch (val & MV_PCS_PAIRSWAP_MASK) { 519 case MV_PCS_PAIRSWAP_AB: 520 phydev->mdix = ETH_TP_MDI_X; 521 break; 522 case MV_PCS_PAIRSWAP_NONE: 523 phydev->mdix = ETH_TP_MDI; 524 break; 525 default: 526 phydev->mdix = ETH_TP_MDI_INVALID; 527 break; 528 } 529 } 530 531 mv3310_update_interface(phydev); 532 533 return 0; 534 } 535 536 static struct phy_driver mv3310_drivers[] = { 537 { 538 .phy_id = 0x002b09aa, 539 .phy_id_mask = MARVELL_PHY_ID_MASK, 540 .name = "mv88x3310", 541 .features = PHY_10GBIT_FEATURES, 542 .soft_reset = gen10g_no_soft_reset, 543 .config_init = mv3310_config_init, 544 .probe = mv3310_probe, 545 .suspend = mv3310_suspend, 546 .resume = mv3310_resume, 547 .config_aneg = mv3310_config_aneg, 548 .aneg_done = mv3310_aneg_done, 549 .read_status = mv3310_read_status, 550 }, 551 }; 552 553 module_phy_driver(mv3310_drivers); 554 555 static struct mdio_device_id __maybe_unused mv3310_tbl[] = { 556 { 0x002b09aa, MARVELL_PHY_ID_MASK }, 557 { }, 558 }; 559 MODULE_DEVICE_TABLE(mdio, mv3310_tbl); 560 MODULE_DESCRIPTION("Marvell Alaska X 10Gigabit Ethernet PHY driver (MV88X3310)"); 561 MODULE_LICENSE("GPL"); 562