1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Marvell 10G 88x3310 PHY driver 4 * 5 * Based upon the ID registers, this PHY appears to be a mixture of IPs 6 * from two different companies. 7 * 8 * There appears to be several different data paths through the PHY which 9 * are automatically managed by the PHY. The following has been determined 10 * via observation and experimentation for a setup using single-lane Serdes: 11 * 12 * SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G) 13 * 10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G) 14 * 10GBASE-KR PHYXS -- BASE-R PCS -- Fiber 15 * 16 * With XAUI, observation shows: 17 * 18 * XAUI PHYXS -- <appropriate PCS as above> 19 * 20 * and no switching of the host interface mode occurs. 21 * 22 * If both the fiber and copper ports are connected, the first to gain 23 * link takes priority and the other port is completely locked out. 24 */ 25 #include <linux/ctype.h> 26 #include <linux/hwmon.h> 27 #include <linux/marvell_phy.h> 28 #include <linux/phy.h> 29 30 enum { 31 MV_PCS_BASE_T = 0x0000, 32 MV_PCS_BASE_R = 0x1000, 33 MV_PCS_1000BASEX = 0x2000, 34 35 MV_PCS_PAIRSWAP = 0x8182, 36 MV_PCS_PAIRSWAP_MASK = 0x0003, 37 MV_PCS_PAIRSWAP_AB = 0x0002, 38 MV_PCS_PAIRSWAP_NONE = 0x0003, 39 40 /* These registers appear at 0x800X and 0xa00X - the 0xa00X control 41 * registers appear to set themselves to the 0x800X when AN is 42 * restarted, but status registers appear readable from either. 43 */ 44 MV_AN_CTRL1000 = 0x8000, /* 1000base-T control register */ 45 MV_AN_STAT1000 = 0x8001, /* 1000base-T status register */ 46 47 /* Vendor2 MMD registers */ 48 MV_V2_TEMP_CTRL = 0xf08a, 49 MV_V2_TEMP_CTRL_MASK = 0xc000, 50 MV_V2_TEMP_CTRL_SAMPLE = 0x0000, 51 MV_V2_TEMP_CTRL_DISABLE = 0xc000, 52 MV_V2_TEMP = 0xf08c, 53 MV_V2_TEMP_UNKNOWN = 0x9600, /* unknown function */ 54 }; 55 56 struct mv3310_priv { 57 struct device *hwmon_dev; 58 char *hwmon_name; 59 }; 60 61 static int mv3310_modify(struct phy_device *phydev, int devad, u16 reg, 62 u16 mask, u16 bits) 63 { 64 int old, val, ret; 65 66 old = phy_read_mmd(phydev, devad, reg); 67 if (old < 0) 68 return old; 69 70 val = (old & ~mask) | (bits & mask); 71 if (val == old) 72 return 0; 73 74 ret = phy_write_mmd(phydev, devad, reg, val); 75 76 return ret < 0 ? ret : 1; 77 } 78 79 #ifdef CONFIG_HWMON 80 static umode_t mv3310_hwmon_is_visible(const void *data, 81 enum hwmon_sensor_types type, 82 u32 attr, int channel) 83 { 84 if (type == hwmon_chip && attr == hwmon_chip_update_interval) 85 return 0444; 86 if (type == hwmon_temp && attr == hwmon_temp_input) 87 return 0444; 88 return 0; 89 } 90 91 static int mv3310_hwmon_read(struct device *dev, enum hwmon_sensor_types type, 92 u32 attr, int channel, long *value) 93 { 94 struct phy_device *phydev = dev_get_drvdata(dev); 95 int temp; 96 97 if (type == hwmon_chip && attr == hwmon_chip_update_interval) { 98 *value = MSEC_PER_SEC; 99 return 0; 100 } 101 102 if (type == hwmon_temp && attr == hwmon_temp_input) { 103 temp = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP); 104 if (temp < 0) 105 return temp; 106 107 *value = ((temp & 0xff) - 75) * 1000; 108 109 return 0; 110 } 111 112 return -EOPNOTSUPP; 113 } 114 115 static const struct hwmon_ops mv3310_hwmon_ops = { 116 .is_visible = mv3310_hwmon_is_visible, 117 .read = mv3310_hwmon_read, 118 }; 119 120 static u32 mv3310_hwmon_chip_config[] = { 121 HWMON_C_REGISTER_TZ | HWMON_C_UPDATE_INTERVAL, 122 0, 123 }; 124 125 static const struct hwmon_channel_info mv3310_hwmon_chip = { 126 .type = hwmon_chip, 127 .config = mv3310_hwmon_chip_config, 128 }; 129 130 static u32 mv3310_hwmon_temp_config[] = { 131 HWMON_T_INPUT, 132 0, 133 }; 134 135 static const struct hwmon_channel_info mv3310_hwmon_temp = { 136 .type = hwmon_temp, 137 .config = mv3310_hwmon_temp_config, 138 }; 139 140 static const struct hwmon_channel_info *mv3310_hwmon_info[] = { 141 &mv3310_hwmon_chip, 142 &mv3310_hwmon_temp, 143 NULL, 144 }; 145 146 static const struct hwmon_chip_info mv3310_hwmon_chip_info = { 147 .ops = &mv3310_hwmon_ops, 148 .info = mv3310_hwmon_info, 149 }; 150 151 static int mv3310_hwmon_config(struct phy_device *phydev, bool enable) 152 { 153 u16 val; 154 int ret; 155 156 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP, 157 MV_V2_TEMP_UNKNOWN); 158 if (ret < 0) 159 return ret; 160 161 val = enable ? MV_V2_TEMP_CTRL_SAMPLE : MV_V2_TEMP_CTRL_DISABLE; 162 ret = mv3310_modify(phydev, MDIO_MMD_VEND2, MV_V2_TEMP_CTRL, 163 MV_V2_TEMP_CTRL_MASK, val); 164 165 return ret < 0 ? ret : 0; 166 } 167 168 static void mv3310_hwmon_disable(void *data) 169 { 170 struct phy_device *phydev = data; 171 172 mv3310_hwmon_config(phydev, false); 173 } 174 175 static int mv3310_hwmon_probe(struct phy_device *phydev) 176 { 177 struct device *dev = &phydev->mdio.dev; 178 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); 179 int i, j, ret; 180 181 priv->hwmon_name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL); 182 if (!priv->hwmon_name) 183 return -ENODEV; 184 185 for (i = j = 0; priv->hwmon_name[i]; i++) { 186 if (isalnum(priv->hwmon_name[i])) { 187 if (i != j) 188 priv->hwmon_name[j] = priv->hwmon_name[i]; 189 j++; 190 } 191 } 192 priv->hwmon_name[j] = '\0'; 193 194 ret = mv3310_hwmon_config(phydev, true); 195 if (ret) 196 return ret; 197 198 ret = devm_add_action_or_reset(dev, mv3310_hwmon_disable, phydev); 199 if (ret) 200 return ret; 201 202 priv->hwmon_dev = devm_hwmon_device_register_with_info(dev, 203 priv->hwmon_name, phydev, 204 &mv3310_hwmon_chip_info, NULL); 205 206 return PTR_ERR_OR_ZERO(priv->hwmon_dev); 207 } 208 #else 209 static inline int mv3310_hwmon_config(struct phy_device *phydev, bool enable) 210 { 211 return 0; 212 } 213 214 static int mv3310_hwmon_probe(struct phy_device *phydev) 215 { 216 return 0; 217 } 218 #endif 219 220 static int mv3310_probe(struct phy_device *phydev) 221 { 222 struct mv3310_priv *priv; 223 u32 mmd_mask = MDIO_DEVS_PMAPMD | MDIO_DEVS_AN; 224 int ret; 225 226 if (!phydev->is_c45 || 227 (phydev->c45_ids.devices_in_package & mmd_mask) != mmd_mask) 228 return -ENODEV; 229 230 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); 231 if (!priv) 232 return -ENOMEM; 233 234 dev_set_drvdata(&phydev->mdio.dev, priv); 235 236 ret = mv3310_hwmon_probe(phydev); 237 if (ret) 238 return ret; 239 240 return 0; 241 } 242 243 static int mv3310_suspend(struct phy_device *phydev) 244 { 245 return 0; 246 } 247 248 static int mv3310_resume(struct phy_device *phydev) 249 { 250 return mv3310_hwmon_config(phydev, true); 251 } 252 253 static int mv3310_config_init(struct phy_device *phydev) 254 { 255 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported) = { 0, }; 256 int val; 257 258 /* Check that the PHY interface type is compatible */ 259 if (phydev->interface != PHY_INTERFACE_MODE_SGMII && 260 phydev->interface != PHY_INTERFACE_MODE_XAUI && 261 phydev->interface != PHY_INTERFACE_MODE_RXAUI && 262 phydev->interface != PHY_INTERFACE_MODE_10GKR) 263 return -ENODEV; 264 265 __set_bit(ETHTOOL_LINK_MODE_Pause_BIT, supported); 266 __set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, supported); 267 268 if (phydev->c45_ids.devices_in_package & MDIO_DEVS_AN) { 269 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); 270 if (val < 0) 271 return val; 272 273 if (val & MDIO_AN_STAT1_ABLE) 274 __set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, supported); 275 } 276 277 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT2); 278 if (val < 0) 279 return val; 280 281 /* Ethtool does not support the WAN mode bits */ 282 if (val & (MDIO_PMA_STAT2_10GBSR | MDIO_PMA_STAT2_10GBLR | 283 MDIO_PMA_STAT2_10GBER | MDIO_PMA_STAT2_10GBLX4 | 284 MDIO_PMA_STAT2_10GBSW | MDIO_PMA_STAT2_10GBLW | 285 MDIO_PMA_STAT2_10GBEW)) 286 __set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, supported); 287 if (val & MDIO_PMA_STAT2_10GBSR) 288 __set_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, supported); 289 if (val & MDIO_PMA_STAT2_10GBLR) 290 __set_bit(ETHTOOL_LINK_MODE_10000baseLR_Full_BIT, supported); 291 if (val & MDIO_PMA_STAT2_10GBER) 292 __set_bit(ETHTOOL_LINK_MODE_10000baseER_Full_BIT, supported); 293 294 if (val & MDIO_PMA_STAT2_EXTABLE) { 295 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE); 296 if (val < 0) 297 return val; 298 299 if (val & (MDIO_PMA_EXTABLE_10GBT | MDIO_PMA_EXTABLE_1000BT | 300 MDIO_PMA_EXTABLE_100BTX | MDIO_PMA_EXTABLE_10BT)) 301 __set_bit(ETHTOOL_LINK_MODE_TP_BIT, supported); 302 if (val & MDIO_PMA_EXTABLE_10GBLRM) 303 __set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, supported); 304 if (val & (MDIO_PMA_EXTABLE_10GBKX4 | MDIO_PMA_EXTABLE_10GBKR | 305 MDIO_PMA_EXTABLE_1000BKX)) 306 __set_bit(ETHTOOL_LINK_MODE_Backplane_BIT, supported); 307 if (val & MDIO_PMA_EXTABLE_10GBLRM) 308 __set_bit(ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT, 309 supported); 310 if (val & MDIO_PMA_EXTABLE_10GBT) 311 __set_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 312 supported); 313 if (val & MDIO_PMA_EXTABLE_10GBKX4) 314 __set_bit(ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT, 315 supported); 316 if (val & MDIO_PMA_EXTABLE_10GBKR) 317 __set_bit(ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, 318 supported); 319 if (val & MDIO_PMA_EXTABLE_1000BT) 320 __set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 321 supported); 322 if (val & MDIO_PMA_EXTABLE_1000BKX) 323 __set_bit(ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, 324 supported); 325 if (val & MDIO_PMA_EXTABLE_100BTX) { 326 __set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, 327 supported); 328 __set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, 329 supported); 330 } 331 if (val & MDIO_PMA_EXTABLE_10BT) { 332 __set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, 333 supported); 334 __set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, 335 supported); 336 } 337 } 338 339 linkmode_copy(phydev->supported, supported); 340 linkmode_and(phydev->advertising, phydev->advertising, 341 phydev->supported); 342 343 return 0; 344 } 345 346 static int mv3310_config_aneg(struct phy_device *phydev) 347 { 348 bool changed = false; 349 u16 reg; 350 int ret; 351 352 /* We don't support manual MDI control */ 353 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; 354 355 if (phydev->autoneg == AUTONEG_DISABLE) { 356 ret = genphy_c45_pma_setup_forced(phydev); 357 if (ret < 0) 358 return ret; 359 360 return genphy_c45_an_disable_aneg(phydev); 361 } 362 363 linkmode_and(phydev->advertising, phydev->advertising, 364 phydev->supported); 365 366 ret = mv3310_modify(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE, 367 ADVERTISE_ALL | ADVERTISE_100BASE4 | 368 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM, 369 linkmode_adv_to_mii_adv_t(phydev->advertising)); 370 if (ret < 0) 371 return ret; 372 if (ret > 0) 373 changed = true; 374 375 reg = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising); 376 ret = mv3310_modify(phydev, MDIO_MMD_AN, MV_AN_CTRL1000, 377 ADVERTISE_1000FULL | ADVERTISE_1000HALF, reg); 378 if (ret < 0) 379 return ret; 380 if (ret > 0) 381 changed = true; 382 383 /* 10G control register */ 384 if (linkmode_test_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 385 phydev->advertising)) 386 reg = MDIO_AN_10GBT_CTRL_ADV10G; 387 else 388 reg = 0; 389 390 ret = mv3310_modify(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, 391 MDIO_AN_10GBT_CTRL_ADV10G, reg); 392 if (ret < 0) 393 return ret; 394 if (ret > 0) 395 changed = true; 396 397 if (changed) 398 ret = genphy_c45_restart_aneg(phydev); 399 400 return ret; 401 } 402 403 static int mv3310_aneg_done(struct phy_device *phydev) 404 { 405 int val; 406 407 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1); 408 if (val < 0) 409 return val; 410 411 if (val & MDIO_STAT1_LSTATUS) 412 return 1; 413 414 return genphy_c45_aneg_done(phydev); 415 } 416 417 static void mv3310_update_interface(struct phy_device *phydev) 418 { 419 if ((phydev->interface == PHY_INTERFACE_MODE_SGMII || 420 phydev->interface == PHY_INTERFACE_MODE_10GKR) && phydev->link) { 421 /* The PHY automatically switches its serdes interface (and 422 * active PHYXS instance) between Cisco SGMII and 10GBase-KR 423 * modes according to the speed. Florian suggests setting 424 * phydev->interface to communicate this to the MAC. Only do 425 * this if we are already in either SGMII or 10GBase-KR mode. 426 */ 427 if (phydev->speed == SPEED_10000) 428 phydev->interface = PHY_INTERFACE_MODE_10GKR; 429 else if (phydev->speed >= SPEED_10 && 430 phydev->speed < SPEED_10000) 431 phydev->interface = PHY_INTERFACE_MODE_SGMII; 432 } 433 } 434 435 /* 10GBASE-ER,LR,LRM,SR do not support autonegotiation. */ 436 static int mv3310_read_10gbr_status(struct phy_device *phydev) 437 { 438 phydev->link = 1; 439 phydev->speed = SPEED_10000; 440 phydev->duplex = DUPLEX_FULL; 441 442 mv3310_update_interface(phydev); 443 444 return 0; 445 } 446 447 static int mv3310_read_status(struct phy_device *phydev) 448 { 449 u32 mmd_mask = phydev->c45_ids.devices_in_package; 450 int val; 451 452 /* The vendor devads do not report link status. Avoid the PHYXS 453 * instance as there are three, and its status depends on the MAC 454 * being appropriately configured for the negotiated speed. 455 */ 456 mmd_mask &= ~(BIT(MDIO_MMD_VEND1) | BIT(MDIO_MMD_VEND2) | 457 BIT(MDIO_MMD_PHYXS)); 458 459 phydev->speed = SPEED_UNKNOWN; 460 phydev->duplex = DUPLEX_UNKNOWN; 461 linkmode_zero(phydev->lp_advertising); 462 phydev->link = 0; 463 phydev->pause = 0; 464 phydev->asym_pause = 0; 465 phydev->mdix = 0; 466 467 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1); 468 if (val < 0) 469 return val; 470 471 if (val & MDIO_STAT1_LSTATUS) 472 return mv3310_read_10gbr_status(phydev); 473 474 val = genphy_c45_read_link(phydev, mmd_mask); 475 if (val < 0) 476 return val; 477 478 phydev->link = val > 0 ? 1 : 0; 479 480 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); 481 if (val < 0) 482 return val; 483 484 if (val & MDIO_AN_STAT1_COMPLETE) { 485 val = genphy_c45_read_lpa(phydev); 486 if (val < 0) 487 return val; 488 489 /* Read the link partner's 1G advertisement */ 490 val = phy_read_mmd(phydev, MDIO_MMD_AN, MV_AN_STAT1000); 491 if (val < 0) 492 return val; 493 494 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val); 495 496 if (phydev->autoneg == AUTONEG_ENABLE) 497 phy_resolve_aneg_linkmode(phydev); 498 } 499 500 if (phydev->autoneg != AUTONEG_ENABLE) { 501 val = genphy_c45_read_pma(phydev); 502 if (val < 0) 503 return val; 504 } 505 506 if (phydev->speed == SPEED_10000) { 507 val = genphy_c45_read_mdix(phydev); 508 if (val < 0) 509 return val; 510 } else { 511 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_PAIRSWAP); 512 if (val < 0) 513 return val; 514 515 switch (val & MV_PCS_PAIRSWAP_MASK) { 516 case MV_PCS_PAIRSWAP_AB: 517 phydev->mdix = ETH_TP_MDI_X; 518 break; 519 case MV_PCS_PAIRSWAP_NONE: 520 phydev->mdix = ETH_TP_MDI; 521 break; 522 default: 523 phydev->mdix = ETH_TP_MDI_INVALID; 524 break; 525 } 526 } 527 528 mv3310_update_interface(phydev); 529 530 return 0; 531 } 532 533 static struct phy_driver mv3310_drivers[] = { 534 { 535 .phy_id = 0x002b09aa, 536 .phy_id_mask = MARVELL_PHY_ID_MASK, 537 .name = "mv88x3310", 538 .features = PHY_10GBIT_FEATURES, 539 .soft_reset = gen10g_no_soft_reset, 540 .config_init = mv3310_config_init, 541 .probe = mv3310_probe, 542 .suspend = mv3310_suspend, 543 .resume = mv3310_resume, 544 .config_aneg = mv3310_config_aneg, 545 .aneg_done = mv3310_aneg_done, 546 .read_status = mv3310_read_status, 547 }, 548 }; 549 550 module_phy_driver(mv3310_drivers); 551 552 static struct mdio_device_id __maybe_unused mv3310_tbl[] = { 553 { 0x002b09aa, MARVELL_PHY_ID_MASK }, 554 { }, 555 }; 556 MODULE_DEVICE_TABLE(mdio, mv3310_tbl); 557 MODULE_DESCRIPTION("Marvell Alaska X 10Gigabit Ethernet PHY driver (MV88X3310)"); 558 MODULE_LICENSE("GPL"); 559