1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Marvell 10G 88x3310 PHY driver 4 * 5 * Based upon the ID registers, this PHY appears to be a mixture of IPs 6 * from two different companies. 7 * 8 * There appears to be several different data paths through the PHY which 9 * are automatically managed by the PHY. The following has been determined 10 * via observation and experimentation for a setup using single-lane Serdes: 11 * 12 * SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G) 13 * 10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G) 14 * 10GBASE-KR PHYXS -- BASE-R PCS -- Fiber 15 * 16 * With XAUI, observation shows: 17 * 18 * XAUI PHYXS -- <appropriate PCS as above> 19 * 20 * and no switching of the host interface mode occurs. 21 * 22 * If both the fiber and copper ports are connected, the first to gain 23 * link takes priority and the other port is completely locked out. 24 */ 25 #include <linux/ctype.h> 26 #include <linux/delay.h> 27 #include <linux/hwmon.h> 28 #include <linux/marvell_phy.h> 29 #include <linux/phy.h> 30 #include <linux/sfp.h> 31 32 #define MV_PHY_ALASKA_NBT_QUIRK_MASK 0xfffffffe 33 #define MV_PHY_ALASKA_NBT_QUIRK_REV (MARVELL_PHY_ID_88X3310 | 0xa) 34 35 enum { 36 MV_PMA_FW_VER0 = 0xc011, 37 MV_PMA_FW_VER1 = 0xc012, 38 MV_PMA_BOOT = 0xc050, 39 MV_PMA_BOOT_FATAL = BIT(0), 40 41 MV_PCS_BASE_T = 0x0000, 42 MV_PCS_BASE_R = 0x1000, 43 MV_PCS_1000BASEX = 0x2000, 44 45 MV_PCS_CSCR1 = 0x8000, 46 MV_PCS_CSCR1_ED_MASK = 0x0300, 47 MV_PCS_CSCR1_ED_OFF = 0x0000, 48 MV_PCS_CSCR1_ED_RX = 0x0200, 49 MV_PCS_CSCR1_ED_NLP = 0x0300, 50 MV_PCS_CSCR1_MDIX_MASK = 0x0060, 51 MV_PCS_CSCR1_MDIX_MDI = 0x0000, 52 MV_PCS_CSCR1_MDIX_MDIX = 0x0020, 53 MV_PCS_CSCR1_MDIX_AUTO = 0x0060, 54 55 MV_PCS_CSSR1 = 0x8008, 56 MV_PCS_CSSR1_SPD1_MASK = 0xc000, 57 MV_PCS_CSSR1_SPD1_SPD2 = 0xc000, 58 MV_PCS_CSSR1_SPD1_1000 = 0x8000, 59 MV_PCS_CSSR1_SPD1_100 = 0x4000, 60 MV_PCS_CSSR1_SPD1_10 = 0x0000, 61 MV_PCS_CSSR1_DUPLEX_FULL= BIT(13), 62 MV_PCS_CSSR1_RESOLVED = BIT(11), 63 MV_PCS_CSSR1_MDIX = BIT(6), 64 MV_PCS_CSSR1_SPD2_MASK = 0x000c, 65 MV_PCS_CSSR1_SPD2_5000 = 0x0008, 66 MV_PCS_CSSR1_SPD2_2500 = 0x0004, 67 MV_PCS_CSSR1_SPD2_10000 = 0x0000, 68 69 /* Temperature read register (88E2110 only) */ 70 MV_PCS_TEMP = 0x8042, 71 72 /* These registers appear at 0x800X and 0xa00X - the 0xa00X control 73 * registers appear to set themselves to the 0x800X when AN is 74 * restarted, but status registers appear readable from either. 75 */ 76 MV_AN_CTRL1000 = 0x8000, /* 1000base-T control register */ 77 MV_AN_STAT1000 = 0x8001, /* 1000base-T status register */ 78 79 /* Vendor2 MMD registers */ 80 MV_V2_PORT_CTRL = 0xf001, 81 MV_V2_PORT_CTRL_SWRST = BIT(15), 82 MV_V2_PORT_CTRL_PWRDOWN = BIT(11), 83 /* Temperature control/read registers (88X3310 only) */ 84 MV_V2_TEMP_CTRL = 0xf08a, 85 MV_V2_TEMP_CTRL_MASK = 0xc000, 86 MV_V2_TEMP_CTRL_SAMPLE = 0x0000, 87 MV_V2_TEMP_CTRL_DISABLE = 0xc000, 88 MV_V2_TEMP = 0xf08c, 89 MV_V2_TEMP_UNKNOWN = 0x9600, /* unknown function */ 90 }; 91 92 struct mv3310_priv { 93 u32 firmware_ver; 94 95 struct device *hwmon_dev; 96 char *hwmon_name; 97 }; 98 99 #ifdef CONFIG_HWMON 100 static umode_t mv3310_hwmon_is_visible(const void *data, 101 enum hwmon_sensor_types type, 102 u32 attr, int channel) 103 { 104 if (type == hwmon_chip && attr == hwmon_chip_update_interval) 105 return 0444; 106 if (type == hwmon_temp && attr == hwmon_temp_input) 107 return 0444; 108 return 0; 109 } 110 111 static int mv3310_hwmon_read_temp_reg(struct phy_device *phydev) 112 { 113 return phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP); 114 } 115 116 static int mv2110_hwmon_read_temp_reg(struct phy_device *phydev) 117 { 118 return phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_TEMP); 119 } 120 121 static int mv10g_hwmon_read_temp_reg(struct phy_device *phydev) 122 { 123 if (phydev->drv->phy_id == MARVELL_PHY_ID_88X3310) 124 return mv3310_hwmon_read_temp_reg(phydev); 125 else /* MARVELL_PHY_ID_88E2110 */ 126 return mv2110_hwmon_read_temp_reg(phydev); 127 } 128 129 static int mv3310_hwmon_read(struct device *dev, enum hwmon_sensor_types type, 130 u32 attr, int channel, long *value) 131 { 132 struct phy_device *phydev = dev_get_drvdata(dev); 133 int temp; 134 135 if (type == hwmon_chip && attr == hwmon_chip_update_interval) { 136 *value = MSEC_PER_SEC; 137 return 0; 138 } 139 140 if (type == hwmon_temp && attr == hwmon_temp_input) { 141 temp = mv10g_hwmon_read_temp_reg(phydev); 142 if (temp < 0) 143 return temp; 144 145 *value = ((temp & 0xff) - 75) * 1000; 146 147 return 0; 148 } 149 150 return -EOPNOTSUPP; 151 } 152 153 static const struct hwmon_ops mv3310_hwmon_ops = { 154 .is_visible = mv3310_hwmon_is_visible, 155 .read = mv3310_hwmon_read, 156 }; 157 158 static u32 mv3310_hwmon_chip_config[] = { 159 HWMON_C_REGISTER_TZ | HWMON_C_UPDATE_INTERVAL, 160 0, 161 }; 162 163 static const struct hwmon_channel_info mv3310_hwmon_chip = { 164 .type = hwmon_chip, 165 .config = mv3310_hwmon_chip_config, 166 }; 167 168 static u32 mv3310_hwmon_temp_config[] = { 169 HWMON_T_INPUT, 170 0, 171 }; 172 173 static const struct hwmon_channel_info mv3310_hwmon_temp = { 174 .type = hwmon_temp, 175 .config = mv3310_hwmon_temp_config, 176 }; 177 178 static const struct hwmon_channel_info *mv3310_hwmon_info[] = { 179 &mv3310_hwmon_chip, 180 &mv3310_hwmon_temp, 181 NULL, 182 }; 183 184 static const struct hwmon_chip_info mv3310_hwmon_chip_info = { 185 .ops = &mv3310_hwmon_ops, 186 .info = mv3310_hwmon_info, 187 }; 188 189 static int mv3310_hwmon_config(struct phy_device *phydev, bool enable) 190 { 191 u16 val; 192 int ret; 193 194 if (phydev->drv->phy_id != MARVELL_PHY_ID_88X3310) 195 return 0; 196 197 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP, 198 MV_V2_TEMP_UNKNOWN); 199 if (ret < 0) 200 return ret; 201 202 val = enable ? MV_V2_TEMP_CTRL_SAMPLE : MV_V2_TEMP_CTRL_DISABLE; 203 204 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP_CTRL, 205 MV_V2_TEMP_CTRL_MASK, val); 206 } 207 208 static void mv3310_hwmon_disable(void *data) 209 { 210 struct phy_device *phydev = data; 211 212 mv3310_hwmon_config(phydev, false); 213 } 214 215 static int mv3310_hwmon_probe(struct phy_device *phydev) 216 { 217 struct device *dev = &phydev->mdio.dev; 218 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); 219 int i, j, ret; 220 221 priv->hwmon_name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL); 222 if (!priv->hwmon_name) 223 return -ENODEV; 224 225 for (i = j = 0; priv->hwmon_name[i]; i++) { 226 if (isalnum(priv->hwmon_name[i])) { 227 if (i != j) 228 priv->hwmon_name[j] = priv->hwmon_name[i]; 229 j++; 230 } 231 } 232 priv->hwmon_name[j] = '\0'; 233 234 ret = mv3310_hwmon_config(phydev, true); 235 if (ret) 236 return ret; 237 238 ret = devm_add_action_or_reset(dev, mv3310_hwmon_disable, phydev); 239 if (ret) 240 return ret; 241 242 priv->hwmon_dev = devm_hwmon_device_register_with_info(dev, 243 priv->hwmon_name, phydev, 244 &mv3310_hwmon_chip_info, NULL); 245 246 return PTR_ERR_OR_ZERO(priv->hwmon_dev); 247 } 248 #else 249 static inline int mv3310_hwmon_config(struct phy_device *phydev, bool enable) 250 { 251 return 0; 252 } 253 254 static int mv3310_hwmon_probe(struct phy_device *phydev) 255 { 256 return 0; 257 } 258 #endif 259 260 static int mv3310_power_down(struct phy_device *phydev) 261 { 262 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, 263 MV_V2_PORT_CTRL_PWRDOWN); 264 } 265 266 static int mv3310_power_up(struct phy_device *phydev) 267 { 268 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); 269 int ret; 270 271 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, 272 MV_V2_PORT_CTRL_PWRDOWN); 273 274 if (phydev->drv->phy_id != MARVELL_PHY_ID_88X3310 || 275 priv->firmware_ver < 0x00030000) 276 return ret; 277 278 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, 279 MV_V2_PORT_CTRL_SWRST); 280 } 281 282 static int mv3310_reset(struct phy_device *phydev, u32 unit) 283 { 284 int val, err; 285 286 err = phy_modify_mmd(phydev, MDIO_MMD_PCS, unit + MDIO_CTRL1, 287 MDIO_CTRL1_RESET, MDIO_CTRL1_RESET); 288 if (err < 0) 289 return err; 290 291 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_PCS, 292 unit + MDIO_CTRL1, val, 293 !(val & MDIO_CTRL1_RESET), 294 5000, 100000, true); 295 } 296 297 static int mv3310_get_edpd(struct phy_device *phydev, u16 *edpd) 298 { 299 int val; 300 301 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1); 302 if (val < 0) 303 return val; 304 305 switch (val & MV_PCS_CSCR1_ED_MASK) { 306 case MV_PCS_CSCR1_ED_NLP: 307 *edpd = 1000; 308 break; 309 case MV_PCS_CSCR1_ED_RX: 310 *edpd = ETHTOOL_PHY_EDPD_NO_TX; 311 break; 312 default: 313 *edpd = ETHTOOL_PHY_EDPD_DISABLE; 314 break; 315 } 316 return 0; 317 } 318 319 static int mv3310_set_edpd(struct phy_device *phydev, u16 edpd) 320 { 321 u16 val; 322 int err; 323 324 switch (edpd) { 325 case 1000: 326 case ETHTOOL_PHY_EDPD_DFLT_TX_MSECS: 327 val = MV_PCS_CSCR1_ED_NLP; 328 break; 329 330 case ETHTOOL_PHY_EDPD_NO_TX: 331 val = MV_PCS_CSCR1_ED_RX; 332 break; 333 334 case ETHTOOL_PHY_EDPD_DISABLE: 335 val = MV_PCS_CSCR1_ED_OFF; 336 break; 337 338 default: 339 return -EINVAL; 340 } 341 342 err = phy_modify_mmd_changed(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1, 343 MV_PCS_CSCR1_ED_MASK, val); 344 if (err > 0) 345 err = mv3310_reset(phydev, MV_PCS_BASE_T); 346 347 return err; 348 } 349 350 static int mv3310_sfp_insert(void *upstream, const struct sfp_eeprom_id *id) 351 { 352 struct phy_device *phydev = upstream; 353 __ETHTOOL_DECLARE_LINK_MODE_MASK(support) = { 0, }; 354 phy_interface_t iface; 355 356 sfp_parse_support(phydev->sfp_bus, id, support); 357 iface = sfp_select_interface(phydev->sfp_bus, support); 358 359 if (iface != PHY_INTERFACE_MODE_10GBASER) { 360 dev_err(&phydev->mdio.dev, "incompatible SFP module inserted\n"); 361 return -EINVAL; 362 } 363 return 0; 364 } 365 366 static const struct sfp_upstream_ops mv3310_sfp_ops = { 367 .attach = phy_sfp_attach, 368 .detach = phy_sfp_detach, 369 .module_insert = mv3310_sfp_insert, 370 }; 371 372 static int mv3310_probe(struct phy_device *phydev) 373 { 374 struct mv3310_priv *priv; 375 u32 mmd_mask = MDIO_DEVS_PMAPMD | MDIO_DEVS_AN; 376 int ret; 377 378 if (!phydev->is_c45 || 379 (phydev->c45_ids.devices_in_package & mmd_mask) != mmd_mask) 380 return -ENODEV; 381 382 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_BOOT); 383 if (ret < 0) 384 return ret; 385 386 if (ret & MV_PMA_BOOT_FATAL) { 387 dev_warn(&phydev->mdio.dev, 388 "PHY failed to boot firmware, status=%04x\n", ret); 389 return -ENODEV; 390 } 391 392 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); 393 if (!priv) 394 return -ENOMEM; 395 396 dev_set_drvdata(&phydev->mdio.dev, priv); 397 398 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_FW_VER0); 399 if (ret < 0) 400 return ret; 401 402 priv->firmware_ver = ret << 16; 403 404 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_FW_VER1); 405 if (ret < 0) 406 return ret; 407 408 priv->firmware_ver |= ret; 409 410 phydev_info(phydev, "Firmware version %u.%u.%u.%u\n", 411 priv->firmware_ver >> 24, (priv->firmware_ver >> 16) & 255, 412 (priv->firmware_ver >> 8) & 255, priv->firmware_ver & 255); 413 414 /* Powering down the port when not in use saves about 600mW */ 415 ret = mv3310_power_down(phydev); 416 if (ret) 417 return ret; 418 419 ret = mv3310_hwmon_probe(phydev); 420 if (ret) 421 return ret; 422 423 return phy_sfp_probe(phydev, &mv3310_sfp_ops); 424 } 425 426 static int mv3310_suspend(struct phy_device *phydev) 427 { 428 return mv3310_power_down(phydev); 429 } 430 431 static int mv3310_resume(struct phy_device *phydev) 432 { 433 int ret; 434 435 ret = mv3310_power_up(phydev); 436 if (ret) 437 return ret; 438 439 return mv3310_hwmon_config(phydev, true); 440 } 441 442 /* Some PHYs in the Alaska family such as the 88X3310 and the 88E2010 443 * don't set bit 14 in PMA Extended Abilities (1.11), although they do 444 * support 2.5GBASET and 5GBASET. For these models, we can still read their 445 * 2.5G/5G extended abilities register (1.21). We detect these models based on 446 * the PMA device identifier, with a mask matching models known to have this 447 * issue 448 */ 449 static bool mv3310_has_pma_ngbaset_quirk(struct phy_device *phydev) 450 { 451 if (!(phydev->c45_ids.devices_in_package & MDIO_DEVS_PMAPMD)) 452 return false; 453 454 /* Only some revisions of the 88X3310 family PMA seem to be impacted */ 455 return (phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] & 456 MV_PHY_ALASKA_NBT_QUIRK_MASK) == MV_PHY_ALASKA_NBT_QUIRK_REV; 457 } 458 459 static int mv3310_config_init(struct phy_device *phydev) 460 { 461 int err; 462 463 /* Check that the PHY interface type is compatible */ 464 if (phydev->interface != PHY_INTERFACE_MODE_SGMII && 465 phydev->interface != PHY_INTERFACE_MODE_2500BASEX && 466 phydev->interface != PHY_INTERFACE_MODE_XAUI && 467 phydev->interface != PHY_INTERFACE_MODE_RXAUI && 468 phydev->interface != PHY_INTERFACE_MODE_10GBASER) 469 return -ENODEV; 470 471 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; 472 473 /* Power up so reset works */ 474 err = mv3310_power_up(phydev); 475 if (err) 476 return err; 477 478 /* Enable EDPD mode - saving 600mW */ 479 return mv3310_set_edpd(phydev, ETHTOOL_PHY_EDPD_DFLT_TX_MSECS); 480 } 481 482 static int mv3310_get_features(struct phy_device *phydev) 483 { 484 int ret, val; 485 486 ret = genphy_c45_pma_read_abilities(phydev); 487 if (ret) 488 return ret; 489 490 if (mv3310_has_pma_ngbaset_quirk(phydev)) { 491 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, 492 MDIO_PMA_NG_EXTABLE); 493 if (val < 0) 494 return val; 495 496 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 497 phydev->supported, 498 val & MDIO_PMA_NG_EXTABLE_2_5GBT); 499 500 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 501 phydev->supported, 502 val & MDIO_PMA_NG_EXTABLE_5GBT); 503 } 504 505 return 0; 506 } 507 508 static int mv3310_config_mdix(struct phy_device *phydev) 509 { 510 u16 val; 511 int err; 512 513 switch (phydev->mdix_ctrl) { 514 case ETH_TP_MDI_AUTO: 515 val = MV_PCS_CSCR1_MDIX_AUTO; 516 break; 517 case ETH_TP_MDI_X: 518 val = MV_PCS_CSCR1_MDIX_MDIX; 519 break; 520 case ETH_TP_MDI: 521 val = MV_PCS_CSCR1_MDIX_MDI; 522 break; 523 default: 524 return -EINVAL; 525 } 526 527 err = phy_modify_mmd_changed(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1, 528 MV_PCS_CSCR1_MDIX_MASK, val); 529 if (err > 0) 530 err = mv3310_reset(phydev, MV_PCS_BASE_T); 531 532 return err; 533 } 534 535 static int mv3310_config_aneg(struct phy_device *phydev) 536 { 537 bool changed = false; 538 u16 reg; 539 int ret; 540 541 ret = mv3310_config_mdix(phydev); 542 if (ret < 0) 543 return ret; 544 545 if (phydev->autoneg == AUTONEG_DISABLE) 546 return genphy_c45_pma_setup_forced(phydev); 547 548 ret = genphy_c45_an_config_aneg(phydev); 549 if (ret < 0) 550 return ret; 551 if (ret > 0) 552 changed = true; 553 554 /* Clause 45 has no standardized support for 1000BaseT, therefore 555 * use vendor registers for this mode. 556 */ 557 reg = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising); 558 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MV_AN_CTRL1000, 559 ADVERTISE_1000FULL | ADVERTISE_1000HALF, reg); 560 if (ret < 0) 561 return ret; 562 if (ret > 0) 563 changed = true; 564 565 return genphy_c45_check_and_restart_aneg(phydev, changed); 566 } 567 568 static int mv3310_aneg_done(struct phy_device *phydev) 569 { 570 int val; 571 572 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1); 573 if (val < 0) 574 return val; 575 576 if (val & MDIO_STAT1_LSTATUS) 577 return 1; 578 579 return genphy_c45_aneg_done(phydev); 580 } 581 582 static void mv3310_update_interface(struct phy_device *phydev) 583 { 584 if ((phydev->interface == PHY_INTERFACE_MODE_SGMII || 585 phydev->interface == PHY_INTERFACE_MODE_2500BASEX || 586 phydev->interface == PHY_INTERFACE_MODE_10GBASER) && 587 phydev->link) { 588 /* The PHY automatically switches its serdes interface (and 589 * active PHYXS instance) between Cisco SGMII, 10GBase-R and 590 * 2500BaseX modes according to the speed. Florian suggests 591 * setting phydev->interface to communicate this to the MAC. 592 * Only do this if we are already in one of the above modes. 593 */ 594 switch (phydev->speed) { 595 case SPEED_10000: 596 phydev->interface = PHY_INTERFACE_MODE_10GBASER; 597 break; 598 case SPEED_2500: 599 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 600 break; 601 case SPEED_1000: 602 case SPEED_100: 603 case SPEED_10: 604 phydev->interface = PHY_INTERFACE_MODE_SGMII; 605 break; 606 default: 607 break; 608 } 609 } 610 } 611 612 /* 10GBASE-ER,LR,LRM,SR do not support autonegotiation. */ 613 static int mv3310_read_status_10gbaser(struct phy_device *phydev) 614 { 615 phydev->link = 1; 616 phydev->speed = SPEED_10000; 617 phydev->duplex = DUPLEX_FULL; 618 619 return 0; 620 } 621 622 static int mv3310_read_status_copper(struct phy_device *phydev) 623 { 624 int cssr1, speed, val; 625 626 val = genphy_c45_read_link(phydev); 627 if (val < 0) 628 return val; 629 630 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); 631 if (val < 0) 632 return val; 633 634 cssr1 = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_CSSR1); 635 if (cssr1 < 0) 636 return val; 637 638 /* If the link settings are not resolved, mark the link down */ 639 if (!(cssr1 & MV_PCS_CSSR1_RESOLVED)) { 640 phydev->link = 0; 641 return 0; 642 } 643 644 /* Read the copper link settings */ 645 speed = cssr1 & MV_PCS_CSSR1_SPD1_MASK; 646 if (speed == MV_PCS_CSSR1_SPD1_SPD2) 647 speed |= cssr1 & MV_PCS_CSSR1_SPD2_MASK; 648 649 switch (speed) { 650 case MV_PCS_CSSR1_SPD1_SPD2 | MV_PCS_CSSR1_SPD2_10000: 651 phydev->speed = SPEED_10000; 652 break; 653 654 case MV_PCS_CSSR1_SPD1_SPD2 | MV_PCS_CSSR1_SPD2_5000: 655 phydev->speed = SPEED_5000; 656 break; 657 658 case MV_PCS_CSSR1_SPD1_SPD2 | MV_PCS_CSSR1_SPD2_2500: 659 phydev->speed = SPEED_2500; 660 break; 661 662 case MV_PCS_CSSR1_SPD1_1000: 663 phydev->speed = SPEED_1000; 664 break; 665 666 case MV_PCS_CSSR1_SPD1_100: 667 phydev->speed = SPEED_100; 668 break; 669 670 case MV_PCS_CSSR1_SPD1_10: 671 phydev->speed = SPEED_10; 672 break; 673 } 674 675 phydev->duplex = cssr1 & MV_PCS_CSSR1_DUPLEX_FULL ? 676 DUPLEX_FULL : DUPLEX_HALF; 677 phydev->mdix = cssr1 & MV_PCS_CSSR1_MDIX ? 678 ETH_TP_MDI_X : ETH_TP_MDI; 679 680 if (val & MDIO_AN_STAT1_COMPLETE) { 681 val = genphy_c45_read_lpa(phydev); 682 if (val < 0) 683 return val; 684 685 /* Read the link partner's 1G advertisement */ 686 val = phy_read_mmd(phydev, MDIO_MMD_AN, MV_AN_STAT1000); 687 if (val < 0) 688 return val; 689 690 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val); 691 692 /* Update the pause status */ 693 phy_resolve_aneg_pause(phydev); 694 } 695 696 return 0; 697 } 698 699 static int mv3310_read_status(struct phy_device *phydev) 700 { 701 int err, val; 702 703 phydev->speed = SPEED_UNKNOWN; 704 phydev->duplex = DUPLEX_UNKNOWN; 705 linkmode_zero(phydev->lp_advertising); 706 phydev->link = 0; 707 phydev->pause = 0; 708 phydev->asym_pause = 0; 709 phydev->mdix = ETH_TP_MDI_INVALID; 710 711 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1); 712 if (val < 0) 713 return val; 714 715 if (val & MDIO_STAT1_LSTATUS) 716 err = mv3310_read_status_10gbaser(phydev); 717 else 718 err = mv3310_read_status_copper(phydev); 719 if (err < 0) 720 return err; 721 722 if (phydev->link) 723 mv3310_update_interface(phydev); 724 725 return 0; 726 } 727 728 static int mv3310_get_tunable(struct phy_device *phydev, 729 struct ethtool_tunable *tuna, void *data) 730 { 731 switch (tuna->id) { 732 case ETHTOOL_PHY_EDPD: 733 return mv3310_get_edpd(phydev, data); 734 default: 735 return -EOPNOTSUPP; 736 } 737 } 738 739 static int mv3310_set_tunable(struct phy_device *phydev, 740 struct ethtool_tunable *tuna, const void *data) 741 { 742 switch (tuna->id) { 743 case ETHTOOL_PHY_EDPD: 744 return mv3310_set_edpd(phydev, *(u16 *)data); 745 default: 746 return -EOPNOTSUPP; 747 } 748 } 749 750 static struct phy_driver mv3310_drivers[] = { 751 { 752 .phy_id = MARVELL_PHY_ID_88X3310, 753 .phy_id_mask = MARVELL_PHY_ID_MASK, 754 .name = "mv88x3310", 755 .get_features = mv3310_get_features, 756 .config_init = mv3310_config_init, 757 .probe = mv3310_probe, 758 .suspend = mv3310_suspend, 759 .resume = mv3310_resume, 760 .config_aneg = mv3310_config_aneg, 761 .aneg_done = mv3310_aneg_done, 762 .read_status = mv3310_read_status, 763 .get_tunable = mv3310_get_tunable, 764 .set_tunable = mv3310_set_tunable, 765 }, 766 { 767 .phy_id = MARVELL_PHY_ID_88E2110, 768 .phy_id_mask = MARVELL_PHY_ID_MASK, 769 .name = "mv88x2110", 770 .probe = mv3310_probe, 771 .suspend = mv3310_suspend, 772 .resume = mv3310_resume, 773 .config_init = mv3310_config_init, 774 .config_aneg = mv3310_config_aneg, 775 .aneg_done = mv3310_aneg_done, 776 .read_status = mv3310_read_status, 777 .get_tunable = mv3310_get_tunable, 778 .set_tunable = mv3310_set_tunable, 779 }, 780 }; 781 782 module_phy_driver(mv3310_drivers); 783 784 static struct mdio_device_id __maybe_unused mv3310_tbl[] = { 785 { MARVELL_PHY_ID_88X3310, MARVELL_PHY_ID_MASK }, 786 { MARVELL_PHY_ID_88E2110, MARVELL_PHY_ID_MASK }, 787 { }, 788 }; 789 MODULE_DEVICE_TABLE(mdio, mv3310_tbl); 790 MODULE_DESCRIPTION("Marvell Alaska X 10Gigabit Ethernet PHY driver (MV88X3310)"); 791 MODULE_LICENSE("GPL"); 792