1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Marvell 10G 88x3310 PHY driver 4 * 5 * Based upon the ID registers, this PHY appears to be a mixture of IPs 6 * from two different companies. 7 * 8 * There appears to be several different data paths through the PHY which 9 * are automatically managed by the PHY. The following has been determined 10 * via observation and experimentation for a setup using single-lane Serdes: 11 * 12 * SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G) 13 * 10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G) 14 * 10GBASE-KR PHYXS -- BASE-R PCS -- Fiber 15 * 16 * With XAUI, observation shows: 17 * 18 * XAUI PHYXS -- <appropriate PCS as above> 19 * 20 * and no switching of the host interface mode occurs. 21 * 22 * If both the fiber and copper ports are connected, the first to gain 23 * link takes priority and the other port is completely locked out. 24 */ 25 #include <linux/ctype.h> 26 #include <linux/delay.h> 27 #include <linux/hwmon.h> 28 #include <linux/marvell_phy.h> 29 #include <linux/phy.h> 30 #include <linux/sfp.h> 31 32 #define MV_PHY_ALASKA_NBT_QUIRK_MASK 0xfffffffe 33 #define MV_PHY_ALASKA_NBT_QUIRK_REV (MARVELL_PHY_ID_88X3310 | 0xa) 34 35 enum { 36 MV_PMA_FW_VER0 = 0xc011, 37 MV_PMA_FW_VER1 = 0xc012, 38 MV_PMA_21X0_PORT_CTRL = 0xc04a, 39 MV_PMA_21X0_PORT_CTRL_SWRST = BIT(15), 40 MV_PMA_21X0_PORT_CTRL_MACTYPE_MASK = 0x7, 41 MV_PMA_21X0_PORT_CTRL_MACTYPE_USXGMII = 0x0, 42 MV_PMA_2180_PORT_CTRL_MACTYPE_DXGMII = 0x1, 43 MV_PMA_2180_PORT_CTRL_MACTYPE_QXGMII = 0x2, 44 MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER = 0x4, 45 MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER_NO_SGMII_AN = 0x5, 46 MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH = 0x6, 47 MV_PMA_BOOT = 0xc050, 48 MV_PMA_BOOT_FATAL = BIT(0), 49 50 MV_PCS_BASE_T = 0x0000, 51 MV_PCS_BASE_R = 0x1000, 52 MV_PCS_1000BASEX = 0x2000, 53 54 MV_PCS_CSCR1 = 0x8000, 55 MV_PCS_CSCR1_ED_MASK = 0x0300, 56 MV_PCS_CSCR1_ED_OFF = 0x0000, 57 MV_PCS_CSCR1_ED_RX = 0x0200, 58 MV_PCS_CSCR1_ED_NLP = 0x0300, 59 MV_PCS_CSCR1_MDIX_MASK = 0x0060, 60 MV_PCS_CSCR1_MDIX_MDI = 0x0000, 61 MV_PCS_CSCR1_MDIX_MDIX = 0x0020, 62 MV_PCS_CSCR1_MDIX_AUTO = 0x0060, 63 64 MV_PCS_CSSR1 = 0x8008, 65 MV_PCS_CSSR1_SPD1_MASK = 0xc000, 66 MV_PCS_CSSR1_SPD1_SPD2 = 0xc000, 67 MV_PCS_CSSR1_SPD1_1000 = 0x8000, 68 MV_PCS_CSSR1_SPD1_100 = 0x4000, 69 MV_PCS_CSSR1_SPD1_10 = 0x0000, 70 MV_PCS_CSSR1_DUPLEX_FULL= BIT(13), 71 MV_PCS_CSSR1_RESOLVED = BIT(11), 72 MV_PCS_CSSR1_MDIX = BIT(6), 73 MV_PCS_CSSR1_SPD2_MASK = 0x000c, 74 MV_PCS_CSSR1_SPD2_5000 = 0x0008, 75 MV_PCS_CSSR1_SPD2_2500 = 0x0004, 76 MV_PCS_CSSR1_SPD2_10000 = 0x0000, 77 78 /* Temperature read register (88E2110 only) */ 79 MV_PCS_TEMP = 0x8042, 80 81 /* These registers appear at 0x800X and 0xa00X - the 0xa00X control 82 * registers appear to set themselves to the 0x800X when AN is 83 * restarted, but status registers appear readable from either. 84 */ 85 MV_AN_CTRL1000 = 0x8000, /* 1000base-T control register */ 86 MV_AN_STAT1000 = 0x8001, /* 1000base-T status register */ 87 88 /* Vendor2 MMD registers */ 89 MV_V2_PORT_CTRL = 0xf001, 90 MV_V2_PORT_CTRL_PWRDOWN = BIT(11), 91 MV_V2_33X0_PORT_CTRL_SWRST = BIT(15), 92 MV_V2_33X0_PORT_CTRL_MACTYPE_MASK = 0x7, 93 MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI = 0x0, 94 MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH = 0x1, 95 MV_V2_3340_PORT_CTRL_MACTYPE_RXAUI_NO_SGMII_AN = 0x1, 96 MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH = 0x2, 97 MV_V2_3310_PORT_CTRL_MACTYPE_XAUI = 0x3, 98 MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER = 0x4, 99 MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_NO_SGMII_AN = 0x5, 100 MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH = 0x6, 101 MV_V2_33X0_PORT_CTRL_MACTYPE_USXGMII = 0x7, 102 /* Temperature control/read registers (88X3310 only) */ 103 MV_V2_TEMP_CTRL = 0xf08a, 104 MV_V2_TEMP_CTRL_MASK = 0xc000, 105 MV_V2_TEMP_CTRL_SAMPLE = 0x0000, 106 MV_V2_TEMP_CTRL_DISABLE = 0xc000, 107 MV_V2_TEMP = 0xf08c, 108 MV_V2_TEMP_UNKNOWN = 0x9600, /* unknown function */ 109 }; 110 111 struct mv3310_chip { 112 void (*init_supported_interfaces)(unsigned long *mask); 113 int (*get_mactype)(struct phy_device *phydev); 114 int (*init_interface)(struct phy_device *phydev, int mactype); 115 116 #ifdef CONFIG_HWMON 117 int (*hwmon_read_temp_reg)(struct phy_device *phydev); 118 #endif 119 }; 120 121 struct mv3310_priv { 122 DECLARE_BITMAP(supported_interfaces, PHY_INTERFACE_MODE_MAX); 123 124 u32 firmware_ver; 125 bool rate_match; 126 phy_interface_t const_interface; 127 128 struct device *hwmon_dev; 129 char *hwmon_name; 130 }; 131 132 static const struct mv3310_chip *to_mv3310_chip(struct phy_device *phydev) 133 { 134 return phydev->drv->driver_data; 135 } 136 137 #ifdef CONFIG_HWMON 138 static umode_t mv3310_hwmon_is_visible(const void *data, 139 enum hwmon_sensor_types type, 140 u32 attr, int channel) 141 { 142 if (type == hwmon_chip && attr == hwmon_chip_update_interval) 143 return 0444; 144 if (type == hwmon_temp && attr == hwmon_temp_input) 145 return 0444; 146 return 0; 147 } 148 149 static int mv3310_hwmon_read_temp_reg(struct phy_device *phydev) 150 { 151 return phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP); 152 } 153 154 static int mv2110_hwmon_read_temp_reg(struct phy_device *phydev) 155 { 156 return phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_TEMP); 157 } 158 159 static int mv3310_hwmon_read(struct device *dev, enum hwmon_sensor_types type, 160 u32 attr, int channel, long *value) 161 { 162 struct phy_device *phydev = dev_get_drvdata(dev); 163 const struct mv3310_chip *chip = to_mv3310_chip(phydev); 164 int temp; 165 166 if (type == hwmon_chip && attr == hwmon_chip_update_interval) { 167 *value = MSEC_PER_SEC; 168 return 0; 169 } 170 171 if (type == hwmon_temp && attr == hwmon_temp_input) { 172 temp = chip->hwmon_read_temp_reg(phydev); 173 if (temp < 0) 174 return temp; 175 176 *value = ((temp & 0xff) - 75) * 1000; 177 178 return 0; 179 } 180 181 return -EOPNOTSUPP; 182 } 183 184 static const struct hwmon_ops mv3310_hwmon_ops = { 185 .is_visible = mv3310_hwmon_is_visible, 186 .read = mv3310_hwmon_read, 187 }; 188 189 static u32 mv3310_hwmon_chip_config[] = { 190 HWMON_C_REGISTER_TZ | HWMON_C_UPDATE_INTERVAL, 191 0, 192 }; 193 194 static const struct hwmon_channel_info mv3310_hwmon_chip = { 195 .type = hwmon_chip, 196 .config = mv3310_hwmon_chip_config, 197 }; 198 199 static u32 mv3310_hwmon_temp_config[] = { 200 HWMON_T_INPUT, 201 0, 202 }; 203 204 static const struct hwmon_channel_info mv3310_hwmon_temp = { 205 .type = hwmon_temp, 206 .config = mv3310_hwmon_temp_config, 207 }; 208 209 static const struct hwmon_channel_info *mv3310_hwmon_info[] = { 210 &mv3310_hwmon_chip, 211 &mv3310_hwmon_temp, 212 NULL, 213 }; 214 215 static const struct hwmon_chip_info mv3310_hwmon_chip_info = { 216 .ops = &mv3310_hwmon_ops, 217 .info = mv3310_hwmon_info, 218 }; 219 220 static int mv3310_hwmon_config(struct phy_device *phydev, bool enable) 221 { 222 u16 val; 223 int ret; 224 225 if (phydev->drv->phy_id != MARVELL_PHY_ID_88X3310) 226 return 0; 227 228 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP, 229 MV_V2_TEMP_UNKNOWN); 230 if (ret < 0) 231 return ret; 232 233 val = enable ? MV_V2_TEMP_CTRL_SAMPLE : MV_V2_TEMP_CTRL_DISABLE; 234 235 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP_CTRL, 236 MV_V2_TEMP_CTRL_MASK, val); 237 } 238 239 static int mv3310_hwmon_probe(struct phy_device *phydev) 240 { 241 struct device *dev = &phydev->mdio.dev; 242 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); 243 int i, j, ret; 244 245 priv->hwmon_name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL); 246 if (!priv->hwmon_name) 247 return -ENODEV; 248 249 for (i = j = 0; priv->hwmon_name[i]; i++) { 250 if (isalnum(priv->hwmon_name[i])) { 251 if (i != j) 252 priv->hwmon_name[j] = priv->hwmon_name[i]; 253 j++; 254 } 255 } 256 priv->hwmon_name[j] = '\0'; 257 258 ret = mv3310_hwmon_config(phydev, true); 259 if (ret) 260 return ret; 261 262 priv->hwmon_dev = devm_hwmon_device_register_with_info(dev, 263 priv->hwmon_name, phydev, 264 &mv3310_hwmon_chip_info, NULL); 265 266 return PTR_ERR_OR_ZERO(priv->hwmon_dev); 267 } 268 #else 269 static inline int mv3310_hwmon_config(struct phy_device *phydev, bool enable) 270 { 271 return 0; 272 } 273 274 static int mv3310_hwmon_probe(struct phy_device *phydev) 275 { 276 return 0; 277 } 278 #endif 279 280 static int mv3310_power_down(struct phy_device *phydev) 281 { 282 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, 283 MV_V2_PORT_CTRL_PWRDOWN); 284 } 285 286 static int mv3310_power_up(struct phy_device *phydev) 287 { 288 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); 289 int ret; 290 291 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, 292 MV_V2_PORT_CTRL_PWRDOWN); 293 294 if (phydev->drv->phy_id != MARVELL_PHY_ID_88X3310 || 295 priv->firmware_ver < 0x00030000) 296 return ret; 297 298 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, 299 MV_V2_33X0_PORT_CTRL_SWRST); 300 } 301 302 static int mv3310_reset(struct phy_device *phydev, u32 unit) 303 { 304 int val, err; 305 306 err = phy_modify_mmd(phydev, MDIO_MMD_PCS, unit + MDIO_CTRL1, 307 MDIO_CTRL1_RESET, MDIO_CTRL1_RESET); 308 if (err < 0) 309 return err; 310 311 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_PCS, 312 unit + MDIO_CTRL1, val, 313 !(val & MDIO_CTRL1_RESET), 314 5000, 100000, true); 315 } 316 317 static int mv3310_get_edpd(struct phy_device *phydev, u16 *edpd) 318 { 319 int val; 320 321 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1); 322 if (val < 0) 323 return val; 324 325 switch (val & MV_PCS_CSCR1_ED_MASK) { 326 case MV_PCS_CSCR1_ED_NLP: 327 *edpd = 1000; 328 break; 329 case MV_PCS_CSCR1_ED_RX: 330 *edpd = ETHTOOL_PHY_EDPD_NO_TX; 331 break; 332 default: 333 *edpd = ETHTOOL_PHY_EDPD_DISABLE; 334 break; 335 } 336 return 0; 337 } 338 339 static int mv3310_set_edpd(struct phy_device *phydev, u16 edpd) 340 { 341 u16 val; 342 int err; 343 344 switch (edpd) { 345 case 1000: 346 case ETHTOOL_PHY_EDPD_DFLT_TX_MSECS: 347 val = MV_PCS_CSCR1_ED_NLP; 348 break; 349 350 case ETHTOOL_PHY_EDPD_NO_TX: 351 val = MV_PCS_CSCR1_ED_RX; 352 break; 353 354 case ETHTOOL_PHY_EDPD_DISABLE: 355 val = MV_PCS_CSCR1_ED_OFF; 356 break; 357 358 default: 359 return -EINVAL; 360 } 361 362 err = phy_modify_mmd_changed(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1, 363 MV_PCS_CSCR1_ED_MASK, val); 364 if (err > 0) 365 err = mv3310_reset(phydev, MV_PCS_BASE_T); 366 367 return err; 368 } 369 370 static int mv3310_sfp_insert(void *upstream, const struct sfp_eeprom_id *id) 371 { 372 struct phy_device *phydev = upstream; 373 __ETHTOOL_DECLARE_LINK_MODE_MASK(support) = { 0, }; 374 phy_interface_t iface; 375 376 sfp_parse_support(phydev->sfp_bus, id, support); 377 iface = sfp_select_interface(phydev->sfp_bus, support); 378 379 if (iface != PHY_INTERFACE_MODE_10GBASER) { 380 dev_err(&phydev->mdio.dev, "incompatible SFP module inserted\n"); 381 return -EINVAL; 382 } 383 return 0; 384 } 385 386 static const struct sfp_upstream_ops mv3310_sfp_ops = { 387 .attach = phy_sfp_attach, 388 .detach = phy_sfp_detach, 389 .module_insert = mv3310_sfp_insert, 390 }; 391 392 static int mv3310_probe(struct phy_device *phydev) 393 { 394 const struct mv3310_chip *chip = to_mv3310_chip(phydev); 395 struct mv3310_priv *priv; 396 u32 mmd_mask = MDIO_DEVS_PMAPMD | MDIO_DEVS_AN; 397 int ret; 398 399 if (!phydev->is_c45 || 400 (phydev->c45_ids.devices_in_package & mmd_mask) != mmd_mask) 401 return -ENODEV; 402 403 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_BOOT); 404 if (ret < 0) 405 return ret; 406 407 if (ret & MV_PMA_BOOT_FATAL) { 408 dev_warn(&phydev->mdio.dev, 409 "PHY failed to boot firmware, status=%04x\n", ret); 410 return -ENODEV; 411 } 412 413 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); 414 if (!priv) 415 return -ENOMEM; 416 417 dev_set_drvdata(&phydev->mdio.dev, priv); 418 419 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_FW_VER0); 420 if (ret < 0) 421 return ret; 422 423 priv->firmware_ver = ret << 16; 424 425 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_FW_VER1); 426 if (ret < 0) 427 return ret; 428 429 priv->firmware_ver |= ret; 430 431 phydev_info(phydev, "Firmware version %u.%u.%u.%u\n", 432 priv->firmware_ver >> 24, (priv->firmware_ver >> 16) & 255, 433 (priv->firmware_ver >> 8) & 255, priv->firmware_ver & 255); 434 435 /* Powering down the port when not in use saves about 600mW */ 436 ret = mv3310_power_down(phydev); 437 if (ret) 438 return ret; 439 440 ret = mv3310_hwmon_probe(phydev); 441 if (ret) 442 return ret; 443 444 chip->init_supported_interfaces(priv->supported_interfaces); 445 446 return phy_sfp_probe(phydev, &mv3310_sfp_ops); 447 } 448 449 static void mv3310_remove(struct phy_device *phydev) 450 { 451 mv3310_hwmon_config(phydev, false); 452 } 453 454 static int mv3310_suspend(struct phy_device *phydev) 455 { 456 return mv3310_power_down(phydev); 457 } 458 459 static int mv3310_resume(struct phy_device *phydev) 460 { 461 int ret; 462 463 ret = mv3310_power_up(phydev); 464 if (ret) 465 return ret; 466 467 return mv3310_hwmon_config(phydev, true); 468 } 469 470 /* Some PHYs in the Alaska family such as the 88X3310 and the 88E2010 471 * don't set bit 14 in PMA Extended Abilities (1.11), although they do 472 * support 2.5GBASET and 5GBASET. For these models, we can still read their 473 * 2.5G/5G extended abilities register (1.21). We detect these models based on 474 * the PMA device identifier, with a mask matching models known to have this 475 * issue 476 */ 477 static bool mv3310_has_pma_ngbaset_quirk(struct phy_device *phydev) 478 { 479 if (!(phydev->c45_ids.devices_in_package & MDIO_DEVS_PMAPMD)) 480 return false; 481 482 /* Only some revisions of the 88X3310 family PMA seem to be impacted */ 483 return (phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] & 484 MV_PHY_ALASKA_NBT_QUIRK_MASK) == MV_PHY_ALASKA_NBT_QUIRK_REV; 485 } 486 487 static int mv2110_get_mactype(struct phy_device *phydev) 488 { 489 int mactype; 490 491 mactype = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_21X0_PORT_CTRL); 492 if (mactype < 0) 493 return mactype; 494 495 return mactype & MV_PMA_21X0_PORT_CTRL_MACTYPE_MASK; 496 } 497 498 static int mv3310_get_mactype(struct phy_device *phydev) 499 { 500 int mactype; 501 502 mactype = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL); 503 if (mactype < 0) 504 return mactype; 505 506 return mactype & MV_V2_33X0_PORT_CTRL_MACTYPE_MASK; 507 } 508 509 static int mv2110_init_interface(struct phy_device *phydev, int mactype) 510 { 511 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); 512 513 priv->rate_match = false; 514 515 if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH) 516 priv->rate_match = true; 517 518 if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_USXGMII) 519 priv->const_interface = PHY_INTERFACE_MODE_USXGMII; 520 else if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH) 521 priv->const_interface = PHY_INTERFACE_MODE_10GBASER; 522 else if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER || 523 mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER_NO_SGMII_AN) 524 priv->const_interface = PHY_INTERFACE_MODE_NA; 525 else 526 return -EINVAL; 527 528 return 0; 529 } 530 531 static int mv3310_init_interface(struct phy_device *phydev, int mactype) 532 { 533 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); 534 535 priv->rate_match = false; 536 537 if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH || 538 mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH || 539 mactype == MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH) 540 priv->rate_match = true; 541 542 if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_USXGMII) 543 priv->const_interface = PHY_INTERFACE_MODE_USXGMII; 544 else if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH || 545 mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_NO_SGMII_AN || 546 mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER) 547 priv->const_interface = PHY_INTERFACE_MODE_10GBASER; 548 else if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH || 549 mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI) 550 priv->const_interface = PHY_INTERFACE_MODE_RXAUI; 551 else if (mactype == MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH || 552 mactype == MV_V2_3310_PORT_CTRL_MACTYPE_XAUI) 553 priv->const_interface = PHY_INTERFACE_MODE_XAUI; 554 else 555 return -EINVAL; 556 557 return 0; 558 } 559 560 static int mv3340_init_interface(struct phy_device *phydev, int mactype) 561 { 562 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); 563 int err = 0; 564 565 priv->rate_match = false; 566 567 if (mactype == MV_V2_3340_PORT_CTRL_MACTYPE_RXAUI_NO_SGMII_AN) 568 priv->const_interface = PHY_INTERFACE_MODE_RXAUI; 569 else 570 err = mv3310_init_interface(phydev, mactype); 571 572 return err; 573 } 574 575 static int mv3310_config_init(struct phy_device *phydev) 576 { 577 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); 578 const struct mv3310_chip *chip = to_mv3310_chip(phydev); 579 int err, mactype; 580 581 /* Check that the PHY interface type is compatible */ 582 if (!test_bit(phydev->interface, priv->supported_interfaces)) 583 return -ENODEV; 584 585 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; 586 587 /* Power up so reset works */ 588 err = mv3310_power_up(phydev); 589 if (err) 590 return err; 591 592 mactype = chip->get_mactype(phydev); 593 if (mactype < 0) 594 return mactype; 595 596 err = chip->init_interface(phydev, mactype); 597 if (err) { 598 phydev_err(phydev, "MACTYPE configuration invalid\n"); 599 return err; 600 } 601 602 /* Enable EDPD mode - saving 600mW */ 603 return mv3310_set_edpd(phydev, ETHTOOL_PHY_EDPD_DFLT_TX_MSECS); 604 } 605 606 static int mv3310_get_features(struct phy_device *phydev) 607 { 608 int ret, val; 609 610 ret = genphy_c45_pma_read_abilities(phydev); 611 if (ret) 612 return ret; 613 614 if (mv3310_has_pma_ngbaset_quirk(phydev)) { 615 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, 616 MDIO_PMA_NG_EXTABLE); 617 if (val < 0) 618 return val; 619 620 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 621 phydev->supported, 622 val & MDIO_PMA_NG_EXTABLE_2_5GBT); 623 624 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 625 phydev->supported, 626 val & MDIO_PMA_NG_EXTABLE_5GBT); 627 } 628 629 return 0; 630 } 631 632 static int mv3310_config_mdix(struct phy_device *phydev) 633 { 634 u16 val; 635 int err; 636 637 switch (phydev->mdix_ctrl) { 638 case ETH_TP_MDI_AUTO: 639 val = MV_PCS_CSCR1_MDIX_AUTO; 640 break; 641 case ETH_TP_MDI_X: 642 val = MV_PCS_CSCR1_MDIX_MDIX; 643 break; 644 case ETH_TP_MDI: 645 val = MV_PCS_CSCR1_MDIX_MDI; 646 break; 647 default: 648 return -EINVAL; 649 } 650 651 err = phy_modify_mmd_changed(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1, 652 MV_PCS_CSCR1_MDIX_MASK, val); 653 if (err > 0) 654 err = mv3310_reset(phydev, MV_PCS_BASE_T); 655 656 return err; 657 } 658 659 static int mv3310_config_aneg(struct phy_device *phydev) 660 { 661 bool changed = false; 662 u16 reg; 663 int ret; 664 665 ret = mv3310_config_mdix(phydev); 666 if (ret < 0) 667 return ret; 668 669 if (phydev->autoneg == AUTONEG_DISABLE) 670 return genphy_c45_pma_setup_forced(phydev); 671 672 ret = genphy_c45_an_config_aneg(phydev); 673 if (ret < 0) 674 return ret; 675 if (ret > 0) 676 changed = true; 677 678 /* Clause 45 has no standardized support for 1000BaseT, therefore 679 * use vendor registers for this mode. 680 */ 681 reg = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising); 682 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MV_AN_CTRL1000, 683 ADVERTISE_1000FULL | ADVERTISE_1000HALF, reg); 684 if (ret < 0) 685 return ret; 686 if (ret > 0) 687 changed = true; 688 689 return genphy_c45_check_and_restart_aneg(phydev, changed); 690 } 691 692 static int mv3310_aneg_done(struct phy_device *phydev) 693 { 694 int val; 695 696 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1); 697 if (val < 0) 698 return val; 699 700 if (val & MDIO_STAT1_LSTATUS) 701 return 1; 702 703 return genphy_c45_aneg_done(phydev); 704 } 705 706 static void mv3310_update_interface(struct phy_device *phydev) 707 { 708 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); 709 710 if (!phydev->link) 711 return; 712 713 /* In all of the "* with Rate Matching" modes the PHY interface is fixed 714 * at 10Gb. The PHY adapts the rate to actual wire speed with help of 715 * internal 16KB buffer. 716 * 717 * In USXGMII mode the PHY interface mode is also fixed. 718 */ 719 if (priv->rate_match || 720 priv->const_interface == PHY_INTERFACE_MODE_USXGMII) { 721 phydev->interface = priv->const_interface; 722 return; 723 } 724 725 /* The PHY automatically switches its serdes interface (and active PHYXS 726 * instance) between Cisco SGMII, 2500BaseX, 5GBase-R and 10GBase-R / 727 * xaui / rxaui modes according to the speed. 728 * Florian suggests setting phydev->interface to communicate this to the 729 * MAC. Only do this if we are already in one of the above modes. 730 */ 731 switch (phydev->speed) { 732 case SPEED_10000: 733 phydev->interface = priv->const_interface; 734 break; 735 case SPEED_5000: 736 phydev->interface = PHY_INTERFACE_MODE_5GBASER; 737 break; 738 case SPEED_2500: 739 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 740 break; 741 case SPEED_1000: 742 case SPEED_100: 743 case SPEED_10: 744 phydev->interface = PHY_INTERFACE_MODE_SGMII; 745 break; 746 default: 747 break; 748 } 749 } 750 751 /* 10GBASE-ER,LR,LRM,SR do not support autonegotiation. */ 752 static int mv3310_read_status_10gbaser(struct phy_device *phydev) 753 { 754 phydev->link = 1; 755 phydev->speed = SPEED_10000; 756 phydev->duplex = DUPLEX_FULL; 757 phydev->port = PORT_FIBRE; 758 759 return 0; 760 } 761 762 static int mv3310_read_status_copper(struct phy_device *phydev) 763 { 764 int cssr1, speed, val; 765 766 val = genphy_c45_read_link(phydev); 767 if (val < 0) 768 return val; 769 770 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); 771 if (val < 0) 772 return val; 773 774 cssr1 = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_CSSR1); 775 if (cssr1 < 0) 776 return val; 777 778 /* If the link settings are not resolved, mark the link down */ 779 if (!(cssr1 & MV_PCS_CSSR1_RESOLVED)) { 780 phydev->link = 0; 781 return 0; 782 } 783 784 /* Read the copper link settings */ 785 speed = cssr1 & MV_PCS_CSSR1_SPD1_MASK; 786 if (speed == MV_PCS_CSSR1_SPD1_SPD2) 787 speed |= cssr1 & MV_PCS_CSSR1_SPD2_MASK; 788 789 switch (speed) { 790 case MV_PCS_CSSR1_SPD1_SPD2 | MV_PCS_CSSR1_SPD2_10000: 791 phydev->speed = SPEED_10000; 792 break; 793 794 case MV_PCS_CSSR1_SPD1_SPD2 | MV_PCS_CSSR1_SPD2_5000: 795 phydev->speed = SPEED_5000; 796 break; 797 798 case MV_PCS_CSSR1_SPD1_SPD2 | MV_PCS_CSSR1_SPD2_2500: 799 phydev->speed = SPEED_2500; 800 break; 801 802 case MV_PCS_CSSR1_SPD1_1000: 803 phydev->speed = SPEED_1000; 804 break; 805 806 case MV_PCS_CSSR1_SPD1_100: 807 phydev->speed = SPEED_100; 808 break; 809 810 case MV_PCS_CSSR1_SPD1_10: 811 phydev->speed = SPEED_10; 812 break; 813 } 814 815 phydev->duplex = cssr1 & MV_PCS_CSSR1_DUPLEX_FULL ? 816 DUPLEX_FULL : DUPLEX_HALF; 817 phydev->port = PORT_TP; 818 phydev->mdix = cssr1 & MV_PCS_CSSR1_MDIX ? 819 ETH_TP_MDI_X : ETH_TP_MDI; 820 821 if (val & MDIO_AN_STAT1_COMPLETE) { 822 val = genphy_c45_read_lpa(phydev); 823 if (val < 0) 824 return val; 825 826 /* Read the link partner's 1G advertisement */ 827 val = phy_read_mmd(phydev, MDIO_MMD_AN, MV_AN_STAT1000); 828 if (val < 0) 829 return val; 830 831 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val); 832 833 /* Update the pause status */ 834 phy_resolve_aneg_pause(phydev); 835 } 836 837 return 0; 838 } 839 840 static int mv3310_read_status(struct phy_device *phydev) 841 { 842 int err, val; 843 844 phydev->speed = SPEED_UNKNOWN; 845 phydev->duplex = DUPLEX_UNKNOWN; 846 linkmode_zero(phydev->lp_advertising); 847 phydev->link = 0; 848 phydev->pause = 0; 849 phydev->asym_pause = 0; 850 phydev->mdix = ETH_TP_MDI_INVALID; 851 852 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1); 853 if (val < 0) 854 return val; 855 856 if (val & MDIO_STAT1_LSTATUS) 857 err = mv3310_read_status_10gbaser(phydev); 858 else 859 err = mv3310_read_status_copper(phydev); 860 if (err < 0) 861 return err; 862 863 if (phydev->link) 864 mv3310_update_interface(phydev); 865 866 return 0; 867 } 868 869 static int mv3310_get_tunable(struct phy_device *phydev, 870 struct ethtool_tunable *tuna, void *data) 871 { 872 switch (tuna->id) { 873 case ETHTOOL_PHY_EDPD: 874 return mv3310_get_edpd(phydev, data); 875 default: 876 return -EOPNOTSUPP; 877 } 878 } 879 880 static int mv3310_set_tunable(struct phy_device *phydev, 881 struct ethtool_tunable *tuna, const void *data) 882 { 883 switch (tuna->id) { 884 case ETHTOOL_PHY_EDPD: 885 return mv3310_set_edpd(phydev, *(u16 *)data); 886 default: 887 return -EOPNOTSUPP; 888 } 889 } 890 891 static void mv3310_init_supported_interfaces(unsigned long *mask) 892 { 893 __set_bit(PHY_INTERFACE_MODE_SGMII, mask); 894 __set_bit(PHY_INTERFACE_MODE_2500BASEX, mask); 895 __set_bit(PHY_INTERFACE_MODE_5GBASER, mask); 896 __set_bit(PHY_INTERFACE_MODE_XAUI, mask); 897 __set_bit(PHY_INTERFACE_MODE_RXAUI, mask); 898 __set_bit(PHY_INTERFACE_MODE_10GBASER, mask); 899 __set_bit(PHY_INTERFACE_MODE_USXGMII, mask); 900 } 901 902 static void mv3340_init_supported_interfaces(unsigned long *mask) 903 { 904 __set_bit(PHY_INTERFACE_MODE_SGMII, mask); 905 __set_bit(PHY_INTERFACE_MODE_2500BASEX, mask); 906 __set_bit(PHY_INTERFACE_MODE_5GBASER, mask); 907 __set_bit(PHY_INTERFACE_MODE_RXAUI, mask); 908 __set_bit(PHY_INTERFACE_MODE_10GBASER, mask); 909 __set_bit(PHY_INTERFACE_MODE_USXGMII, mask); 910 } 911 912 static void mv2110_init_supported_interfaces(unsigned long *mask) 913 { 914 __set_bit(PHY_INTERFACE_MODE_SGMII, mask); 915 __set_bit(PHY_INTERFACE_MODE_2500BASEX, mask); 916 __set_bit(PHY_INTERFACE_MODE_5GBASER, mask); 917 __set_bit(PHY_INTERFACE_MODE_10GBASER, mask); 918 __set_bit(PHY_INTERFACE_MODE_USXGMII, mask); 919 } 920 921 static void mv2111_init_supported_interfaces(unsigned long *mask) 922 { 923 __set_bit(PHY_INTERFACE_MODE_SGMII, mask); 924 __set_bit(PHY_INTERFACE_MODE_2500BASEX, mask); 925 __set_bit(PHY_INTERFACE_MODE_10GBASER, mask); 926 __set_bit(PHY_INTERFACE_MODE_USXGMII, mask); 927 } 928 929 static const struct mv3310_chip mv3310_type = { 930 .init_supported_interfaces = mv3310_init_supported_interfaces, 931 .get_mactype = mv3310_get_mactype, 932 .init_interface = mv3310_init_interface, 933 934 #ifdef CONFIG_HWMON 935 .hwmon_read_temp_reg = mv3310_hwmon_read_temp_reg, 936 #endif 937 }; 938 939 static const struct mv3310_chip mv3340_type = { 940 .init_supported_interfaces = mv3340_init_supported_interfaces, 941 .get_mactype = mv3310_get_mactype, 942 .init_interface = mv3340_init_interface, 943 944 #ifdef CONFIG_HWMON 945 .hwmon_read_temp_reg = mv3310_hwmon_read_temp_reg, 946 #endif 947 }; 948 949 static const struct mv3310_chip mv2110_type = { 950 .init_supported_interfaces = mv2110_init_supported_interfaces, 951 .get_mactype = mv2110_get_mactype, 952 .init_interface = mv2110_init_interface, 953 954 #ifdef CONFIG_HWMON 955 .hwmon_read_temp_reg = mv2110_hwmon_read_temp_reg, 956 #endif 957 }; 958 959 static const struct mv3310_chip mv2111_type = { 960 .init_supported_interfaces = mv2111_init_supported_interfaces, 961 .get_mactype = mv2110_get_mactype, 962 .init_interface = mv2110_init_interface, 963 964 #ifdef CONFIG_HWMON 965 .hwmon_read_temp_reg = mv2110_hwmon_read_temp_reg, 966 #endif 967 }; 968 969 static int mv211x_match_phy_device(struct phy_device *phydev, bool has_5g) 970 { 971 int val; 972 973 if ((phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] & 974 MARVELL_PHY_ID_MASK) != MARVELL_PHY_ID_88E2110) 975 return 0; 976 977 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_SPEED); 978 if (val < 0) 979 return val; 980 981 return !!(val & MDIO_PCS_SPEED_5G) == has_5g; 982 } 983 984 static int mv2110_match_phy_device(struct phy_device *phydev) 985 { 986 return mv211x_match_phy_device(phydev, true); 987 } 988 989 static int mv2111_match_phy_device(struct phy_device *phydev) 990 { 991 return mv211x_match_phy_device(phydev, false); 992 } 993 994 static struct phy_driver mv3310_drivers[] = { 995 { 996 .phy_id = MARVELL_PHY_ID_88X3310, 997 .phy_id_mask = MARVELL_PHY_ID_88X33X0_MASK, 998 .name = "mv88x3310", 999 .driver_data = &mv3310_type, 1000 .get_features = mv3310_get_features, 1001 .config_init = mv3310_config_init, 1002 .probe = mv3310_probe, 1003 .suspend = mv3310_suspend, 1004 .resume = mv3310_resume, 1005 .config_aneg = mv3310_config_aneg, 1006 .aneg_done = mv3310_aneg_done, 1007 .read_status = mv3310_read_status, 1008 .get_tunable = mv3310_get_tunable, 1009 .set_tunable = mv3310_set_tunable, 1010 .remove = mv3310_remove, 1011 .set_loopback = genphy_c45_loopback, 1012 }, 1013 { 1014 .phy_id = MARVELL_PHY_ID_88X3340, 1015 .phy_id_mask = MARVELL_PHY_ID_88X33X0_MASK, 1016 .name = "mv88x3340", 1017 .driver_data = &mv3340_type, 1018 .get_features = mv3310_get_features, 1019 .config_init = mv3310_config_init, 1020 .probe = mv3310_probe, 1021 .suspend = mv3310_suspend, 1022 .resume = mv3310_resume, 1023 .config_aneg = mv3310_config_aneg, 1024 .aneg_done = mv3310_aneg_done, 1025 .read_status = mv3310_read_status, 1026 .get_tunable = mv3310_get_tunable, 1027 .set_tunable = mv3310_set_tunable, 1028 .remove = mv3310_remove, 1029 .set_loopback = genphy_c45_loopback, 1030 }, 1031 { 1032 .phy_id = MARVELL_PHY_ID_88E2110, 1033 .phy_id_mask = MARVELL_PHY_ID_MASK, 1034 .match_phy_device = mv2110_match_phy_device, 1035 .name = "mv88e2110", 1036 .driver_data = &mv2110_type, 1037 .probe = mv3310_probe, 1038 .suspend = mv3310_suspend, 1039 .resume = mv3310_resume, 1040 .config_init = mv3310_config_init, 1041 .config_aneg = mv3310_config_aneg, 1042 .aneg_done = mv3310_aneg_done, 1043 .read_status = mv3310_read_status, 1044 .get_tunable = mv3310_get_tunable, 1045 .set_tunable = mv3310_set_tunable, 1046 .remove = mv3310_remove, 1047 .set_loopback = genphy_c45_loopback, 1048 }, 1049 { 1050 .phy_id = MARVELL_PHY_ID_88E2110, 1051 .phy_id_mask = MARVELL_PHY_ID_MASK, 1052 .match_phy_device = mv2111_match_phy_device, 1053 .name = "mv88e2111", 1054 .driver_data = &mv2111_type, 1055 .probe = mv3310_probe, 1056 .suspend = mv3310_suspend, 1057 .resume = mv3310_resume, 1058 .config_init = mv3310_config_init, 1059 .config_aneg = mv3310_config_aneg, 1060 .aneg_done = mv3310_aneg_done, 1061 .read_status = mv3310_read_status, 1062 .get_tunable = mv3310_get_tunable, 1063 .set_tunable = mv3310_set_tunable, 1064 .remove = mv3310_remove, 1065 .set_loopback = genphy_c45_loopback, 1066 }, 1067 }; 1068 1069 module_phy_driver(mv3310_drivers); 1070 1071 static struct mdio_device_id __maybe_unused mv3310_tbl[] = { 1072 { MARVELL_PHY_ID_88X3310, MARVELL_PHY_ID_88X33X0_MASK }, 1073 { MARVELL_PHY_ID_88X3340, MARVELL_PHY_ID_88X33X0_MASK }, 1074 { MARVELL_PHY_ID_88E2110, MARVELL_PHY_ID_MASK }, 1075 { }, 1076 }; 1077 MODULE_DEVICE_TABLE(mdio, mv3310_tbl); 1078 MODULE_DESCRIPTION("Marvell Alaska X/M multi-gigabit Ethernet PHY driver"); 1079 MODULE_LICENSE("GPL"); 1080