1a2443fd1SAndrew Lunn // SPDX-License-Identifier: GPL-2.0+ 220b2af32SRussell King /* 320b2af32SRussell King * Marvell 10G 88x3310 PHY driver 420b2af32SRussell King * 520b2af32SRussell King * Based upon the ID registers, this PHY appears to be a mixture of IPs 620b2af32SRussell King * from two different companies. 720b2af32SRussell King * 820b2af32SRussell King * There appears to be several different data paths through the PHY which 920b2af32SRussell King * are automatically managed by the PHY. The following has been determined 1005ca1b32SRussell King * via observation and experimentation for a setup using single-lane Serdes: 1120b2af32SRussell King * 1220b2af32SRussell King * SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G) 1320b2af32SRussell King * 10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G) 1420b2af32SRussell King * 10GBASE-KR PHYXS -- BASE-R PCS -- Fiber 1520b2af32SRussell King * 1605ca1b32SRussell King * With XAUI, observation shows: 1705ca1b32SRussell King * 1805ca1b32SRussell King * XAUI PHYXS -- <appropriate PCS as above> 1905ca1b32SRussell King * 2005ca1b32SRussell King * and no switching of the host interface mode occurs. 2105ca1b32SRussell King * 2220b2af32SRussell King * If both the fiber and copper ports are connected, the first to gain 2320b2af32SRussell King * link takes priority and the other port is completely locked out. 2420b2af32SRussell King */ 250d3ad854SRussell King #include <linux/ctype.h> 268d8963c3SRussell King #include <linux/delay.h> 270d3ad854SRussell King #include <linux/hwmon.h> 28952b6b3bSAntoine Tenart #include <linux/marvell_phy.h> 290d3ad854SRussell King #include <linux/phy.h> 3036023da1SRussell King #include <linux/sfp.h> 3120b2af32SRussell King 32c47455f9SMaxime Chevallier #define MV_PHY_ALASKA_NBT_QUIRK_MASK 0xfffffffe 33c47455f9SMaxime Chevallier #define MV_PHY_ALASKA_NBT_QUIRK_REV (MARVELL_PHY_ID_88X3310 | 0xa) 34c47455f9SMaxime Chevallier 3520b2af32SRussell King enum { 36dd649b4fSRussell King MV_PMA_FW_VER0 = 0xc011, 37dd649b4fSRussell King MV_PMA_FW_VER1 = 0xc012, 383d3ced2eSRussell King MV_PMA_BOOT = 0xc050, 393d3ced2eSRussell King MV_PMA_BOOT_FATAL = BIT(0), 403d3ced2eSRussell King 4120b2af32SRussell King MV_PCS_BASE_T = 0x0000, 4220b2af32SRussell King MV_PCS_BASE_R = 0x1000, 4320b2af32SRussell King MV_PCS_1000BASEX = 0x2000, 4420b2af32SRussell King 458d8963c3SRussell King MV_PCS_CSCR1 = 0x8000, 46a585c03eSRussell King MV_PCS_CSCR1_ED_MASK = 0x0300, 47a585c03eSRussell King MV_PCS_CSCR1_ED_OFF = 0x0000, 48a585c03eSRussell King MV_PCS_CSCR1_ED_RX = 0x0200, 49a585c03eSRussell King MV_PCS_CSCR1_ED_NLP = 0x0300, 508d8963c3SRussell King MV_PCS_CSCR1_MDIX_MASK = 0x0060, 518d8963c3SRussell King MV_PCS_CSCR1_MDIX_MDI = 0x0000, 528d8963c3SRussell King MV_PCS_CSCR1_MDIX_MDIX = 0x0020, 538d8963c3SRussell King MV_PCS_CSCR1_MDIX_AUTO = 0x0060, 548d8963c3SRussell King 55c84786faSRussell King MV_PCS_CSSR1 = 0x8008, 56c84786faSRussell King MV_PCS_CSSR1_SPD1_MASK = 0xc000, 57c84786faSRussell King MV_PCS_CSSR1_SPD1_SPD2 = 0xc000, 58c84786faSRussell King MV_PCS_CSSR1_SPD1_1000 = 0x8000, 59c84786faSRussell King MV_PCS_CSSR1_SPD1_100 = 0x4000, 60c84786faSRussell King MV_PCS_CSSR1_SPD1_10 = 0x0000, 61c84786faSRussell King MV_PCS_CSSR1_DUPLEX_FULL= BIT(13), 62c84786faSRussell King MV_PCS_CSSR1_RESOLVED = BIT(11), 63c84786faSRussell King MV_PCS_CSSR1_MDIX = BIT(6), 64c84786faSRussell King MV_PCS_CSSR1_SPD2_MASK = 0x000c, 65c84786faSRussell King MV_PCS_CSSR1_SPD2_5000 = 0x0008, 66c84786faSRussell King MV_PCS_CSSR1_SPD2_2500 = 0x0004, 67c84786faSRussell King MV_PCS_CSSR1_SPD2_10000 = 0x0000, 68ea4efe25SRussell King 69c3e302edSBaruch Siach /* Temperature read register (88E2110 only) */ 70c3e302edSBaruch Siach MV_PCS_TEMP = 0x8042, 71c3e302edSBaruch Siach 7220b2af32SRussell King /* These registers appear at 0x800X and 0xa00X - the 0xa00X control 7320b2af32SRussell King * registers appear to set themselves to the 0x800X when AN is 7420b2af32SRussell King * restarted, but status registers appear readable from either. 7520b2af32SRussell King */ 7620b2af32SRussell King MV_AN_CTRL1000 = 0x8000, /* 1000base-T control register */ 7720b2af32SRussell King MV_AN_STAT1000 = 0x8001, /* 1000base-T status register */ 780d3ad854SRussell King 790d3ad854SRussell King /* Vendor2 MMD registers */ 80af3e28cbSAntoine Tenart MV_V2_PORT_CTRL = 0xf001, 818f48c2acSRussell King MV_V2_PORT_CTRL_SWRST = BIT(15), 828f48c2acSRussell King MV_V2_PORT_CTRL_PWRDOWN = BIT(11), 83e1170333SBaruch Siach MV_V2_PORT_MAC_TYPE_MASK = 0x7, 84e1170333SBaruch Siach MV_V2_PORT_MAC_TYPE_RATE_MATCH = 0x6, 85c3e302edSBaruch Siach /* Temperature control/read registers (88X3310 only) */ 860d3ad854SRussell King MV_V2_TEMP_CTRL = 0xf08a, 870d3ad854SRussell King MV_V2_TEMP_CTRL_MASK = 0xc000, 880d3ad854SRussell King MV_V2_TEMP_CTRL_SAMPLE = 0x0000, 890d3ad854SRussell King MV_V2_TEMP_CTRL_DISABLE = 0xc000, 900d3ad854SRussell King MV_V2_TEMP = 0xf08c, 910d3ad854SRussell King MV_V2_TEMP_UNKNOWN = 0x9600, /* unknown function */ 920d3ad854SRussell King }; 930d3ad854SRussell King 940d3ad854SRussell King struct mv3310_priv { 95dd649b4fSRussell King u32 firmware_ver; 96e1170333SBaruch Siach bool rate_match; 97dd649b4fSRussell King 980d3ad854SRussell King struct device *hwmon_dev; 990d3ad854SRussell King char *hwmon_name; 10020b2af32SRussell King }; 10120b2af32SRussell King 1020d3ad854SRussell King #ifdef CONFIG_HWMON 1030d3ad854SRussell King static umode_t mv3310_hwmon_is_visible(const void *data, 1040d3ad854SRussell King enum hwmon_sensor_types type, 1050d3ad854SRussell King u32 attr, int channel) 1060d3ad854SRussell King { 1070d3ad854SRussell King if (type == hwmon_chip && attr == hwmon_chip_update_interval) 1080d3ad854SRussell King return 0444; 1090d3ad854SRussell King if (type == hwmon_temp && attr == hwmon_temp_input) 1100d3ad854SRussell King return 0444; 1110d3ad854SRussell King return 0; 1120d3ad854SRussell King } 1130d3ad854SRussell King 114c3e302edSBaruch Siach static int mv3310_hwmon_read_temp_reg(struct phy_device *phydev) 115c3e302edSBaruch Siach { 116c3e302edSBaruch Siach return phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP); 117c3e302edSBaruch Siach } 118c3e302edSBaruch Siach 119c3e302edSBaruch Siach static int mv2110_hwmon_read_temp_reg(struct phy_device *phydev) 120c3e302edSBaruch Siach { 121c3e302edSBaruch Siach return phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_TEMP); 122c3e302edSBaruch Siach } 123c3e302edSBaruch Siach 124c3e302edSBaruch Siach static int mv10g_hwmon_read_temp_reg(struct phy_device *phydev) 125c3e302edSBaruch Siach { 126c3e302edSBaruch Siach if (phydev->drv->phy_id == MARVELL_PHY_ID_88X3310) 127c3e302edSBaruch Siach return mv3310_hwmon_read_temp_reg(phydev); 128c3e302edSBaruch Siach else /* MARVELL_PHY_ID_88E2110 */ 129c3e302edSBaruch Siach return mv2110_hwmon_read_temp_reg(phydev); 130c3e302edSBaruch Siach } 131c3e302edSBaruch Siach 1320d3ad854SRussell King static int mv3310_hwmon_read(struct device *dev, enum hwmon_sensor_types type, 1330d3ad854SRussell King u32 attr, int channel, long *value) 1340d3ad854SRussell King { 1350d3ad854SRussell King struct phy_device *phydev = dev_get_drvdata(dev); 1360d3ad854SRussell King int temp; 1370d3ad854SRussell King 1380d3ad854SRussell King if (type == hwmon_chip && attr == hwmon_chip_update_interval) { 1390d3ad854SRussell King *value = MSEC_PER_SEC; 1400d3ad854SRussell King return 0; 1410d3ad854SRussell King } 1420d3ad854SRussell King 1430d3ad854SRussell King if (type == hwmon_temp && attr == hwmon_temp_input) { 144c3e302edSBaruch Siach temp = mv10g_hwmon_read_temp_reg(phydev); 1450d3ad854SRussell King if (temp < 0) 1460d3ad854SRussell King return temp; 1470d3ad854SRussell King 1480d3ad854SRussell King *value = ((temp & 0xff) - 75) * 1000; 1490d3ad854SRussell King 1500d3ad854SRussell King return 0; 1510d3ad854SRussell King } 1520d3ad854SRussell King 1530d3ad854SRussell King return -EOPNOTSUPP; 1540d3ad854SRussell King } 1550d3ad854SRussell King 1560d3ad854SRussell King static const struct hwmon_ops mv3310_hwmon_ops = { 1570d3ad854SRussell King .is_visible = mv3310_hwmon_is_visible, 1580d3ad854SRussell King .read = mv3310_hwmon_read, 1590d3ad854SRussell King }; 1600d3ad854SRussell King 1610d3ad854SRussell King static u32 mv3310_hwmon_chip_config[] = { 1620d3ad854SRussell King HWMON_C_REGISTER_TZ | HWMON_C_UPDATE_INTERVAL, 1630d3ad854SRussell King 0, 1640d3ad854SRussell King }; 1650d3ad854SRussell King 1660d3ad854SRussell King static const struct hwmon_channel_info mv3310_hwmon_chip = { 1670d3ad854SRussell King .type = hwmon_chip, 1680d3ad854SRussell King .config = mv3310_hwmon_chip_config, 1690d3ad854SRussell King }; 1700d3ad854SRussell King 1710d3ad854SRussell King static u32 mv3310_hwmon_temp_config[] = { 1720d3ad854SRussell King HWMON_T_INPUT, 1730d3ad854SRussell King 0, 1740d3ad854SRussell King }; 1750d3ad854SRussell King 1760d3ad854SRussell King static const struct hwmon_channel_info mv3310_hwmon_temp = { 1770d3ad854SRussell King .type = hwmon_temp, 1780d3ad854SRussell King .config = mv3310_hwmon_temp_config, 1790d3ad854SRussell King }; 1800d3ad854SRussell King 1810d3ad854SRussell King static const struct hwmon_channel_info *mv3310_hwmon_info[] = { 1820d3ad854SRussell King &mv3310_hwmon_chip, 1830d3ad854SRussell King &mv3310_hwmon_temp, 1840d3ad854SRussell King NULL, 1850d3ad854SRussell King }; 1860d3ad854SRussell King 1870d3ad854SRussell King static const struct hwmon_chip_info mv3310_hwmon_chip_info = { 1880d3ad854SRussell King .ops = &mv3310_hwmon_ops, 1890d3ad854SRussell King .info = mv3310_hwmon_info, 1900d3ad854SRussell King }; 1910d3ad854SRussell King 1920d3ad854SRussell King static int mv3310_hwmon_config(struct phy_device *phydev, bool enable) 1930d3ad854SRussell King { 1940d3ad854SRussell King u16 val; 1950d3ad854SRussell King int ret; 1960d3ad854SRussell King 197c3e302edSBaruch Siach if (phydev->drv->phy_id != MARVELL_PHY_ID_88X3310) 198c3e302edSBaruch Siach return 0; 199c3e302edSBaruch Siach 2000d3ad854SRussell King ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP, 2010d3ad854SRussell King MV_V2_TEMP_UNKNOWN); 2020d3ad854SRussell King if (ret < 0) 2030d3ad854SRussell King return ret; 2040d3ad854SRussell King 2050d3ad854SRussell King val = enable ? MV_V2_TEMP_CTRL_SAMPLE : MV_V2_TEMP_CTRL_DISABLE; 2060d3ad854SRussell King 207b06d8e5aSHeiner Kallweit return phy_modify_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP_CTRL, 208b06d8e5aSHeiner Kallweit MV_V2_TEMP_CTRL_MASK, val); 2090d3ad854SRussell King } 2100d3ad854SRussell King 2110d3ad854SRussell King static void mv3310_hwmon_disable(void *data) 2120d3ad854SRussell King { 2130d3ad854SRussell King struct phy_device *phydev = data; 2140d3ad854SRussell King 2150d3ad854SRussell King mv3310_hwmon_config(phydev, false); 2160d3ad854SRussell King } 2170d3ad854SRussell King 2180d3ad854SRussell King static int mv3310_hwmon_probe(struct phy_device *phydev) 2190d3ad854SRussell King { 2200d3ad854SRussell King struct device *dev = &phydev->mdio.dev; 2210d3ad854SRussell King struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); 2220d3ad854SRussell King int i, j, ret; 2230d3ad854SRussell King 2240d3ad854SRussell King priv->hwmon_name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL); 2250d3ad854SRussell King if (!priv->hwmon_name) 2260d3ad854SRussell King return -ENODEV; 2270d3ad854SRussell King 2280d3ad854SRussell King for (i = j = 0; priv->hwmon_name[i]; i++) { 2290d3ad854SRussell King if (isalnum(priv->hwmon_name[i])) { 2300d3ad854SRussell King if (i != j) 2310d3ad854SRussell King priv->hwmon_name[j] = priv->hwmon_name[i]; 2320d3ad854SRussell King j++; 2330d3ad854SRussell King } 2340d3ad854SRussell King } 2350d3ad854SRussell King priv->hwmon_name[j] = '\0'; 2360d3ad854SRussell King 2370d3ad854SRussell King ret = mv3310_hwmon_config(phydev, true); 2380d3ad854SRussell King if (ret) 2390d3ad854SRussell King return ret; 2400d3ad854SRussell King 2410d3ad854SRussell King ret = devm_add_action_or_reset(dev, mv3310_hwmon_disable, phydev); 2420d3ad854SRussell King if (ret) 2430d3ad854SRussell King return ret; 2440d3ad854SRussell King 2450d3ad854SRussell King priv->hwmon_dev = devm_hwmon_device_register_with_info(dev, 2460d3ad854SRussell King priv->hwmon_name, phydev, 2470d3ad854SRussell King &mv3310_hwmon_chip_info, NULL); 2480d3ad854SRussell King 2490d3ad854SRussell King return PTR_ERR_OR_ZERO(priv->hwmon_dev); 2500d3ad854SRussell King } 2510d3ad854SRussell King #else 2520d3ad854SRussell King static inline int mv3310_hwmon_config(struct phy_device *phydev, bool enable) 2530d3ad854SRussell King { 2540d3ad854SRussell King return 0; 2550d3ad854SRussell King } 2560d3ad854SRussell King 2570d3ad854SRussell King static int mv3310_hwmon_probe(struct phy_device *phydev) 2580d3ad854SRussell King { 2590d3ad854SRussell King return 0; 2600d3ad854SRussell King } 2610d3ad854SRussell King #endif 2620d3ad854SRussell King 263c9cc1c81SRussell King static int mv3310_power_down(struct phy_device *phydev) 264c9cc1c81SRussell King { 265c9cc1c81SRussell King return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, 266c9cc1c81SRussell King MV_V2_PORT_CTRL_PWRDOWN); 267c9cc1c81SRussell King } 268c9cc1c81SRussell King 269c9cc1c81SRussell King static int mv3310_power_up(struct phy_device *phydev) 270c9cc1c81SRussell King { 2718f48c2acSRussell King struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); 2728f48c2acSRussell King int ret; 2738f48c2acSRussell King 2748f48c2acSRussell King ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, 275c9cc1c81SRussell King MV_V2_PORT_CTRL_PWRDOWN); 2768f48c2acSRussell King 277829e7573SBaruch Siach if (phydev->drv->phy_id != MARVELL_PHY_ID_88X3310 || 278829e7573SBaruch Siach priv->firmware_ver < 0x00030000) 2798f48c2acSRussell King return ret; 2808f48c2acSRussell King 2818f48c2acSRussell King return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, 2828f48c2acSRussell King MV_V2_PORT_CTRL_SWRST); 283c9cc1c81SRussell King } 284c9cc1c81SRussell King 2858d8963c3SRussell King static int mv3310_reset(struct phy_device *phydev, u32 unit) 2868d8963c3SRussell King { 2878964a217SDejin Zheng int val, err; 2888d8963c3SRussell King 2898d8963c3SRussell King err = phy_modify_mmd(phydev, MDIO_MMD_PCS, unit + MDIO_CTRL1, 2908d8963c3SRussell King MDIO_CTRL1_RESET, MDIO_CTRL1_RESET); 2918d8963c3SRussell King if (err < 0) 2928d8963c3SRussell King return err; 2938d8963c3SRussell King 2948964a217SDejin Zheng return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_PCS, 2958964a217SDejin Zheng unit + MDIO_CTRL1, val, 2968964a217SDejin Zheng !(val & MDIO_CTRL1_RESET), 2978964a217SDejin Zheng 5000, 100000, true); 2988d8963c3SRussell King } 2998d8963c3SRussell King 300a585c03eSRussell King static int mv3310_get_edpd(struct phy_device *phydev, u16 *edpd) 301a585c03eSRussell King { 302a585c03eSRussell King int val; 303a585c03eSRussell King 304a585c03eSRussell King val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1); 305a585c03eSRussell King if (val < 0) 306a585c03eSRussell King return val; 307a585c03eSRussell King 308a585c03eSRussell King switch (val & MV_PCS_CSCR1_ED_MASK) { 309a585c03eSRussell King case MV_PCS_CSCR1_ED_NLP: 310a585c03eSRussell King *edpd = 1000; 311a585c03eSRussell King break; 312a585c03eSRussell King case MV_PCS_CSCR1_ED_RX: 313a585c03eSRussell King *edpd = ETHTOOL_PHY_EDPD_NO_TX; 314a585c03eSRussell King break; 315a585c03eSRussell King default: 316a585c03eSRussell King *edpd = ETHTOOL_PHY_EDPD_DISABLE; 317a585c03eSRussell King break; 318a585c03eSRussell King } 319a585c03eSRussell King return 0; 320a585c03eSRussell King } 321a585c03eSRussell King 322a585c03eSRussell King static int mv3310_set_edpd(struct phy_device *phydev, u16 edpd) 323a585c03eSRussell King { 324a585c03eSRussell King u16 val; 325a585c03eSRussell King int err; 326a585c03eSRussell King 327a585c03eSRussell King switch (edpd) { 328a585c03eSRussell King case 1000: 329a585c03eSRussell King case ETHTOOL_PHY_EDPD_DFLT_TX_MSECS: 330a585c03eSRussell King val = MV_PCS_CSCR1_ED_NLP; 331a585c03eSRussell King break; 332a585c03eSRussell King 333a585c03eSRussell King case ETHTOOL_PHY_EDPD_NO_TX: 334a585c03eSRussell King val = MV_PCS_CSCR1_ED_RX; 335a585c03eSRussell King break; 336a585c03eSRussell King 337a585c03eSRussell King case ETHTOOL_PHY_EDPD_DISABLE: 338a585c03eSRussell King val = MV_PCS_CSCR1_ED_OFF; 339a585c03eSRussell King break; 340a585c03eSRussell King 341a585c03eSRussell King default: 342a585c03eSRussell King return -EINVAL; 343a585c03eSRussell King } 344a585c03eSRussell King 345a585c03eSRussell King err = phy_modify_mmd_changed(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1, 346a585c03eSRussell King MV_PCS_CSCR1_ED_MASK, val); 347a585c03eSRussell King if (err > 0) 348a585c03eSRussell King err = mv3310_reset(phydev, MV_PCS_BASE_T); 349a585c03eSRussell King 350a585c03eSRussell King return err; 351a585c03eSRussell King } 352a585c03eSRussell King 35336023da1SRussell King static int mv3310_sfp_insert(void *upstream, const struct sfp_eeprom_id *id) 35436023da1SRussell King { 35536023da1SRussell King struct phy_device *phydev = upstream; 35636023da1SRussell King __ETHTOOL_DECLARE_LINK_MODE_MASK(support) = { 0, }; 35736023da1SRussell King phy_interface_t iface; 35836023da1SRussell King 35936023da1SRussell King sfp_parse_support(phydev->sfp_bus, id, support); 360a4516c70SRussell King iface = sfp_select_interface(phydev->sfp_bus, support); 36136023da1SRussell King 362e0f909bcSRussell King if (iface != PHY_INTERFACE_MODE_10GBASER) { 36336023da1SRussell King dev_err(&phydev->mdio.dev, "incompatible SFP module inserted\n"); 36436023da1SRussell King return -EINVAL; 36536023da1SRussell King } 36636023da1SRussell King return 0; 36736023da1SRussell King } 36836023da1SRussell King 36936023da1SRussell King static const struct sfp_upstream_ops mv3310_sfp_ops = { 37036023da1SRussell King .attach = phy_sfp_attach, 37136023da1SRussell King .detach = phy_sfp_detach, 37236023da1SRussell King .module_insert = mv3310_sfp_insert, 37336023da1SRussell King }; 37436023da1SRussell King 37520b2af32SRussell King static int mv3310_probe(struct phy_device *phydev) 37620b2af32SRussell King { 3770d3ad854SRussell King struct mv3310_priv *priv; 37820b2af32SRussell King u32 mmd_mask = MDIO_DEVS_PMAPMD | MDIO_DEVS_AN; 3790d3ad854SRussell King int ret; 38020b2af32SRussell King 38120b2af32SRussell King if (!phydev->is_c45 || 38220b2af32SRussell King (phydev->c45_ids.devices_in_package & mmd_mask) != mmd_mask) 38320b2af32SRussell King return -ENODEV; 38420b2af32SRussell King 3853d3ced2eSRussell King ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_BOOT); 3863d3ced2eSRussell King if (ret < 0) 3873d3ced2eSRussell King return ret; 3883d3ced2eSRussell King 3893d3ced2eSRussell King if (ret & MV_PMA_BOOT_FATAL) { 3903d3ced2eSRussell King dev_warn(&phydev->mdio.dev, 3913d3ced2eSRussell King "PHY failed to boot firmware, status=%04x\n", ret); 3923d3ced2eSRussell King return -ENODEV; 3933d3ced2eSRussell King } 3943d3ced2eSRussell King 3950d3ad854SRussell King priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); 3960d3ad854SRussell King if (!priv) 3970d3ad854SRussell King return -ENOMEM; 3980d3ad854SRussell King 3990d3ad854SRussell King dev_set_drvdata(&phydev->mdio.dev, priv); 4000d3ad854SRussell King 401dd649b4fSRussell King ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_FW_VER0); 402dd649b4fSRussell King if (ret < 0) 403dd649b4fSRussell King return ret; 404dd649b4fSRussell King 405dd649b4fSRussell King priv->firmware_ver = ret << 16; 406dd649b4fSRussell King 407dd649b4fSRussell King ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_FW_VER1); 408dd649b4fSRussell King if (ret < 0) 409dd649b4fSRussell King return ret; 410dd649b4fSRussell King 411dd649b4fSRussell King priv->firmware_ver |= ret; 412dd649b4fSRussell King 413dd649b4fSRussell King phydev_info(phydev, "Firmware version %u.%u.%u.%u\n", 414dd649b4fSRussell King priv->firmware_ver >> 24, (priv->firmware_ver >> 16) & 255, 415dd649b4fSRussell King (priv->firmware_ver >> 8) & 255, priv->firmware_ver & 255); 416dd649b4fSRussell King 417c9cc1c81SRussell King /* Powering down the port when not in use saves about 600mW */ 418c9cc1c81SRussell King ret = mv3310_power_down(phydev); 419c9cc1c81SRussell King if (ret) 420c9cc1c81SRussell King return ret; 421c9cc1c81SRussell King 4220d3ad854SRussell King ret = mv3310_hwmon_probe(phydev); 4230d3ad854SRussell King if (ret) 4240d3ad854SRussell King return ret; 4250d3ad854SRussell King 42636023da1SRussell King return phy_sfp_probe(phydev, &mv3310_sfp_ops); 42720b2af32SRussell King } 42820b2af32SRussell King 4290d3ad854SRussell King static int mv3310_suspend(struct phy_device *phydev) 4300d3ad854SRussell King { 431c9cc1c81SRussell King return mv3310_power_down(phydev); 4320d3ad854SRussell King } 4330d3ad854SRussell King 4340d3ad854SRussell King static int mv3310_resume(struct phy_device *phydev) 4350d3ad854SRussell King { 436af3e28cbSAntoine Tenart int ret; 437af3e28cbSAntoine Tenart 438c9cc1c81SRussell King ret = mv3310_power_up(phydev); 439af3e28cbSAntoine Tenart if (ret) 440af3e28cbSAntoine Tenart return ret; 441af3e28cbSAntoine Tenart 4420d3ad854SRussell King return mv3310_hwmon_config(phydev, true); 4430d3ad854SRussell King } 4440d3ad854SRussell King 445c47455f9SMaxime Chevallier /* Some PHYs in the Alaska family such as the 88X3310 and the 88E2010 446c47455f9SMaxime Chevallier * don't set bit 14 in PMA Extended Abilities (1.11), although they do 447c47455f9SMaxime Chevallier * support 2.5GBASET and 5GBASET. For these models, we can still read their 448c47455f9SMaxime Chevallier * 2.5G/5G extended abilities register (1.21). We detect these models based on 449c47455f9SMaxime Chevallier * the PMA device identifier, with a mask matching models known to have this 450c47455f9SMaxime Chevallier * issue 451c47455f9SMaxime Chevallier */ 452c47455f9SMaxime Chevallier static bool mv3310_has_pma_ngbaset_quirk(struct phy_device *phydev) 453c47455f9SMaxime Chevallier { 454c47455f9SMaxime Chevallier if (!(phydev->c45_ids.devices_in_package & MDIO_DEVS_PMAPMD)) 455c47455f9SMaxime Chevallier return false; 456c47455f9SMaxime Chevallier 457c47455f9SMaxime Chevallier /* Only some revisions of the 88X3310 family PMA seem to be impacted */ 458c47455f9SMaxime Chevallier return (phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] & 459c47455f9SMaxime Chevallier MV_PHY_ALASKA_NBT_QUIRK_MASK) == MV_PHY_ALASKA_NBT_QUIRK_REV; 460c47455f9SMaxime Chevallier } 461c47455f9SMaxime Chevallier 46220b2af32SRussell King static int mv3310_config_init(struct phy_device *phydev) 46320b2af32SRussell King { 464e1170333SBaruch Siach struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); 465c9cc1c81SRussell King int err; 466e1170333SBaruch Siach int val; 467c9cc1c81SRussell King 46820b2af32SRussell King /* Check that the PHY interface type is compatible */ 46920b2af32SRussell King if (phydev->interface != PHY_INTERFACE_MODE_SGMII && 470e555e5b1SMaxime Chevallier phydev->interface != PHY_INTERFACE_MODE_2500BASEX && 47120b2af32SRussell King phydev->interface != PHY_INTERFACE_MODE_XAUI && 47220b2af32SRussell King phydev->interface != PHY_INTERFACE_MODE_RXAUI && 473e0f909bcSRussell King phydev->interface != PHY_INTERFACE_MODE_10GBASER) 47420b2af32SRussell King return -ENODEV; 47520b2af32SRussell King 4768d8963c3SRussell King phydev->mdix_ctrl = ETH_TP_MDI_AUTO; 4778d8963c3SRussell King 478c9cc1c81SRussell King /* Power up so reset works */ 479c9cc1c81SRussell King err = mv3310_power_up(phydev); 480c9cc1c81SRussell King if (err) 481c9cc1c81SRussell King return err; 482c9cc1c81SRussell King 483e1170333SBaruch Siach val = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL); 484e1170333SBaruch Siach if (val < 0) 485e1170333SBaruch Siach return val; 486e1170333SBaruch Siach priv->rate_match = ((val & MV_V2_PORT_MAC_TYPE_MASK) == 487e1170333SBaruch Siach MV_V2_PORT_MAC_TYPE_RATE_MATCH); 488e1170333SBaruch Siach 489a585c03eSRussell King /* Enable EDPD mode - saving 600mW */ 490a585c03eSRussell King return mv3310_set_edpd(phydev, ETHTOOL_PHY_EDPD_DFLT_TX_MSECS); 49174145424SMaxime Chevallier } 49274145424SMaxime Chevallier 49374145424SMaxime Chevallier static int mv3310_get_features(struct phy_device *phydev) 49474145424SMaxime Chevallier { 49574145424SMaxime Chevallier int ret, val; 49674145424SMaxime Chevallier 497ac3f5533SMaxime Chevallier ret = genphy_c45_pma_read_abilities(phydev); 498ac3f5533SMaxime Chevallier if (ret) 499ac3f5533SMaxime Chevallier return ret; 50020b2af32SRussell King 501c47455f9SMaxime Chevallier if (mv3310_has_pma_ngbaset_quirk(phydev)) { 502c47455f9SMaxime Chevallier val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, 503c47455f9SMaxime Chevallier MDIO_PMA_NG_EXTABLE); 504c47455f9SMaxime Chevallier if (val < 0) 505c47455f9SMaxime Chevallier return val; 506c47455f9SMaxime Chevallier 507c47455f9SMaxime Chevallier linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 508c47455f9SMaxime Chevallier phydev->supported, 509c47455f9SMaxime Chevallier val & MDIO_PMA_NG_EXTABLE_2_5GBT); 510c47455f9SMaxime Chevallier 511c47455f9SMaxime Chevallier linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 512c47455f9SMaxime Chevallier phydev->supported, 513c47455f9SMaxime Chevallier val & MDIO_PMA_NG_EXTABLE_5GBT); 514c47455f9SMaxime Chevallier } 515c47455f9SMaxime Chevallier 51620b2af32SRussell King return 0; 51720b2af32SRussell King } 51820b2af32SRussell King 5198d8963c3SRussell King static int mv3310_config_mdix(struct phy_device *phydev) 5208d8963c3SRussell King { 5218d8963c3SRussell King u16 val; 5228d8963c3SRussell King int err; 5238d8963c3SRussell King 5248d8963c3SRussell King switch (phydev->mdix_ctrl) { 5258d8963c3SRussell King case ETH_TP_MDI_AUTO: 5268d8963c3SRussell King val = MV_PCS_CSCR1_MDIX_AUTO; 5278d8963c3SRussell King break; 5288d8963c3SRussell King case ETH_TP_MDI_X: 5298d8963c3SRussell King val = MV_PCS_CSCR1_MDIX_MDIX; 5308d8963c3SRussell King break; 5318d8963c3SRussell King case ETH_TP_MDI: 5328d8963c3SRussell King val = MV_PCS_CSCR1_MDIX_MDI; 5338d8963c3SRussell King break; 5348d8963c3SRussell King default: 5358d8963c3SRussell King return -EINVAL; 5368d8963c3SRussell King } 5378d8963c3SRussell King 5388d8963c3SRussell King err = phy_modify_mmd_changed(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1, 5398d8963c3SRussell King MV_PCS_CSCR1_MDIX_MASK, val); 5408d8963c3SRussell King if (err > 0) 5418d8963c3SRussell King err = mv3310_reset(phydev, MV_PCS_BASE_T); 5428d8963c3SRussell King 5438d8963c3SRussell King return err; 5448d8963c3SRussell King } 5458d8963c3SRussell King 54620b2af32SRussell King static int mv3310_config_aneg(struct phy_device *phydev) 54720b2af32SRussell King { 54820b2af32SRussell King bool changed = false; 5493c1bcc86SAndrew Lunn u16 reg; 55020b2af32SRussell King int ret; 55120b2af32SRussell King 5528d8963c3SRussell King ret = mv3310_config_mdix(phydev); 5538d8963c3SRussell King if (ret < 0) 5548d8963c3SRussell King return ret; 555ea4efe25SRussell King 55630de65c3SHeiner Kallweit if (phydev->autoneg == AUTONEG_DISABLE) 55730de65c3SHeiner Kallweit return genphy_c45_pma_setup_forced(phydev); 55820b2af32SRussell King 5593de97f3cSAndrew Lunn ret = genphy_c45_an_config_aneg(phydev); 56020b2af32SRussell King if (ret < 0) 56120b2af32SRussell King return ret; 56220b2af32SRussell King if (ret > 0) 56320b2af32SRussell King changed = true; 56420b2af32SRussell King 5653de97f3cSAndrew Lunn /* Clause 45 has no standardized support for 1000BaseT, therefore 5663de97f3cSAndrew Lunn * use vendor registers for this mode. 5673de97f3cSAndrew Lunn */ 5683c1bcc86SAndrew Lunn reg = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising); 569b06d8e5aSHeiner Kallweit ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MV_AN_CTRL1000, 5703c1bcc86SAndrew Lunn ADVERTISE_1000FULL | ADVERTISE_1000HALF, reg); 57120b2af32SRussell King if (ret < 0) 57220b2af32SRussell King return ret; 57320b2af32SRussell King if (ret > 0) 57420b2af32SRussell King changed = true; 57520b2af32SRussell King 5766b4cb6cbSHeiner Kallweit return genphy_c45_check_and_restart_aneg(phydev, changed); 57720b2af32SRussell King } 57820b2af32SRussell King 57920b2af32SRussell King static int mv3310_aneg_done(struct phy_device *phydev) 58020b2af32SRussell King { 58120b2af32SRussell King int val; 58220b2af32SRussell King 58320b2af32SRussell King val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1); 58420b2af32SRussell King if (val < 0) 58520b2af32SRussell King return val; 58620b2af32SRussell King 58720b2af32SRussell King if (val & MDIO_STAT1_LSTATUS) 58820b2af32SRussell King return 1; 58920b2af32SRussell King 59020b2af32SRussell King return genphy_c45_aneg_done(phydev); 59120b2af32SRussell King } 59220b2af32SRussell King 59336c4449aSRussell King static void mv3310_update_interface(struct phy_device *phydev) 59436c4449aSRussell King { 595e1170333SBaruch Siach struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); 596e1170333SBaruch Siach 597e1170333SBaruch Siach /* In "XFI with Rate Matching" mode the PHY interface is fixed at 598e1170333SBaruch Siach * 10Gb. The PHY adapts the rate to actual wire speed with help of 599e1170333SBaruch Siach * internal 16KB buffer. 600e1170333SBaruch Siach */ 601e1170333SBaruch Siach if (priv->rate_match) { 602e1170333SBaruch Siach phydev->interface = PHY_INTERFACE_MODE_10GBASER; 603e1170333SBaruch Siach return; 604e1170333SBaruch Siach } 605e1170333SBaruch Siach 60636c4449aSRussell King if ((phydev->interface == PHY_INTERFACE_MODE_SGMII || 607e555e5b1SMaxime Chevallier phydev->interface == PHY_INTERFACE_MODE_2500BASEX || 608e0f909bcSRussell King phydev->interface == PHY_INTERFACE_MODE_10GBASER) && 609e0f909bcSRussell King phydev->link) { 61036c4449aSRussell King /* The PHY automatically switches its serdes interface (and 611e0f909bcSRussell King * active PHYXS instance) between Cisco SGMII, 10GBase-R and 612e555e5b1SMaxime Chevallier * 2500BaseX modes according to the speed. Florian suggests 613e555e5b1SMaxime Chevallier * setting phydev->interface to communicate this to the MAC. 614e555e5b1SMaxime Chevallier * Only do this if we are already in one of the above modes. 61536c4449aSRussell King */ 616e555e5b1SMaxime Chevallier switch (phydev->speed) { 617e555e5b1SMaxime Chevallier case SPEED_10000: 618e0f909bcSRussell King phydev->interface = PHY_INTERFACE_MODE_10GBASER; 619e555e5b1SMaxime Chevallier break; 620e555e5b1SMaxime Chevallier case SPEED_2500: 621e555e5b1SMaxime Chevallier phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 622e555e5b1SMaxime Chevallier break; 623e555e5b1SMaxime Chevallier case SPEED_1000: 624e555e5b1SMaxime Chevallier case SPEED_100: 625e555e5b1SMaxime Chevallier case SPEED_10: 62636c4449aSRussell King phydev->interface = PHY_INTERFACE_MODE_SGMII; 627e555e5b1SMaxime Chevallier break; 628e555e5b1SMaxime Chevallier default: 629e555e5b1SMaxime Chevallier break; 630e555e5b1SMaxime Chevallier } 63136c4449aSRussell King } 63236c4449aSRussell King } 63336c4449aSRussell King 63420b2af32SRussell King /* 10GBASE-ER,LR,LRM,SR do not support autonegotiation. */ 635c84786faSRussell King static int mv3310_read_status_10gbaser(struct phy_device *phydev) 63620b2af32SRussell King { 63720b2af32SRussell King phydev->link = 1; 63820b2af32SRussell King phydev->speed = SPEED_10000; 63920b2af32SRussell King phydev->duplex = DUPLEX_FULL; 64020b2af32SRussell King 64120b2af32SRussell King return 0; 64220b2af32SRussell King } 64320b2af32SRussell King 644c84786faSRussell King static int mv3310_read_status_copper(struct phy_device *phydev) 64520b2af32SRussell King { 646c84786faSRussell King int cssr1, speed, val; 64720b2af32SRussell King 648998a8a83SHeiner Kallweit val = genphy_c45_read_link(phydev); 64920b2af32SRussell King if (val < 0) 65020b2af32SRussell King return val; 65120b2af32SRussell King 65220b2af32SRussell King val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); 65320b2af32SRussell King if (val < 0) 65420b2af32SRussell King return val; 65520b2af32SRussell King 656c84786faSRussell King cssr1 = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_CSSR1); 657c84786faSRussell King if (cssr1 < 0) 658c84786faSRussell King return val; 659c84786faSRussell King 660c84786faSRussell King /* If the link settings are not resolved, mark the link down */ 661c84786faSRussell King if (!(cssr1 & MV_PCS_CSSR1_RESOLVED)) { 662c84786faSRussell King phydev->link = 0; 663c84786faSRussell King return 0; 664c84786faSRussell King } 665c84786faSRussell King 666c84786faSRussell King /* Read the copper link settings */ 667c84786faSRussell King speed = cssr1 & MV_PCS_CSSR1_SPD1_MASK; 668c84786faSRussell King if (speed == MV_PCS_CSSR1_SPD1_SPD2) 669c84786faSRussell King speed |= cssr1 & MV_PCS_CSSR1_SPD2_MASK; 670c84786faSRussell King 671c84786faSRussell King switch (speed) { 672c84786faSRussell King case MV_PCS_CSSR1_SPD1_SPD2 | MV_PCS_CSSR1_SPD2_10000: 673c84786faSRussell King phydev->speed = SPEED_10000; 674c84786faSRussell King break; 675c84786faSRussell King 676c84786faSRussell King case MV_PCS_CSSR1_SPD1_SPD2 | MV_PCS_CSSR1_SPD2_5000: 677c84786faSRussell King phydev->speed = SPEED_5000; 678c84786faSRussell King break; 679c84786faSRussell King 680c84786faSRussell King case MV_PCS_CSSR1_SPD1_SPD2 | MV_PCS_CSSR1_SPD2_2500: 681c84786faSRussell King phydev->speed = SPEED_2500; 682c84786faSRussell King break; 683c84786faSRussell King 684c84786faSRussell King case MV_PCS_CSSR1_SPD1_1000: 685c84786faSRussell King phydev->speed = SPEED_1000; 686c84786faSRussell King break; 687c84786faSRussell King 688c84786faSRussell King case MV_PCS_CSSR1_SPD1_100: 689c84786faSRussell King phydev->speed = SPEED_100; 690c84786faSRussell King break; 691c84786faSRussell King 692c84786faSRussell King case MV_PCS_CSSR1_SPD1_10: 693c84786faSRussell King phydev->speed = SPEED_10; 694c84786faSRussell King break; 695c84786faSRussell King } 696c84786faSRussell King 697c84786faSRussell King phydev->duplex = cssr1 & MV_PCS_CSSR1_DUPLEX_FULL ? 698c84786faSRussell King DUPLEX_FULL : DUPLEX_HALF; 699c84786faSRussell King phydev->mdix = cssr1 & MV_PCS_CSSR1_MDIX ? 700c84786faSRussell King ETH_TP_MDI_X : ETH_TP_MDI; 701c84786faSRussell King 70220b2af32SRussell King if (val & MDIO_AN_STAT1_COMPLETE) { 70320b2af32SRussell King val = genphy_c45_read_lpa(phydev); 70420b2af32SRussell King if (val < 0) 70520b2af32SRussell King return val; 70620b2af32SRussell King 707cc1122b0SColin Ian King /* Read the link partner's 1G advertisement */ 70820b2af32SRussell King val = phy_read_mmd(phydev, MDIO_MMD_AN, MV_AN_STAT1000); 70920b2af32SRussell King if (val < 0) 71020b2af32SRussell King return val; 71120b2af32SRussell King 71278a24df3SAndrew Lunn mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val); 71320b2af32SRussell King 714c84786faSRussell King /* Update the pause status */ 715c84786faSRussell King phy_resolve_aneg_pause(phydev); 71620b2af32SRussell King } 71720b2af32SRussell King 718c84786faSRussell King return 0; 71920b2af32SRussell King } 72020b2af32SRussell King 721c84786faSRussell King static int mv3310_read_status(struct phy_device *phydev) 722c84786faSRussell King { 723c84786faSRussell King int err, val; 724ea4efe25SRussell King 725c84786faSRussell King phydev->speed = SPEED_UNKNOWN; 726c84786faSRussell King phydev->duplex = DUPLEX_UNKNOWN; 727c84786faSRussell King linkmode_zero(phydev->lp_advertising); 728c84786faSRussell King phydev->link = 0; 729c84786faSRussell King phydev->pause = 0; 730c84786faSRussell King phydev->asym_pause = 0; 731ea4efe25SRussell King phydev->mdix = ETH_TP_MDI_INVALID; 732ea4efe25SRussell King 733c84786faSRussell King val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1); 734c84786faSRussell King if (val < 0) 735c84786faSRussell King return val; 736c84786faSRussell King 737c84786faSRussell King if (val & MDIO_STAT1_LSTATUS) 738c84786faSRussell King err = mv3310_read_status_10gbaser(phydev); 739c84786faSRussell King else 740c84786faSRussell King err = mv3310_read_status_copper(phydev); 741c84786faSRussell King if (err < 0) 742c84786faSRussell King return err; 743c84786faSRussell King 744c84786faSRussell King if (phydev->link) 74536c4449aSRussell King mv3310_update_interface(phydev); 74620b2af32SRussell King 74720b2af32SRussell King return 0; 74820b2af32SRussell King } 74920b2af32SRussell King 750a585c03eSRussell King static int mv3310_get_tunable(struct phy_device *phydev, 751a585c03eSRussell King struct ethtool_tunable *tuna, void *data) 752a585c03eSRussell King { 753a585c03eSRussell King switch (tuna->id) { 754a585c03eSRussell King case ETHTOOL_PHY_EDPD: 755a585c03eSRussell King return mv3310_get_edpd(phydev, data); 756a585c03eSRussell King default: 757a585c03eSRussell King return -EOPNOTSUPP; 758a585c03eSRussell King } 759a585c03eSRussell King } 760a585c03eSRussell King 761a585c03eSRussell King static int mv3310_set_tunable(struct phy_device *phydev, 762a585c03eSRussell King struct ethtool_tunable *tuna, const void *data) 763a585c03eSRussell King { 764a585c03eSRussell King switch (tuna->id) { 765a585c03eSRussell King case ETHTOOL_PHY_EDPD: 766a585c03eSRussell King return mv3310_set_edpd(phydev, *(u16 *)data); 767a585c03eSRussell King default: 768a585c03eSRussell King return -EOPNOTSUPP; 769a585c03eSRussell King } 770a585c03eSRussell King } 771a585c03eSRussell King 77220b2af32SRussell King static struct phy_driver mv3310_drivers[] = { 77320b2af32SRussell King { 774631ba906SMaxime Chevallier .phy_id = MARVELL_PHY_ID_88X3310, 775952b6b3bSAntoine Tenart .phy_id_mask = MARVELL_PHY_ID_MASK, 77620b2af32SRussell King .name = "mv88x3310", 77774145424SMaxime Chevallier .get_features = mv3310_get_features, 77820b2af32SRussell King .config_init = mv3310_config_init, 7790d3ad854SRussell King .probe = mv3310_probe, 7800d3ad854SRussell King .suspend = mv3310_suspend, 7810d3ad854SRussell King .resume = mv3310_resume, 78220b2af32SRussell King .config_aneg = mv3310_config_aneg, 78320b2af32SRussell King .aneg_done = mv3310_aneg_done, 78420b2af32SRussell King .read_status = mv3310_read_status, 785a585c03eSRussell King .get_tunable = mv3310_get_tunable, 786a585c03eSRussell King .set_tunable = mv3310_set_tunable, 78720b2af32SRussell King }, 78862d01535SMaxime Chevallier { 78962d01535SMaxime Chevallier .phy_id = MARVELL_PHY_ID_88E2110, 79062d01535SMaxime Chevallier .phy_id_mask = MARVELL_PHY_ID_MASK, 79162d01535SMaxime Chevallier .name = "mv88x2110", 79262d01535SMaxime Chevallier .probe = mv3310_probe, 793e02c4a9dSAntoine Tenart .suspend = mv3310_suspend, 794e02c4a9dSAntoine Tenart .resume = mv3310_resume, 79562d01535SMaxime Chevallier .config_init = mv3310_config_init, 79662d01535SMaxime Chevallier .config_aneg = mv3310_config_aneg, 79762d01535SMaxime Chevallier .aneg_done = mv3310_aneg_done, 79862d01535SMaxime Chevallier .read_status = mv3310_read_status, 799a585c03eSRussell King .get_tunable = mv3310_get_tunable, 800a585c03eSRussell King .set_tunable = mv3310_set_tunable, 80162d01535SMaxime Chevallier }, 80220b2af32SRussell King }; 80320b2af32SRussell King 80420b2af32SRussell King module_phy_driver(mv3310_drivers); 80520b2af32SRussell King 80620b2af32SRussell King static struct mdio_device_id __maybe_unused mv3310_tbl[] = { 807631ba906SMaxime Chevallier { MARVELL_PHY_ID_88X3310, MARVELL_PHY_ID_MASK }, 80862d01535SMaxime Chevallier { MARVELL_PHY_ID_88E2110, MARVELL_PHY_ID_MASK }, 80920b2af32SRussell King { }, 81020b2af32SRussell King }; 81120b2af32SRussell King MODULE_DEVICE_TABLE(mdio, mv3310_tbl); 81220b2af32SRussell King MODULE_DESCRIPTION("Marvell Alaska X 10Gigabit Ethernet PHY driver (MV88X3310)"); 81320b2af32SRussell King MODULE_LICENSE("GPL"); 814