1a2443fd1SAndrew Lunn // SPDX-License-Identifier: GPL-2.0+ 220b2af32SRussell King /* 320b2af32SRussell King * Marvell 10G 88x3310 PHY driver 420b2af32SRussell King * 520b2af32SRussell King * Based upon the ID registers, this PHY appears to be a mixture of IPs 620b2af32SRussell King * from two different companies. 720b2af32SRussell King * 820b2af32SRussell King * There appears to be several different data paths through the PHY which 920b2af32SRussell King * are automatically managed by the PHY. The following has been determined 1005ca1b32SRussell King * via observation and experimentation for a setup using single-lane Serdes: 1120b2af32SRussell King * 1220b2af32SRussell King * SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G) 1320b2af32SRussell King * 10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G) 1420b2af32SRussell King * 10GBASE-KR PHYXS -- BASE-R PCS -- Fiber 1520b2af32SRussell King * 1605ca1b32SRussell King * With XAUI, observation shows: 1705ca1b32SRussell King * 1805ca1b32SRussell King * XAUI PHYXS -- <appropriate PCS as above> 1905ca1b32SRussell King * 2005ca1b32SRussell King * and no switching of the host interface mode occurs. 2105ca1b32SRussell King * 2220b2af32SRussell King * If both the fiber and copper ports are connected, the first to gain 2320b2af32SRussell King * link takes priority and the other port is completely locked out. 2420b2af32SRussell King */ 250d3ad854SRussell King #include <linux/ctype.h> 260d3ad854SRussell King #include <linux/hwmon.h> 27952b6b3bSAntoine Tenart #include <linux/marvell_phy.h> 280d3ad854SRussell King #include <linux/phy.h> 2920b2af32SRussell King 3020b2af32SRussell King enum { 3120b2af32SRussell King MV_PCS_BASE_T = 0x0000, 3220b2af32SRussell King MV_PCS_BASE_R = 0x1000, 3320b2af32SRussell King MV_PCS_1000BASEX = 0x2000, 3420b2af32SRussell King 35ea4efe25SRussell King MV_PCS_PAIRSWAP = 0x8182, 36ea4efe25SRussell King MV_PCS_PAIRSWAP_MASK = 0x0003, 37ea4efe25SRussell King MV_PCS_PAIRSWAP_AB = 0x0002, 38ea4efe25SRussell King MV_PCS_PAIRSWAP_NONE = 0x0003, 39ea4efe25SRussell King 4020b2af32SRussell King /* These registers appear at 0x800X and 0xa00X - the 0xa00X control 4120b2af32SRussell King * registers appear to set themselves to the 0x800X when AN is 4220b2af32SRussell King * restarted, but status registers appear readable from either. 4320b2af32SRussell King */ 4420b2af32SRussell King MV_AN_CTRL1000 = 0x8000, /* 1000base-T control register */ 4520b2af32SRussell King MV_AN_STAT1000 = 0x8001, /* 1000base-T status register */ 460d3ad854SRussell King 470d3ad854SRussell King /* Vendor2 MMD registers */ 480d3ad854SRussell King MV_V2_TEMP_CTRL = 0xf08a, 490d3ad854SRussell King MV_V2_TEMP_CTRL_MASK = 0xc000, 500d3ad854SRussell King MV_V2_TEMP_CTRL_SAMPLE = 0x0000, 510d3ad854SRussell King MV_V2_TEMP_CTRL_DISABLE = 0xc000, 520d3ad854SRussell King MV_V2_TEMP = 0xf08c, 530d3ad854SRussell King MV_V2_TEMP_UNKNOWN = 0x9600, /* unknown function */ 540d3ad854SRussell King }; 550d3ad854SRussell King 560d3ad854SRussell King struct mv3310_priv { 570d3ad854SRussell King struct device *hwmon_dev; 580d3ad854SRussell King char *hwmon_name; 5920b2af32SRussell King }; 6020b2af32SRussell King 610d3ad854SRussell King #ifdef CONFIG_HWMON 620d3ad854SRussell King static umode_t mv3310_hwmon_is_visible(const void *data, 630d3ad854SRussell King enum hwmon_sensor_types type, 640d3ad854SRussell King u32 attr, int channel) 650d3ad854SRussell King { 660d3ad854SRussell King if (type == hwmon_chip && attr == hwmon_chip_update_interval) 670d3ad854SRussell King return 0444; 680d3ad854SRussell King if (type == hwmon_temp && attr == hwmon_temp_input) 690d3ad854SRussell King return 0444; 700d3ad854SRussell King return 0; 710d3ad854SRussell King } 720d3ad854SRussell King 730d3ad854SRussell King static int mv3310_hwmon_read(struct device *dev, enum hwmon_sensor_types type, 740d3ad854SRussell King u32 attr, int channel, long *value) 750d3ad854SRussell King { 760d3ad854SRussell King struct phy_device *phydev = dev_get_drvdata(dev); 770d3ad854SRussell King int temp; 780d3ad854SRussell King 790d3ad854SRussell King if (type == hwmon_chip && attr == hwmon_chip_update_interval) { 800d3ad854SRussell King *value = MSEC_PER_SEC; 810d3ad854SRussell King return 0; 820d3ad854SRussell King } 830d3ad854SRussell King 840d3ad854SRussell King if (type == hwmon_temp && attr == hwmon_temp_input) { 850d3ad854SRussell King temp = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP); 860d3ad854SRussell King if (temp < 0) 870d3ad854SRussell King return temp; 880d3ad854SRussell King 890d3ad854SRussell King *value = ((temp & 0xff) - 75) * 1000; 900d3ad854SRussell King 910d3ad854SRussell King return 0; 920d3ad854SRussell King } 930d3ad854SRussell King 940d3ad854SRussell King return -EOPNOTSUPP; 950d3ad854SRussell King } 960d3ad854SRussell King 970d3ad854SRussell King static const struct hwmon_ops mv3310_hwmon_ops = { 980d3ad854SRussell King .is_visible = mv3310_hwmon_is_visible, 990d3ad854SRussell King .read = mv3310_hwmon_read, 1000d3ad854SRussell King }; 1010d3ad854SRussell King 1020d3ad854SRussell King static u32 mv3310_hwmon_chip_config[] = { 1030d3ad854SRussell King HWMON_C_REGISTER_TZ | HWMON_C_UPDATE_INTERVAL, 1040d3ad854SRussell King 0, 1050d3ad854SRussell King }; 1060d3ad854SRussell King 1070d3ad854SRussell King static const struct hwmon_channel_info mv3310_hwmon_chip = { 1080d3ad854SRussell King .type = hwmon_chip, 1090d3ad854SRussell King .config = mv3310_hwmon_chip_config, 1100d3ad854SRussell King }; 1110d3ad854SRussell King 1120d3ad854SRussell King static u32 mv3310_hwmon_temp_config[] = { 1130d3ad854SRussell King HWMON_T_INPUT, 1140d3ad854SRussell King 0, 1150d3ad854SRussell King }; 1160d3ad854SRussell King 1170d3ad854SRussell King static const struct hwmon_channel_info mv3310_hwmon_temp = { 1180d3ad854SRussell King .type = hwmon_temp, 1190d3ad854SRussell King .config = mv3310_hwmon_temp_config, 1200d3ad854SRussell King }; 1210d3ad854SRussell King 1220d3ad854SRussell King static const struct hwmon_channel_info *mv3310_hwmon_info[] = { 1230d3ad854SRussell King &mv3310_hwmon_chip, 1240d3ad854SRussell King &mv3310_hwmon_temp, 1250d3ad854SRussell King NULL, 1260d3ad854SRussell King }; 1270d3ad854SRussell King 1280d3ad854SRussell King static const struct hwmon_chip_info mv3310_hwmon_chip_info = { 1290d3ad854SRussell King .ops = &mv3310_hwmon_ops, 1300d3ad854SRussell King .info = mv3310_hwmon_info, 1310d3ad854SRussell King }; 1320d3ad854SRussell King 1330d3ad854SRussell King static int mv3310_hwmon_config(struct phy_device *phydev, bool enable) 1340d3ad854SRussell King { 1350d3ad854SRussell King u16 val; 1360d3ad854SRussell King int ret; 1370d3ad854SRussell King 1380d3ad854SRussell King ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP, 1390d3ad854SRussell King MV_V2_TEMP_UNKNOWN); 1400d3ad854SRussell King if (ret < 0) 1410d3ad854SRussell King return ret; 1420d3ad854SRussell King 1430d3ad854SRussell King val = enable ? MV_V2_TEMP_CTRL_SAMPLE : MV_V2_TEMP_CTRL_DISABLE; 1440d3ad854SRussell King 145b06d8e5aSHeiner Kallweit return phy_modify_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP_CTRL, 146b06d8e5aSHeiner Kallweit MV_V2_TEMP_CTRL_MASK, val); 1470d3ad854SRussell King } 1480d3ad854SRussell King 1490d3ad854SRussell King static void mv3310_hwmon_disable(void *data) 1500d3ad854SRussell King { 1510d3ad854SRussell King struct phy_device *phydev = data; 1520d3ad854SRussell King 1530d3ad854SRussell King mv3310_hwmon_config(phydev, false); 1540d3ad854SRussell King } 1550d3ad854SRussell King 1560d3ad854SRussell King static int mv3310_hwmon_probe(struct phy_device *phydev) 1570d3ad854SRussell King { 1580d3ad854SRussell King struct device *dev = &phydev->mdio.dev; 1590d3ad854SRussell King struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); 1600d3ad854SRussell King int i, j, ret; 1610d3ad854SRussell King 1620d3ad854SRussell King priv->hwmon_name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL); 1630d3ad854SRussell King if (!priv->hwmon_name) 1640d3ad854SRussell King return -ENODEV; 1650d3ad854SRussell King 1660d3ad854SRussell King for (i = j = 0; priv->hwmon_name[i]; i++) { 1670d3ad854SRussell King if (isalnum(priv->hwmon_name[i])) { 1680d3ad854SRussell King if (i != j) 1690d3ad854SRussell King priv->hwmon_name[j] = priv->hwmon_name[i]; 1700d3ad854SRussell King j++; 1710d3ad854SRussell King } 1720d3ad854SRussell King } 1730d3ad854SRussell King priv->hwmon_name[j] = '\0'; 1740d3ad854SRussell King 1750d3ad854SRussell King ret = mv3310_hwmon_config(phydev, true); 1760d3ad854SRussell King if (ret) 1770d3ad854SRussell King return ret; 1780d3ad854SRussell King 1790d3ad854SRussell King ret = devm_add_action_or_reset(dev, mv3310_hwmon_disable, phydev); 1800d3ad854SRussell King if (ret) 1810d3ad854SRussell King return ret; 1820d3ad854SRussell King 1830d3ad854SRussell King priv->hwmon_dev = devm_hwmon_device_register_with_info(dev, 1840d3ad854SRussell King priv->hwmon_name, phydev, 1850d3ad854SRussell King &mv3310_hwmon_chip_info, NULL); 1860d3ad854SRussell King 1870d3ad854SRussell King return PTR_ERR_OR_ZERO(priv->hwmon_dev); 1880d3ad854SRussell King } 1890d3ad854SRussell King #else 1900d3ad854SRussell King static inline int mv3310_hwmon_config(struct phy_device *phydev, bool enable) 1910d3ad854SRussell King { 1920d3ad854SRussell King return 0; 1930d3ad854SRussell King } 1940d3ad854SRussell King 1950d3ad854SRussell King static int mv3310_hwmon_probe(struct phy_device *phydev) 1960d3ad854SRussell King { 1970d3ad854SRussell King return 0; 1980d3ad854SRussell King } 1990d3ad854SRussell King #endif 2000d3ad854SRussell King 20120b2af32SRussell King static int mv3310_probe(struct phy_device *phydev) 20220b2af32SRussell King { 2030d3ad854SRussell King struct mv3310_priv *priv; 20420b2af32SRussell King u32 mmd_mask = MDIO_DEVS_PMAPMD | MDIO_DEVS_AN; 2050d3ad854SRussell King int ret; 20620b2af32SRussell King 20720b2af32SRussell King if (!phydev->is_c45 || 20820b2af32SRussell King (phydev->c45_ids.devices_in_package & mmd_mask) != mmd_mask) 20920b2af32SRussell King return -ENODEV; 21020b2af32SRussell King 2110d3ad854SRussell King priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); 2120d3ad854SRussell King if (!priv) 2130d3ad854SRussell King return -ENOMEM; 2140d3ad854SRussell King 2150d3ad854SRussell King dev_set_drvdata(&phydev->mdio.dev, priv); 2160d3ad854SRussell King 2170d3ad854SRussell King ret = mv3310_hwmon_probe(phydev); 2180d3ad854SRussell King if (ret) 2190d3ad854SRussell King return ret; 2200d3ad854SRussell King 22120b2af32SRussell King return 0; 22220b2af32SRussell King } 22320b2af32SRussell King 2240d3ad854SRussell King static int mv3310_suspend(struct phy_device *phydev) 2250d3ad854SRussell King { 2260d3ad854SRussell King return 0; 2270d3ad854SRussell King } 2280d3ad854SRussell King 2290d3ad854SRussell King static int mv3310_resume(struct phy_device *phydev) 2300d3ad854SRussell King { 2310d3ad854SRussell King return mv3310_hwmon_config(phydev, true); 2320d3ad854SRussell King } 2330d3ad854SRussell King 23420b2af32SRussell King static int mv3310_config_init(struct phy_device *phydev) 23520b2af32SRussell King { 23620b2af32SRussell King __ETHTOOL_DECLARE_LINK_MODE_MASK(supported) = { 0, }; 23720b2af32SRussell King int val; 23820b2af32SRussell King 23920b2af32SRussell King /* Check that the PHY interface type is compatible */ 24020b2af32SRussell King if (phydev->interface != PHY_INTERFACE_MODE_SGMII && 24120b2af32SRussell King phydev->interface != PHY_INTERFACE_MODE_XAUI && 24220b2af32SRussell King phydev->interface != PHY_INTERFACE_MODE_RXAUI && 24320b2af32SRussell King phydev->interface != PHY_INTERFACE_MODE_10GKR) 24420b2af32SRussell King return -ENODEV; 24520b2af32SRussell King 24620b2af32SRussell King __set_bit(ETHTOOL_LINK_MODE_Pause_BIT, supported); 24720b2af32SRussell King __set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, supported); 24820b2af32SRussell King 24920b2af32SRussell King if (phydev->c45_ids.devices_in_package & MDIO_DEVS_AN) { 25020b2af32SRussell King val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); 25120b2af32SRussell King if (val < 0) 25220b2af32SRussell King return val; 25320b2af32SRussell King 25420b2af32SRussell King if (val & MDIO_AN_STAT1_ABLE) 25520b2af32SRussell King __set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, supported); 25620b2af32SRussell King } 25720b2af32SRussell King 25820b2af32SRussell King val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT2); 25920b2af32SRussell King if (val < 0) 26020b2af32SRussell King return val; 26120b2af32SRussell King 26220b2af32SRussell King /* Ethtool does not support the WAN mode bits */ 26320b2af32SRussell King if (val & (MDIO_PMA_STAT2_10GBSR | MDIO_PMA_STAT2_10GBLR | 26420b2af32SRussell King MDIO_PMA_STAT2_10GBER | MDIO_PMA_STAT2_10GBLX4 | 26520b2af32SRussell King MDIO_PMA_STAT2_10GBSW | MDIO_PMA_STAT2_10GBLW | 26620b2af32SRussell King MDIO_PMA_STAT2_10GBEW)) 26720b2af32SRussell King __set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, supported); 26820b2af32SRussell King if (val & MDIO_PMA_STAT2_10GBSR) 26920b2af32SRussell King __set_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, supported); 27020b2af32SRussell King if (val & MDIO_PMA_STAT2_10GBLR) 27120b2af32SRussell King __set_bit(ETHTOOL_LINK_MODE_10000baseLR_Full_BIT, supported); 27220b2af32SRussell King if (val & MDIO_PMA_STAT2_10GBER) 27320b2af32SRussell King __set_bit(ETHTOOL_LINK_MODE_10000baseER_Full_BIT, supported); 27420b2af32SRussell King 27520b2af32SRussell King if (val & MDIO_PMA_STAT2_EXTABLE) { 27620b2af32SRussell King val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE); 27720b2af32SRussell King if (val < 0) 27820b2af32SRussell King return val; 27920b2af32SRussell King 28020b2af32SRussell King if (val & (MDIO_PMA_EXTABLE_10GBT | MDIO_PMA_EXTABLE_1000BT | 28120b2af32SRussell King MDIO_PMA_EXTABLE_100BTX | MDIO_PMA_EXTABLE_10BT)) 28220b2af32SRussell King __set_bit(ETHTOOL_LINK_MODE_TP_BIT, supported); 28320b2af32SRussell King if (val & MDIO_PMA_EXTABLE_10GBLRM) 28420b2af32SRussell King __set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, supported); 28520b2af32SRussell King if (val & (MDIO_PMA_EXTABLE_10GBKX4 | MDIO_PMA_EXTABLE_10GBKR | 28620b2af32SRussell King MDIO_PMA_EXTABLE_1000BKX)) 28720b2af32SRussell King __set_bit(ETHTOOL_LINK_MODE_Backplane_BIT, supported); 28820b2af32SRussell King if (val & MDIO_PMA_EXTABLE_10GBLRM) 28920b2af32SRussell King __set_bit(ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT, 29020b2af32SRussell King supported); 29120b2af32SRussell King if (val & MDIO_PMA_EXTABLE_10GBT) 29220b2af32SRussell King __set_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 29320b2af32SRussell King supported); 29420b2af32SRussell King if (val & MDIO_PMA_EXTABLE_10GBKX4) 29520b2af32SRussell King __set_bit(ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT, 29620b2af32SRussell King supported); 29720b2af32SRussell King if (val & MDIO_PMA_EXTABLE_10GBKR) 29820b2af32SRussell King __set_bit(ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, 29920b2af32SRussell King supported); 30020b2af32SRussell King if (val & MDIO_PMA_EXTABLE_1000BT) 30120b2af32SRussell King __set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 30220b2af32SRussell King supported); 30320b2af32SRussell King if (val & MDIO_PMA_EXTABLE_1000BKX) 30420b2af32SRussell King __set_bit(ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, 30520b2af32SRussell King supported); 3066798d03cSRussell King if (val & MDIO_PMA_EXTABLE_100BTX) { 30720b2af32SRussell King __set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, 30820b2af32SRussell King supported); 3096798d03cSRussell King __set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, 3106798d03cSRussell King supported); 3116798d03cSRussell King } 3126798d03cSRussell King if (val & MDIO_PMA_EXTABLE_10BT) { 31320b2af32SRussell King __set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, 31420b2af32SRussell King supported); 3156798d03cSRussell King __set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, 3166798d03cSRussell King supported); 3176798d03cSRussell King } 31820b2af32SRussell King } 31920b2af32SRussell King 3203c1bcc86SAndrew Lunn linkmode_copy(phydev->supported, supported); 3213c1bcc86SAndrew Lunn linkmode_and(phydev->advertising, phydev->advertising, 3223c1bcc86SAndrew Lunn phydev->supported); 32320b2af32SRussell King 32420b2af32SRussell King return 0; 32520b2af32SRussell King } 32620b2af32SRussell King 32720b2af32SRussell King static int mv3310_config_aneg(struct phy_device *phydev) 32820b2af32SRussell King { 32920b2af32SRussell King bool changed = false; 3303c1bcc86SAndrew Lunn u16 reg; 33120b2af32SRussell King int ret; 33220b2af32SRussell King 333ea4efe25SRussell King /* We don't support manual MDI control */ 334ea4efe25SRussell King phydev->mdix_ctrl = ETH_TP_MDI_AUTO; 335ea4efe25SRussell King 33620b2af32SRussell King if (phydev->autoneg == AUTONEG_DISABLE) { 33720b2af32SRussell King ret = genphy_c45_pma_setup_forced(phydev); 33820b2af32SRussell King if (ret < 0) 33920b2af32SRussell King return ret; 34020b2af32SRussell King 34120b2af32SRussell King return genphy_c45_an_disable_aneg(phydev); 34220b2af32SRussell King } 34320b2af32SRussell King 3443c1bcc86SAndrew Lunn linkmode_and(phydev->advertising, phydev->advertising, 3453c1bcc86SAndrew Lunn phydev->supported); 34620b2af32SRussell King 347b06d8e5aSHeiner Kallweit ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE, 34820b2af32SRussell King ADVERTISE_ALL | ADVERTISE_100BASE4 | 34920b2af32SRussell King ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM, 3503c1bcc86SAndrew Lunn linkmode_adv_to_mii_adv_t(phydev->advertising)); 35120b2af32SRussell King if (ret < 0) 35220b2af32SRussell King return ret; 35320b2af32SRussell King if (ret > 0) 35420b2af32SRussell King changed = true; 35520b2af32SRussell King 3563c1bcc86SAndrew Lunn reg = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising); 357b06d8e5aSHeiner Kallweit ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MV_AN_CTRL1000, 3583c1bcc86SAndrew Lunn ADVERTISE_1000FULL | ADVERTISE_1000HALF, reg); 35920b2af32SRussell King if (ret < 0) 36020b2af32SRussell King return ret; 36120b2af32SRussell King if (ret > 0) 36220b2af32SRussell King changed = true; 36320b2af32SRussell King 36420b2af32SRussell King /* 10G control register */ 3653c1bcc86SAndrew Lunn if (linkmode_test_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 3663c1bcc86SAndrew Lunn phydev->advertising)) 3673c1bcc86SAndrew Lunn reg = MDIO_AN_10GBT_CTRL_ADV10G; 3683c1bcc86SAndrew Lunn else 3693c1bcc86SAndrew Lunn reg = 0; 3703c1bcc86SAndrew Lunn 371b06d8e5aSHeiner Kallweit ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, 3723c1bcc86SAndrew Lunn MDIO_AN_10GBT_CTRL_ADV10G, reg); 37320b2af32SRussell King if (ret < 0) 37420b2af32SRussell King return ret; 37520b2af32SRussell King if (ret > 0) 37620b2af32SRussell King changed = true; 37720b2af32SRussell King 37820b2af32SRussell King if (changed) 37920b2af32SRussell King ret = genphy_c45_restart_aneg(phydev); 38020b2af32SRussell King 38120b2af32SRussell King return ret; 38220b2af32SRussell King } 38320b2af32SRussell King 38420b2af32SRussell King static int mv3310_aneg_done(struct phy_device *phydev) 38520b2af32SRussell King { 38620b2af32SRussell King int val; 38720b2af32SRussell King 38820b2af32SRussell King val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1); 38920b2af32SRussell King if (val < 0) 39020b2af32SRussell King return val; 39120b2af32SRussell King 39220b2af32SRussell King if (val & MDIO_STAT1_LSTATUS) 39320b2af32SRussell King return 1; 39420b2af32SRussell King 39520b2af32SRussell King return genphy_c45_aneg_done(phydev); 39620b2af32SRussell King } 39720b2af32SRussell King 39836c4449aSRussell King static void mv3310_update_interface(struct phy_device *phydev) 39936c4449aSRussell King { 40036c4449aSRussell King if ((phydev->interface == PHY_INTERFACE_MODE_SGMII || 40136c4449aSRussell King phydev->interface == PHY_INTERFACE_MODE_10GKR) && phydev->link) { 40236c4449aSRussell King /* The PHY automatically switches its serdes interface (and 40336c4449aSRussell King * active PHYXS instance) between Cisco SGMII and 10GBase-KR 40436c4449aSRussell King * modes according to the speed. Florian suggests setting 40536c4449aSRussell King * phydev->interface to communicate this to the MAC. Only do 40636c4449aSRussell King * this if we are already in either SGMII or 10GBase-KR mode. 40736c4449aSRussell King */ 40836c4449aSRussell King if (phydev->speed == SPEED_10000) 40936c4449aSRussell King phydev->interface = PHY_INTERFACE_MODE_10GKR; 41036c4449aSRussell King else if (phydev->speed >= SPEED_10 && 41136c4449aSRussell King phydev->speed < SPEED_10000) 41236c4449aSRussell King phydev->interface = PHY_INTERFACE_MODE_SGMII; 41336c4449aSRussell King } 41436c4449aSRussell King } 41536c4449aSRussell King 41620b2af32SRussell King /* 10GBASE-ER,LR,LRM,SR do not support autonegotiation. */ 41720b2af32SRussell King static int mv3310_read_10gbr_status(struct phy_device *phydev) 41820b2af32SRussell King { 41920b2af32SRussell King phydev->link = 1; 42020b2af32SRussell King phydev->speed = SPEED_10000; 42120b2af32SRussell King phydev->duplex = DUPLEX_FULL; 42220b2af32SRussell King 42336c4449aSRussell King mv3310_update_interface(phydev); 42420b2af32SRussell King 42520b2af32SRussell King return 0; 42620b2af32SRussell King } 42720b2af32SRussell King 42820b2af32SRussell King static int mv3310_read_status(struct phy_device *phydev) 42920b2af32SRussell King { 43020b2af32SRussell King int val; 43120b2af32SRussell King 43220b2af32SRussell King phydev->speed = SPEED_UNKNOWN; 43320b2af32SRussell King phydev->duplex = DUPLEX_UNKNOWN; 434c0ec3c27SAndrew Lunn linkmode_zero(phydev->lp_advertising); 43520b2af32SRussell King phydev->link = 0; 43620b2af32SRussell King phydev->pause = 0; 43720b2af32SRussell King phydev->asym_pause = 0; 438ea4efe25SRussell King phydev->mdix = 0; 43920b2af32SRussell King 44020b2af32SRussell King val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1); 44120b2af32SRussell King if (val < 0) 44220b2af32SRussell King return val; 44320b2af32SRussell King 44420b2af32SRussell King if (val & MDIO_STAT1_LSTATUS) 44520b2af32SRussell King return mv3310_read_10gbr_status(phydev); 44620b2af32SRussell King 447998a8a83SHeiner Kallweit val = genphy_c45_read_link(phydev); 44820b2af32SRussell King if (val < 0) 44920b2af32SRussell King return val; 45020b2af32SRussell King 45120b2af32SRussell King val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); 45220b2af32SRussell King if (val < 0) 45320b2af32SRussell King return val; 45420b2af32SRussell King 45520b2af32SRussell King if (val & MDIO_AN_STAT1_COMPLETE) { 45620b2af32SRussell King val = genphy_c45_read_lpa(phydev); 45720b2af32SRussell King if (val < 0) 45820b2af32SRussell King return val; 45920b2af32SRussell King 460cc1122b0SColin Ian King /* Read the link partner's 1G advertisement */ 46120b2af32SRussell King val = phy_read_mmd(phydev, MDIO_MMD_AN, MV_AN_STAT1000); 46220b2af32SRussell King if (val < 0) 46320b2af32SRussell King return val; 46420b2af32SRussell King 46578a24df3SAndrew Lunn mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val); 46620b2af32SRussell King 4676798d03cSRussell King if (phydev->autoneg == AUTONEG_ENABLE) 4686798d03cSRussell King phy_resolve_aneg_linkmode(phydev); 46920b2af32SRussell King } 47020b2af32SRussell King 47120b2af32SRussell King if (phydev->autoneg != AUTONEG_ENABLE) { 47220b2af32SRussell King val = genphy_c45_read_pma(phydev); 47320b2af32SRussell King if (val < 0) 47420b2af32SRussell King return val; 47520b2af32SRussell King } 47620b2af32SRussell King 477ea4efe25SRussell King if (phydev->speed == SPEED_10000) { 478ea4efe25SRussell King val = genphy_c45_read_mdix(phydev); 479ea4efe25SRussell King if (val < 0) 480ea4efe25SRussell King return val; 481ea4efe25SRussell King } else { 482ea4efe25SRussell King val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_PAIRSWAP); 483ea4efe25SRussell King if (val < 0) 484ea4efe25SRussell King return val; 485ea4efe25SRussell King 486ea4efe25SRussell King switch (val & MV_PCS_PAIRSWAP_MASK) { 487ea4efe25SRussell King case MV_PCS_PAIRSWAP_AB: 488ea4efe25SRussell King phydev->mdix = ETH_TP_MDI_X; 489ea4efe25SRussell King break; 490ea4efe25SRussell King case MV_PCS_PAIRSWAP_NONE: 491ea4efe25SRussell King phydev->mdix = ETH_TP_MDI; 492ea4efe25SRussell King break; 493ea4efe25SRussell King default: 494ea4efe25SRussell King phydev->mdix = ETH_TP_MDI_INVALID; 495ea4efe25SRussell King break; 496ea4efe25SRussell King } 497ea4efe25SRussell King } 498ea4efe25SRussell King 49936c4449aSRussell King mv3310_update_interface(phydev); 50020b2af32SRussell King 50120b2af32SRussell King return 0; 50220b2af32SRussell King } 50320b2af32SRussell King 50420b2af32SRussell King static struct phy_driver mv3310_drivers[] = { 50520b2af32SRussell King { 50620b2af32SRussell King .phy_id = 0x002b09aa, 507952b6b3bSAntoine Tenart .phy_id_mask = MARVELL_PHY_ID_MASK, 50820b2af32SRussell King .name = "mv88x3310", 509719655a1SAndrew Lunn .features = PHY_10GBIT_FEATURES, 51056847704SFlorian Fainelli .soft_reset = gen10g_no_soft_reset, 51120b2af32SRussell King .config_init = mv3310_config_init, 5120d3ad854SRussell King .probe = mv3310_probe, 5130d3ad854SRussell King .suspend = mv3310_suspend, 5140d3ad854SRussell King .resume = mv3310_resume, 51520b2af32SRussell King .config_aneg = mv3310_config_aneg, 51620b2af32SRussell King .aneg_done = mv3310_aneg_done, 51720b2af32SRussell King .read_status = mv3310_read_status, 51820b2af32SRussell King }, 51920b2af32SRussell King }; 52020b2af32SRussell King 52120b2af32SRussell King module_phy_driver(mv3310_drivers); 52220b2af32SRussell King 52320b2af32SRussell King static struct mdio_device_id __maybe_unused mv3310_tbl[] = { 524952b6b3bSAntoine Tenart { 0x002b09aa, MARVELL_PHY_ID_MASK }, 52520b2af32SRussell King { }, 52620b2af32SRussell King }; 52720b2af32SRussell King MODULE_DEVICE_TABLE(mdio, mv3310_tbl); 52820b2af32SRussell King MODULE_DESCRIPTION("Marvell Alaska X 10Gigabit Ethernet PHY driver (MV88X3310)"); 52920b2af32SRussell King MODULE_LICENSE("GPL"); 530