1a2443fd1SAndrew Lunn // SPDX-License-Identifier: GPL-2.0+ 220b2af32SRussell King /* 320b2af32SRussell King * Marvell 10G 88x3310 PHY driver 420b2af32SRussell King * 520b2af32SRussell King * Based upon the ID registers, this PHY appears to be a mixture of IPs 620b2af32SRussell King * from two different companies. 720b2af32SRussell King * 820b2af32SRussell King * There appears to be several different data paths through the PHY which 920b2af32SRussell King * are automatically managed by the PHY. The following has been determined 1005ca1b32SRussell King * via observation and experimentation for a setup using single-lane Serdes: 1120b2af32SRussell King * 1220b2af32SRussell King * SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G) 1320b2af32SRussell King * 10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G) 1420b2af32SRussell King * 10GBASE-KR PHYXS -- BASE-R PCS -- Fiber 1520b2af32SRussell King * 1605ca1b32SRussell King * With XAUI, observation shows: 1705ca1b32SRussell King * 1805ca1b32SRussell King * XAUI PHYXS -- <appropriate PCS as above> 1905ca1b32SRussell King * 2005ca1b32SRussell King * and no switching of the host interface mode occurs. 2105ca1b32SRussell King * 2220b2af32SRussell King * If both the fiber and copper ports are connected, the first to gain 2320b2af32SRussell King * link takes priority and the other port is completely locked out. 2420b2af32SRussell King */ 250d3ad854SRussell King #include <linux/ctype.h> 268d8963c3SRussell King #include <linux/delay.h> 270d3ad854SRussell King #include <linux/hwmon.h> 28952b6b3bSAntoine Tenart #include <linux/marvell_phy.h> 290d3ad854SRussell King #include <linux/phy.h> 3036023da1SRussell King #include <linux/sfp.h> 3120b2af32SRussell King 32c47455f9SMaxime Chevallier #define MV_PHY_ALASKA_NBT_QUIRK_MASK 0xfffffffe 33c47455f9SMaxime Chevallier #define MV_PHY_ALASKA_NBT_QUIRK_REV (MARVELL_PHY_ID_88X3310 | 0xa) 34c47455f9SMaxime Chevallier 3520b2af32SRussell King enum { 36dd649b4fSRussell King MV_PMA_FW_VER0 = 0xc011, 37dd649b4fSRussell King MV_PMA_FW_VER1 = 0xc012, 389ab0fbd0SMarek Behún MV_PMA_21X0_PORT_CTRL = 0xc04a, 399ab0fbd0SMarek Behún MV_PMA_21X0_PORT_CTRL_SWRST = BIT(15), 409ab0fbd0SMarek Behún MV_PMA_21X0_PORT_CTRL_MACTYPE_MASK = 0x7, 419ab0fbd0SMarek Behún MV_PMA_21X0_PORT_CTRL_MACTYPE_USXGMII = 0x0, 429ab0fbd0SMarek Behún MV_PMA_2180_PORT_CTRL_MACTYPE_DXGMII = 0x1, 439ab0fbd0SMarek Behún MV_PMA_2180_PORT_CTRL_MACTYPE_QXGMII = 0x2, 449ab0fbd0SMarek Behún MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER = 0x4, 459ab0fbd0SMarek Behún MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER_NO_SGMII_AN = 0x5, 469ab0fbd0SMarek Behún MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH = 0x6, 473d3ced2eSRussell King MV_PMA_BOOT = 0xc050, 483d3ced2eSRussell King MV_PMA_BOOT_FATAL = BIT(0), 493d3ced2eSRussell King 5020b2af32SRussell King MV_PCS_BASE_T = 0x0000, 5120b2af32SRussell King MV_PCS_BASE_R = 0x1000, 5220b2af32SRussell King MV_PCS_1000BASEX = 0x2000, 5320b2af32SRussell King 548d8963c3SRussell King MV_PCS_CSCR1 = 0x8000, 55a585c03eSRussell King MV_PCS_CSCR1_ED_MASK = 0x0300, 56a585c03eSRussell King MV_PCS_CSCR1_ED_OFF = 0x0000, 57a585c03eSRussell King MV_PCS_CSCR1_ED_RX = 0x0200, 58a585c03eSRussell King MV_PCS_CSCR1_ED_NLP = 0x0300, 598d8963c3SRussell King MV_PCS_CSCR1_MDIX_MASK = 0x0060, 608d8963c3SRussell King MV_PCS_CSCR1_MDIX_MDI = 0x0000, 618d8963c3SRussell King MV_PCS_CSCR1_MDIX_MDIX = 0x0020, 628d8963c3SRussell King MV_PCS_CSCR1_MDIX_AUTO = 0x0060, 638d8963c3SRussell King 64c84786faSRussell King MV_PCS_CSSR1 = 0x8008, 65c84786faSRussell King MV_PCS_CSSR1_SPD1_MASK = 0xc000, 66c84786faSRussell King MV_PCS_CSSR1_SPD1_SPD2 = 0xc000, 67c84786faSRussell King MV_PCS_CSSR1_SPD1_1000 = 0x8000, 68c84786faSRussell King MV_PCS_CSSR1_SPD1_100 = 0x4000, 69c84786faSRussell King MV_PCS_CSSR1_SPD1_10 = 0x0000, 70c84786faSRussell King MV_PCS_CSSR1_DUPLEX_FULL= BIT(13), 71c84786faSRussell King MV_PCS_CSSR1_RESOLVED = BIT(11), 72c84786faSRussell King MV_PCS_CSSR1_MDIX = BIT(6), 73c84786faSRussell King MV_PCS_CSSR1_SPD2_MASK = 0x000c, 74c84786faSRussell King MV_PCS_CSSR1_SPD2_5000 = 0x0008, 75c84786faSRussell King MV_PCS_CSSR1_SPD2_2500 = 0x0004, 76c84786faSRussell King MV_PCS_CSSR1_SPD2_10000 = 0x0000, 77ea4efe25SRussell King 78c3e302edSBaruch Siach /* Temperature read register (88E2110 only) */ 79c3e302edSBaruch Siach MV_PCS_TEMP = 0x8042, 80c3e302edSBaruch Siach 81a5de4be0SMarek Behún /* Number of ports on the device */ 82a5de4be0SMarek Behún MV_PCS_PORT_INFO = 0xd00d, 83a5de4be0SMarek Behún MV_PCS_PORT_INFO_NPORTS_MASK = 0x0380, 84a5de4be0SMarek Behún MV_PCS_PORT_INFO_NPORTS_SHIFT = 7, 85a5de4be0SMarek Behún 8620b2af32SRussell King /* These registers appear at 0x800X and 0xa00X - the 0xa00X control 8720b2af32SRussell King * registers appear to set themselves to the 0x800X when AN is 8820b2af32SRussell King * restarted, but status registers appear readable from either. 8920b2af32SRussell King */ 9020b2af32SRussell King MV_AN_CTRL1000 = 0x8000, /* 1000base-T control register */ 9120b2af32SRussell King MV_AN_STAT1000 = 0x8001, /* 1000base-T status register */ 920d3ad854SRussell King 930d3ad854SRussell King /* Vendor2 MMD registers */ 94af3e28cbSAntoine Tenart MV_V2_PORT_CTRL = 0xf001, 958f48c2acSRussell King MV_V2_PORT_CTRL_PWRDOWN = BIT(11), 969893f316SMarek Behún MV_V2_33X0_PORT_CTRL_SWRST = BIT(15), 979893f316SMarek Behún MV_V2_33X0_PORT_CTRL_MACTYPE_MASK = 0x7, 98f8ee45fcSMarek Behún MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI = 0x0, 99f8ee45fcSMarek Behún MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH = 0x1, 100f8ee45fcSMarek Behún MV_V2_3340_PORT_CTRL_MACTYPE_RXAUI_NO_SGMII_AN = 0x1, 101f8ee45fcSMarek Behún MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH = 0x2, 102f8ee45fcSMarek Behún MV_V2_3310_PORT_CTRL_MACTYPE_XAUI = 0x3, 103f8ee45fcSMarek Behún MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER = 0x4, 104f8ee45fcSMarek Behún MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_NO_SGMII_AN = 0x5, 105f8ee45fcSMarek Behún MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH = 0x6, 106f8ee45fcSMarek Behún MV_V2_33X0_PORT_CTRL_MACTYPE_USXGMII = 0x7, 107c3e302edSBaruch Siach /* Temperature control/read registers (88X3310 only) */ 1080d3ad854SRussell King MV_V2_TEMP_CTRL = 0xf08a, 1090d3ad854SRussell King MV_V2_TEMP_CTRL_MASK = 0xc000, 1100d3ad854SRussell King MV_V2_TEMP_CTRL_SAMPLE = 0x0000, 1110d3ad854SRussell King MV_V2_TEMP_CTRL_DISABLE = 0xc000, 1120d3ad854SRussell King MV_V2_TEMP = 0xf08c, 1130d3ad854SRussell King MV_V2_TEMP_UNKNOWN = 0x9600, /* unknown function */ 1140d3ad854SRussell King }; 1150d3ad854SRussell King 11697bbe3bdSMarek Behún struct mv3310_chip { 117261a74c6SMarek Behún void (*init_supported_interfaces)(unsigned long *mask); 11897bbe3bdSMarek Behún int (*get_mactype)(struct phy_device *phydev); 11997bbe3bdSMarek Behún int (*init_interface)(struct phy_device *phydev, int mactype); 120884d9a67SMarek Behún 121884d9a67SMarek Behún #ifdef CONFIG_HWMON 122884d9a67SMarek Behún int (*hwmon_read_temp_reg)(struct phy_device *phydev); 123884d9a67SMarek Behún #endif 12497bbe3bdSMarek Behún }; 12597bbe3bdSMarek Behún 1260d3ad854SRussell King struct mv3310_priv { 127261a74c6SMarek Behún DECLARE_BITMAP(supported_interfaces, PHY_INTERFACE_MODE_MAX); 128261a74c6SMarek Behún 129dd649b4fSRussell King u32 firmware_ver; 130e1170333SBaruch Siach bool rate_match; 13197bbe3bdSMarek Behún phy_interface_t const_interface; 132dd649b4fSRussell King 1330d3ad854SRussell King struct device *hwmon_dev; 1340d3ad854SRussell King char *hwmon_name; 13520b2af32SRussell King }; 13620b2af32SRussell King 13797bbe3bdSMarek Behún static const struct mv3310_chip *to_mv3310_chip(struct phy_device *phydev) 13897bbe3bdSMarek Behún { 13997bbe3bdSMarek Behún return phydev->drv->driver_data; 14097bbe3bdSMarek Behún } 14197bbe3bdSMarek Behún 1420d3ad854SRussell King #ifdef CONFIG_HWMON 1430d3ad854SRussell King static umode_t mv3310_hwmon_is_visible(const void *data, 1440d3ad854SRussell King enum hwmon_sensor_types type, 1450d3ad854SRussell King u32 attr, int channel) 1460d3ad854SRussell King { 1470d3ad854SRussell King if (type == hwmon_chip && attr == hwmon_chip_update_interval) 1480d3ad854SRussell King return 0444; 1490d3ad854SRussell King if (type == hwmon_temp && attr == hwmon_temp_input) 1500d3ad854SRussell King return 0444; 1510d3ad854SRussell King return 0; 1520d3ad854SRussell King } 1530d3ad854SRussell King 154c3e302edSBaruch Siach static int mv3310_hwmon_read_temp_reg(struct phy_device *phydev) 155c3e302edSBaruch Siach { 156c3e302edSBaruch Siach return phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP); 157c3e302edSBaruch Siach } 158c3e302edSBaruch Siach 159c3e302edSBaruch Siach static int mv2110_hwmon_read_temp_reg(struct phy_device *phydev) 160c3e302edSBaruch Siach { 161c3e302edSBaruch Siach return phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_TEMP); 162c3e302edSBaruch Siach } 163c3e302edSBaruch Siach 1640d3ad854SRussell King static int mv3310_hwmon_read(struct device *dev, enum hwmon_sensor_types type, 1650d3ad854SRussell King u32 attr, int channel, long *value) 1660d3ad854SRussell King { 1670d3ad854SRussell King struct phy_device *phydev = dev_get_drvdata(dev); 168884d9a67SMarek Behún const struct mv3310_chip *chip = to_mv3310_chip(phydev); 1690d3ad854SRussell King int temp; 1700d3ad854SRussell King 1710d3ad854SRussell King if (type == hwmon_chip && attr == hwmon_chip_update_interval) { 1720d3ad854SRussell King *value = MSEC_PER_SEC; 1730d3ad854SRussell King return 0; 1740d3ad854SRussell King } 1750d3ad854SRussell King 1760d3ad854SRussell King if (type == hwmon_temp && attr == hwmon_temp_input) { 177884d9a67SMarek Behún temp = chip->hwmon_read_temp_reg(phydev); 1780d3ad854SRussell King if (temp < 0) 1790d3ad854SRussell King return temp; 1800d3ad854SRussell King 1810d3ad854SRussell King *value = ((temp & 0xff) - 75) * 1000; 1820d3ad854SRussell King 1830d3ad854SRussell King return 0; 1840d3ad854SRussell King } 1850d3ad854SRussell King 1860d3ad854SRussell King return -EOPNOTSUPP; 1870d3ad854SRussell King } 1880d3ad854SRussell King 1890d3ad854SRussell King static const struct hwmon_ops mv3310_hwmon_ops = { 1900d3ad854SRussell King .is_visible = mv3310_hwmon_is_visible, 1910d3ad854SRussell King .read = mv3310_hwmon_read, 1920d3ad854SRussell King }; 1930d3ad854SRussell King 1940d3ad854SRussell King static u32 mv3310_hwmon_chip_config[] = { 1950d3ad854SRussell King HWMON_C_REGISTER_TZ | HWMON_C_UPDATE_INTERVAL, 1960d3ad854SRussell King 0, 1970d3ad854SRussell King }; 1980d3ad854SRussell King 1990d3ad854SRussell King static const struct hwmon_channel_info mv3310_hwmon_chip = { 2000d3ad854SRussell King .type = hwmon_chip, 2010d3ad854SRussell King .config = mv3310_hwmon_chip_config, 2020d3ad854SRussell King }; 2030d3ad854SRussell King 2040d3ad854SRussell King static u32 mv3310_hwmon_temp_config[] = { 2050d3ad854SRussell King HWMON_T_INPUT, 2060d3ad854SRussell King 0, 2070d3ad854SRussell King }; 2080d3ad854SRussell King 2090d3ad854SRussell King static const struct hwmon_channel_info mv3310_hwmon_temp = { 2100d3ad854SRussell King .type = hwmon_temp, 2110d3ad854SRussell King .config = mv3310_hwmon_temp_config, 2120d3ad854SRussell King }; 2130d3ad854SRussell King 2140d3ad854SRussell King static const struct hwmon_channel_info *mv3310_hwmon_info[] = { 2150d3ad854SRussell King &mv3310_hwmon_chip, 2160d3ad854SRussell King &mv3310_hwmon_temp, 2170d3ad854SRussell King NULL, 2180d3ad854SRussell King }; 2190d3ad854SRussell King 2200d3ad854SRussell King static const struct hwmon_chip_info mv3310_hwmon_chip_info = { 2210d3ad854SRussell King .ops = &mv3310_hwmon_ops, 2220d3ad854SRussell King .info = mv3310_hwmon_info, 2230d3ad854SRussell King }; 2240d3ad854SRussell King 2250d3ad854SRussell King static int mv3310_hwmon_config(struct phy_device *phydev, bool enable) 2260d3ad854SRussell King { 2270d3ad854SRussell King u16 val; 2280d3ad854SRussell King int ret; 2290d3ad854SRussell King 230c3e302edSBaruch Siach if (phydev->drv->phy_id != MARVELL_PHY_ID_88X3310) 231c3e302edSBaruch Siach return 0; 232c3e302edSBaruch Siach 2330d3ad854SRussell King ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP, 2340d3ad854SRussell King MV_V2_TEMP_UNKNOWN); 2350d3ad854SRussell King if (ret < 0) 2360d3ad854SRussell King return ret; 2370d3ad854SRussell King 2380d3ad854SRussell King val = enable ? MV_V2_TEMP_CTRL_SAMPLE : MV_V2_TEMP_CTRL_DISABLE; 2390d3ad854SRussell King 240b06d8e5aSHeiner Kallweit return phy_modify_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP_CTRL, 241b06d8e5aSHeiner Kallweit MV_V2_TEMP_CTRL_MASK, val); 2420d3ad854SRussell King } 2430d3ad854SRussell King 2440d3ad854SRussell King static int mv3310_hwmon_probe(struct phy_device *phydev) 2450d3ad854SRussell King { 2460d3ad854SRussell King struct device *dev = &phydev->mdio.dev; 2470d3ad854SRussell King struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); 2480d3ad854SRussell King int i, j, ret; 2490d3ad854SRussell King 2500d3ad854SRussell King priv->hwmon_name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL); 2510d3ad854SRussell King if (!priv->hwmon_name) 2520d3ad854SRussell King return -ENODEV; 2530d3ad854SRussell King 2540d3ad854SRussell King for (i = j = 0; priv->hwmon_name[i]; i++) { 2550d3ad854SRussell King if (isalnum(priv->hwmon_name[i])) { 2560d3ad854SRussell King if (i != j) 2570d3ad854SRussell King priv->hwmon_name[j] = priv->hwmon_name[i]; 2580d3ad854SRussell King j++; 2590d3ad854SRussell King } 2600d3ad854SRussell King } 2610d3ad854SRussell King priv->hwmon_name[j] = '\0'; 2620d3ad854SRussell King 2630d3ad854SRussell King ret = mv3310_hwmon_config(phydev, true); 2640d3ad854SRussell King if (ret) 2650d3ad854SRussell King return ret; 2660d3ad854SRussell King 2670d3ad854SRussell King priv->hwmon_dev = devm_hwmon_device_register_with_info(dev, 2680d3ad854SRussell King priv->hwmon_name, phydev, 2690d3ad854SRussell King &mv3310_hwmon_chip_info, NULL); 2700d3ad854SRussell King 2710d3ad854SRussell King return PTR_ERR_OR_ZERO(priv->hwmon_dev); 2720d3ad854SRussell King } 2730d3ad854SRussell King #else 2740d3ad854SRussell King static inline int mv3310_hwmon_config(struct phy_device *phydev, bool enable) 2750d3ad854SRussell King { 2760d3ad854SRussell King return 0; 2770d3ad854SRussell King } 2780d3ad854SRussell King 2790d3ad854SRussell King static int mv3310_hwmon_probe(struct phy_device *phydev) 2800d3ad854SRussell King { 2810d3ad854SRussell King return 0; 2820d3ad854SRussell King } 2830d3ad854SRussell King #endif 2840d3ad854SRussell King 285c9cc1c81SRussell King static int mv3310_power_down(struct phy_device *phydev) 286c9cc1c81SRussell King { 287c9cc1c81SRussell King return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, 288c9cc1c81SRussell King MV_V2_PORT_CTRL_PWRDOWN); 289c9cc1c81SRussell King } 290c9cc1c81SRussell King 291c9cc1c81SRussell King static int mv3310_power_up(struct phy_device *phydev) 292c9cc1c81SRussell King { 2938f48c2acSRussell King struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); 2948f48c2acSRussell King int ret; 2958f48c2acSRussell King 2968f48c2acSRussell King ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, 297c9cc1c81SRussell King MV_V2_PORT_CTRL_PWRDOWN); 2988f48c2acSRussell King 299829e7573SBaruch Siach if (phydev->drv->phy_id != MARVELL_PHY_ID_88X3310 || 300829e7573SBaruch Siach priv->firmware_ver < 0x00030000) 3018f48c2acSRussell King return ret; 3028f48c2acSRussell King 3038f48c2acSRussell King return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, 3049893f316SMarek Behún MV_V2_33X0_PORT_CTRL_SWRST); 305c9cc1c81SRussell King } 306c9cc1c81SRussell King 3078d8963c3SRussell King static int mv3310_reset(struct phy_device *phydev, u32 unit) 3088d8963c3SRussell King { 3098964a217SDejin Zheng int val, err; 3108d8963c3SRussell King 3118d8963c3SRussell King err = phy_modify_mmd(phydev, MDIO_MMD_PCS, unit + MDIO_CTRL1, 3128d8963c3SRussell King MDIO_CTRL1_RESET, MDIO_CTRL1_RESET); 3138d8963c3SRussell King if (err < 0) 3148d8963c3SRussell King return err; 3158d8963c3SRussell King 3168964a217SDejin Zheng return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_PCS, 3178964a217SDejin Zheng unit + MDIO_CTRL1, val, 3188964a217SDejin Zheng !(val & MDIO_CTRL1_RESET), 3198964a217SDejin Zheng 5000, 100000, true); 3208d8963c3SRussell King } 3218d8963c3SRussell King 322a585c03eSRussell King static int mv3310_get_edpd(struct phy_device *phydev, u16 *edpd) 323a585c03eSRussell King { 324a585c03eSRussell King int val; 325a585c03eSRussell King 326a585c03eSRussell King val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1); 327a585c03eSRussell King if (val < 0) 328a585c03eSRussell King return val; 329a585c03eSRussell King 330a585c03eSRussell King switch (val & MV_PCS_CSCR1_ED_MASK) { 331a585c03eSRussell King case MV_PCS_CSCR1_ED_NLP: 332a585c03eSRussell King *edpd = 1000; 333a585c03eSRussell King break; 334a585c03eSRussell King case MV_PCS_CSCR1_ED_RX: 335a585c03eSRussell King *edpd = ETHTOOL_PHY_EDPD_NO_TX; 336a585c03eSRussell King break; 337a585c03eSRussell King default: 338a585c03eSRussell King *edpd = ETHTOOL_PHY_EDPD_DISABLE; 339a585c03eSRussell King break; 340a585c03eSRussell King } 341a585c03eSRussell King return 0; 342a585c03eSRussell King } 343a585c03eSRussell King 344a585c03eSRussell King static int mv3310_set_edpd(struct phy_device *phydev, u16 edpd) 345a585c03eSRussell King { 346a585c03eSRussell King u16 val; 347a585c03eSRussell King int err; 348a585c03eSRussell King 349a585c03eSRussell King switch (edpd) { 350a585c03eSRussell King case 1000: 351a585c03eSRussell King case ETHTOOL_PHY_EDPD_DFLT_TX_MSECS: 352a585c03eSRussell King val = MV_PCS_CSCR1_ED_NLP; 353a585c03eSRussell King break; 354a585c03eSRussell King 355a585c03eSRussell King case ETHTOOL_PHY_EDPD_NO_TX: 356a585c03eSRussell King val = MV_PCS_CSCR1_ED_RX; 357a585c03eSRussell King break; 358a585c03eSRussell King 359a585c03eSRussell King case ETHTOOL_PHY_EDPD_DISABLE: 360a585c03eSRussell King val = MV_PCS_CSCR1_ED_OFF; 361a585c03eSRussell King break; 362a585c03eSRussell King 363a585c03eSRussell King default: 364a585c03eSRussell King return -EINVAL; 365a585c03eSRussell King } 366a585c03eSRussell King 367a585c03eSRussell King err = phy_modify_mmd_changed(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1, 368a585c03eSRussell King MV_PCS_CSCR1_ED_MASK, val); 369a585c03eSRussell King if (err > 0) 370a585c03eSRussell King err = mv3310_reset(phydev, MV_PCS_BASE_T); 371a585c03eSRussell King 372a585c03eSRussell King return err; 373a585c03eSRussell King } 374a585c03eSRussell King 37536023da1SRussell King static int mv3310_sfp_insert(void *upstream, const struct sfp_eeprom_id *id) 37636023da1SRussell King { 37736023da1SRussell King struct phy_device *phydev = upstream; 37836023da1SRussell King __ETHTOOL_DECLARE_LINK_MODE_MASK(support) = { 0, }; 37936023da1SRussell King phy_interface_t iface; 38036023da1SRussell King 38136023da1SRussell King sfp_parse_support(phydev->sfp_bus, id, support); 382a4516c70SRussell King iface = sfp_select_interface(phydev->sfp_bus, support); 38336023da1SRussell King 384e0f909bcSRussell King if (iface != PHY_INTERFACE_MODE_10GBASER) { 38536023da1SRussell King dev_err(&phydev->mdio.dev, "incompatible SFP module inserted\n"); 38636023da1SRussell King return -EINVAL; 38736023da1SRussell King } 38836023da1SRussell King return 0; 38936023da1SRussell King } 39036023da1SRussell King 39136023da1SRussell King static const struct sfp_upstream_ops mv3310_sfp_ops = { 39236023da1SRussell King .attach = phy_sfp_attach, 39336023da1SRussell King .detach = phy_sfp_detach, 39436023da1SRussell King .module_insert = mv3310_sfp_insert, 39536023da1SRussell King }; 39636023da1SRussell King 39720b2af32SRussell King static int mv3310_probe(struct phy_device *phydev) 39820b2af32SRussell King { 399261a74c6SMarek Behún const struct mv3310_chip *chip = to_mv3310_chip(phydev); 4000d3ad854SRussell King struct mv3310_priv *priv; 40120b2af32SRussell King u32 mmd_mask = MDIO_DEVS_PMAPMD | MDIO_DEVS_AN; 4020d3ad854SRussell King int ret; 40320b2af32SRussell King 40420b2af32SRussell King if (!phydev->is_c45 || 40520b2af32SRussell King (phydev->c45_ids.devices_in_package & mmd_mask) != mmd_mask) 40620b2af32SRussell King return -ENODEV; 40720b2af32SRussell King 4083d3ced2eSRussell King ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_BOOT); 4093d3ced2eSRussell King if (ret < 0) 4103d3ced2eSRussell King return ret; 4113d3ced2eSRussell King 4123d3ced2eSRussell King if (ret & MV_PMA_BOOT_FATAL) { 4133d3ced2eSRussell King dev_warn(&phydev->mdio.dev, 4143d3ced2eSRussell King "PHY failed to boot firmware, status=%04x\n", ret); 4153d3ced2eSRussell King return -ENODEV; 4163d3ced2eSRussell King } 4173d3ced2eSRussell King 4180d3ad854SRussell King priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); 4190d3ad854SRussell King if (!priv) 4200d3ad854SRussell King return -ENOMEM; 4210d3ad854SRussell King 4220d3ad854SRussell King dev_set_drvdata(&phydev->mdio.dev, priv); 4230d3ad854SRussell King 424dd649b4fSRussell King ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_FW_VER0); 425dd649b4fSRussell King if (ret < 0) 426dd649b4fSRussell King return ret; 427dd649b4fSRussell King 428dd649b4fSRussell King priv->firmware_ver = ret << 16; 429dd649b4fSRussell King 430dd649b4fSRussell King ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_FW_VER1); 431dd649b4fSRussell King if (ret < 0) 432dd649b4fSRussell King return ret; 433dd649b4fSRussell King 434dd649b4fSRussell King priv->firmware_ver |= ret; 435dd649b4fSRussell King 436dd649b4fSRussell King phydev_info(phydev, "Firmware version %u.%u.%u.%u\n", 437dd649b4fSRussell King priv->firmware_ver >> 24, (priv->firmware_ver >> 16) & 255, 438dd649b4fSRussell King (priv->firmware_ver >> 8) & 255, priv->firmware_ver & 255); 439dd649b4fSRussell King 440c9cc1c81SRussell King /* Powering down the port when not in use saves about 600mW */ 441c9cc1c81SRussell King ret = mv3310_power_down(phydev); 442c9cc1c81SRussell King if (ret) 443c9cc1c81SRussell King return ret; 444c9cc1c81SRussell King 4450d3ad854SRussell King ret = mv3310_hwmon_probe(phydev); 4460d3ad854SRussell King if (ret) 4470d3ad854SRussell King return ret; 4480d3ad854SRussell King 449261a74c6SMarek Behún chip->init_supported_interfaces(priv->supported_interfaces); 450261a74c6SMarek Behún 45136023da1SRussell King return phy_sfp_probe(phydev, &mv3310_sfp_ops); 45220b2af32SRussell King } 45320b2af32SRussell King 4541b8ef142SMarek Behún static void mv3310_remove(struct phy_device *phydev) 4551b8ef142SMarek Behún { 4561b8ef142SMarek Behún mv3310_hwmon_config(phydev, false); 4571b8ef142SMarek Behún } 4581b8ef142SMarek Behún 4590d3ad854SRussell King static int mv3310_suspend(struct phy_device *phydev) 4600d3ad854SRussell King { 461c9cc1c81SRussell King return mv3310_power_down(phydev); 4620d3ad854SRussell King } 4630d3ad854SRussell King 4640d3ad854SRussell King static int mv3310_resume(struct phy_device *phydev) 4650d3ad854SRussell King { 466af3e28cbSAntoine Tenart int ret; 467af3e28cbSAntoine Tenart 468c9cc1c81SRussell King ret = mv3310_power_up(phydev); 469af3e28cbSAntoine Tenart if (ret) 470af3e28cbSAntoine Tenart return ret; 471af3e28cbSAntoine Tenart 4720d3ad854SRussell King return mv3310_hwmon_config(phydev, true); 4730d3ad854SRussell King } 4740d3ad854SRussell King 475c47455f9SMaxime Chevallier /* Some PHYs in the Alaska family such as the 88X3310 and the 88E2010 476c47455f9SMaxime Chevallier * don't set bit 14 in PMA Extended Abilities (1.11), although they do 477c47455f9SMaxime Chevallier * support 2.5GBASET and 5GBASET. For these models, we can still read their 478c47455f9SMaxime Chevallier * 2.5G/5G extended abilities register (1.21). We detect these models based on 479c47455f9SMaxime Chevallier * the PMA device identifier, with a mask matching models known to have this 480c47455f9SMaxime Chevallier * issue 481c47455f9SMaxime Chevallier */ 482c47455f9SMaxime Chevallier static bool mv3310_has_pma_ngbaset_quirk(struct phy_device *phydev) 483c47455f9SMaxime Chevallier { 484c47455f9SMaxime Chevallier if (!(phydev->c45_ids.devices_in_package & MDIO_DEVS_PMAPMD)) 485c47455f9SMaxime Chevallier return false; 486c47455f9SMaxime Chevallier 487c47455f9SMaxime Chevallier /* Only some revisions of the 88X3310 family PMA seem to be impacted */ 488c47455f9SMaxime Chevallier return (phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] & 489c47455f9SMaxime Chevallier MV_PHY_ALASKA_NBT_QUIRK_MASK) == MV_PHY_ALASKA_NBT_QUIRK_REV; 490c47455f9SMaxime Chevallier } 491c47455f9SMaxime Chevallier 49297bbe3bdSMarek Behún static int mv2110_get_mactype(struct phy_device *phydev) 49397bbe3bdSMarek Behún { 49497bbe3bdSMarek Behún int mactype; 49597bbe3bdSMarek Behún 49697bbe3bdSMarek Behún mactype = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_21X0_PORT_CTRL); 49797bbe3bdSMarek Behún if (mactype < 0) 49897bbe3bdSMarek Behún return mactype; 49997bbe3bdSMarek Behún 50097bbe3bdSMarek Behún return mactype & MV_PMA_21X0_PORT_CTRL_MACTYPE_MASK; 50197bbe3bdSMarek Behún } 50297bbe3bdSMarek Behún 50397bbe3bdSMarek Behún static int mv3310_get_mactype(struct phy_device *phydev) 50497bbe3bdSMarek Behún { 50597bbe3bdSMarek Behún int mactype; 50697bbe3bdSMarek Behún 50797bbe3bdSMarek Behún mactype = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL); 50897bbe3bdSMarek Behún if (mactype < 0) 50997bbe3bdSMarek Behún return mactype; 51097bbe3bdSMarek Behún 51197bbe3bdSMarek Behún return mactype & MV_V2_33X0_PORT_CTRL_MACTYPE_MASK; 51297bbe3bdSMarek Behún } 51397bbe3bdSMarek Behún 51497bbe3bdSMarek Behún static int mv2110_init_interface(struct phy_device *phydev, int mactype) 51520b2af32SRussell King { 516e1170333SBaruch Siach struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); 51797bbe3bdSMarek Behún 51897bbe3bdSMarek Behún priv->rate_match = false; 51997bbe3bdSMarek Behún 520ccbf2891SMarek Behún if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH) 52197bbe3bdSMarek Behún priv->rate_match = true; 522ccbf2891SMarek Behún 523ccbf2891SMarek Behún if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_USXGMII) 524ccbf2891SMarek Behún priv->const_interface = PHY_INTERFACE_MODE_USXGMII; 525ccbf2891SMarek Behún else if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH) 52697bbe3bdSMarek Behún priv->const_interface = PHY_INTERFACE_MODE_10GBASER; 527ccbf2891SMarek Behún else if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER || 528ccbf2891SMarek Behún mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER_NO_SGMII_AN) 529ccbf2891SMarek Behún priv->const_interface = PHY_INTERFACE_MODE_NA; 530ccbf2891SMarek Behún else 531ccbf2891SMarek Behún return -EINVAL; 53297bbe3bdSMarek Behún 53397bbe3bdSMarek Behún return 0; 53497bbe3bdSMarek Behún } 53597bbe3bdSMarek Behún 53697bbe3bdSMarek Behún static int mv3310_init_interface(struct phy_device *phydev, int mactype) 53797bbe3bdSMarek Behún { 53897bbe3bdSMarek Behún struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); 53997bbe3bdSMarek Behún 54097bbe3bdSMarek Behún priv->rate_match = false; 54197bbe3bdSMarek Behún 54297bbe3bdSMarek Behún if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH || 54397bbe3bdSMarek Behún mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH || 54497bbe3bdSMarek Behún mactype == MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH) 54597bbe3bdSMarek Behún priv->rate_match = true; 54697bbe3bdSMarek Behún 547ccbf2891SMarek Behún if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_USXGMII) 548ccbf2891SMarek Behún priv->const_interface = PHY_INTERFACE_MODE_USXGMII; 549ccbf2891SMarek Behún else if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH || 550ccbf2891SMarek Behún mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_NO_SGMII_AN || 551ccbf2891SMarek Behún mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER) 55297bbe3bdSMarek Behún priv->const_interface = PHY_INTERFACE_MODE_10GBASER; 553ccbf2891SMarek Behún else if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH || 554ccbf2891SMarek Behún mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI) 55597bbe3bdSMarek Behún priv->const_interface = PHY_INTERFACE_MODE_RXAUI; 556ccbf2891SMarek Behún else if (mactype == MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH || 557ccbf2891SMarek Behún mactype == MV_V2_3310_PORT_CTRL_MACTYPE_XAUI) 55897bbe3bdSMarek Behún priv->const_interface = PHY_INTERFACE_MODE_XAUI; 559ccbf2891SMarek Behún else 560ccbf2891SMarek Behún return -EINVAL; 56197bbe3bdSMarek Behún 56297bbe3bdSMarek Behún return 0; 56397bbe3bdSMarek Behún } 56497bbe3bdSMarek Behún 5659885d016SMarek Behún static int mv3340_init_interface(struct phy_device *phydev, int mactype) 5669885d016SMarek Behún { 5679885d016SMarek Behún struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); 5689885d016SMarek Behún int err = 0; 5699885d016SMarek Behún 5709885d016SMarek Behún priv->rate_match = false; 5719885d016SMarek Behún 5729885d016SMarek Behún if (mactype == MV_V2_3340_PORT_CTRL_MACTYPE_RXAUI_NO_SGMII_AN) 5739885d016SMarek Behún priv->const_interface = PHY_INTERFACE_MODE_RXAUI; 5749885d016SMarek Behún else 5759885d016SMarek Behún err = mv3310_init_interface(phydev, mactype); 5769885d016SMarek Behún 5779885d016SMarek Behún return err; 5789885d016SMarek Behún } 5799885d016SMarek Behún 58097bbe3bdSMarek Behún static int mv3310_config_init(struct phy_device *phydev) 58197bbe3bdSMarek Behún { 582261a74c6SMarek Behún struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); 58397bbe3bdSMarek Behún const struct mv3310_chip *chip = to_mv3310_chip(phydev); 58497bbe3bdSMarek Behún int err, mactype; 585c9cc1c81SRussell King 58620b2af32SRussell King /* Check that the PHY interface type is compatible */ 587261a74c6SMarek Behún if (!test_bit(phydev->interface, priv->supported_interfaces)) 58820b2af32SRussell King return -ENODEV; 58920b2af32SRussell King 5908d8963c3SRussell King phydev->mdix_ctrl = ETH_TP_MDI_AUTO; 5918d8963c3SRussell King 592c9cc1c81SRussell King /* Power up so reset works */ 593c9cc1c81SRussell King err = mv3310_power_up(phydev); 594c9cc1c81SRussell King if (err) 595c9cc1c81SRussell King return err; 596c9cc1c81SRussell King 59797bbe3bdSMarek Behún mactype = chip->get_mactype(phydev); 59897bbe3bdSMarek Behún if (mactype < 0) 59997bbe3bdSMarek Behún return mactype; 60097bbe3bdSMarek Behún 60197bbe3bdSMarek Behún err = chip->init_interface(phydev, mactype); 602ccbf2891SMarek Behún if (err) { 603ccbf2891SMarek Behún phydev_err(phydev, "MACTYPE configuration invalid\n"); 60497bbe3bdSMarek Behún return err; 605ccbf2891SMarek Behún } 606e1170333SBaruch Siach 607a585c03eSRussell King /* Enable EDPD mode - saving 600mW */ 608a585c03eSRussell King return mv3310_set_edpd(phydev, ETHTOOL_PHY_EDPD_DFLT_TX_MSECS); 60974145424SMaxime Chevallier } 61074145424SMaxime Chevallier 61174145424SMaxime Chevallier static int mv3310_get_features(struct phy_device *phydev) 61274145424SMaxime Chevallier { 61374145424SMaxime Chevallier int ret, val; 61474145424SMaxime Chevallier 615ac3f5533SMaxime Chevallier ret = genphy_c45_pma_read_abilities(phydev); 616ac3f5533SMaxime Chevallier if (ret) 617ac3f5533SMaxime Chevallier return ret; 61820b2af32SRussell King 619c47455f9SMaxime Chevallier if (mv3310_has_pma_ngbaset_quirk(phydev)) { 620c47455f9SMaxime Chevallier val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, 621c47455f9SMaxime Chevallier MDIO_PMA_NG_EXTABLE); 622c47455f9SMaxime Chevallier if (val < 0) 623c47455f9SMaxime Chevallier return val; 624c47455f9SMaxime Chevallier 625c47455f9SMaxime Chevallier linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 626c47455f9SMaxime Chevallier phydev->supported, 627c47455f9SMaxime Chevallier val & MDIO_PMA_NG_EXTABLE_2_5GBT); 628c47455f9SMaxime Chevallier 629c47455f9SMaxime Chevallier linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 630c47455f9SMaxime Chevallier phydev->supported, 631c47455f9SMaxime Chevallier val & MDIO_PMA_NG_EXTABLE_5GBT); 632c47455f9SMaxime Chevallier } 633c47455f9SMaxime Chevallier 63420b2af32SRussell King return 0; 63520b2af32SRussell King } 63620b2af32SRussell King 6378d8963c3SRussell King static int mv3310_config_mdix(struct phy_device *phydev) 6388d8963c3SRussell King { 6398d8963c3SRussell King u16 val; 6408d8963c3SRussell King int err; 6418d8963c3SRussell King 6428d8963c3SRussell King switch (phydev->mdix_ctrl) { 6438d8963c3SRussell King case ETH_TP_MDI_AUTO: 6448d8963c3SRussell King val = MV_PCS_CSCR1_MDIX_AUTO; 6458d8963c3SRussell King break; 6468d8963c3SRussell King case ETH_TP_MDI_X: 6478d8963c3SRussell King val = MV_PCS_CSCR1_MDIX_MDIX; 6488d8963c3SRussell King break; 6498d8963c3SRussell King case ETH_TP_MDI: 6508d8963c3SRussell King val = MV_PCS_CSCR1_MDIX_MDI; 6518d8963c3SRussell King break; 6528d8963c3SRussell King default: 6538d8963c3SRussell King return -EINVAL; 6548d8963c3SRussell King } 6558d8963c3SRussell King 6568d8963c3SRussell King err = phy_modify_mmd_changed(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1, 6578d8963c3SRussell King MV_PCS_CSCR1_MDIX_MASK, val); 6588d8963c3SRussell King if (err > 0) 6598d8963c3SRussell King err = mv3310_reset(phydev, MV_PCS_BASE_T); 6608d8963c3SRussell King 6618d8963c3SRussell King return err; 6628d8963c3SRussell King } 6638d8963c3SRussell King 66420b2af32SRussell King static int mv3310_config_aneg(struct phy_device *phydev) 66520b2af32SRussell King { 66620b2af32SRussell King bool changed = false; 6673c1bcc86SAndrew Lunn u16 reg; 66820b2af32SRussell King int ret; 66920b2af32SRussell King 6708d8963c3SRussell King ret = mv3310_config_mdix(phydev); 6718d8963c3SRussell King if (ret < 0) 6728d8963c3SRussell King return ret; 673ea4efe25SRussell King 67430de65c3SHeiner Kallweit if (phydev->autoneg == AUTONEG_DISABLE) 67530de65c3SHeiner Kallweit return genphy_c45_pma_setup_forced(phydev); 67620b2af32SRussell King 6773de97f3cSAndrew Lunn ret = genphy_c45_an_config_aneg(phydev); 67820b2af32SRussell King if (ret < 0) 67920b2af32SRussell King return ret; 68020b2af32SRussell King if (ret > 0) 68120b2af32SRussell King changed = true; 68220b2af32SRussell King 6833de97f3cSAndrew Lunn /* Clause 45 has no standardized support for 1000BaseT, therefore 6843de97f3cSAndrew Lunn * use vendor registers for this mode. 6853de97f3cSAndrew Lunn */ 6863c1bcc86SAndrew Lunn reg = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising); 687b06d8e5aSHeiner Kallweit ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MV_AN_CTRL1000, 6883c1bcc86SAndrew Lunn ADVERTISE_1000FULL | ADVERTISE_1000HALF, reg); 68920b2af32SRussell King if (ret < 0) 69020b2af32SRussell King return ret; 69120b2af32SRussell King if (ret > 0) 69220b2af32SRussell King changed = true; 69320b2af32SRussell King 6946b4cb6cbSHeiner Kallweit return genphy_c45_check_and_restart_aneg(phydev, changed); 69520b2af32SRussell King } 69620b2af32SRussell King 69720b2af32SRussell King static int mv3310_aneg_done(struct phy_device *phydev) 69820b2af32SRussell King { 69920b2af32SRussell King int val; 70020b2af32SRussell King 70120b2af32SRussell King val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1); 70220b2af32SRussell King if (val < 0) 70320b2af32SRussell King return val; 70420b2af32SRussell King 70520b2af32SRussell King if (val & MDIO_STAT1_LSTATUS) 70620b2af32SRussell King return 1; 70720b2af32SRussell King 70820b2af32SRussell King return genphy_c45_aneg_done(phydev); 70920b2af32SRussell King } 71020b2af32SRussell King 71136c4449aSRussell King static void mv3310_update_interface(struct phy_device *phydev) 71236c4449aSRussell King { 713e1170333SBaruch Siach struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); 714e1170333SBaruch Siach 715ccbf2891SMarek Behún if (!phydev->link) 716ccbf2891SMarek Behún return; 717ccbf2891SMarek Behún 71897bbe3bdSMarek Behún /* In all of the "* with Rate Matching" modes the PHY interface is fixed 71997bbe3bdSMarek Behún * at 10Gb. The PHY adapts the rate to actual wire speed with help of 720e1170333SBaruch Siach * internal 16KB buffer. 721ccbf2891SMarek Behún * 722ccbf2891SMarek Behún * In USXGMII mode the PHY interface mode is also fixed. 723e1170333SBaruch Siach */ 724ccbf2891SMarek Behún if (priv->rate_match || 725ccbf2891SMarek Behún priv->const_interface == PHY_INTERFACE_MODE_USXGMII) { 72697bbe3bdSMarek Behún phydev->interface = priv->const_interface; 727e1170333SBaruch Siach return; 728e1170333SBaruch Siach } 729e1170333SBaruch Siach 730ccbf2891SMarek Behún /* The PHY automatically switches its serdes interface (and active PHYXS 731ccbf2891SMarek Behún * instance) between Cisco SGMII, 2500BaseX, 5GBase-R and 10GBase-R / 732ccbf2891SMarek Behún * xaui / rxaui modes according to the speed. 733ccbf2891SMarek Behún * Florian suggests setting phydev->interface to communicate this to the 734ccbf2891SMarek Behún * MAC. Only do this if we are already in one of the above modes. 73536c4449aSRussell King */ 736e555e5b1SMaxime Chevallier switch (phydev->speed) { 737e555e5b1SMaxime Chevallier case SPEED_10000: 738ccbf2891SMarek Behún phydev->interface = priv->const_interface; 739e555e5b1SMaxime Chevallier break; 7400d375542SMarek Behún case SPEED_5000: 7410d375542SMarek Behún phydev->interface = PHY_INTERFACE_MODE_5GBASER; 7420d375542SMarek Behún break; 743e555e5b1SMaxime Chevallier case SPEED_2500: 744e555e5b1SMaxime Chevallier phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 745e555e5b1SMaxime Chevallier break; 746e555e5b1SMaxime Chevallier case SPEED_1000: 747e555e5b1SMaxime Chevallier case SPEED_100: 748e555e5b1SMaxime Chevallier case SPEED_10: 74936c4449aSRussell King phydev->interface = PHY_INTERFACE_MODE_SGMII; 750e555e5b1SMaxime Chevallier break; 751e555e5b1SMaxime Chevallier default: 752e555e5b1SMaxime Chevallier break; 753e555e5b1SMaxime Chevallier } 75436c4449aSRussell King } 75536c4449aSRussell King 75620b2af32SRussell King /* 10GBASE-ER,LR,LRM,SR do not support autonegotiation. */ 757c84786faSRussell King static int mv3310_read_status_10gbaser(struct phy_device *phydev) 75820b2af32SRussell King { 75920b2af32SRussell King phydev->link = 1; 76020b2af32SRussell King phydev->speed = SPEED_10000; 76120b2af32SRussell King phydev->duplex = DUPLEX_FULL; 7624217a64eSMichael Walle phydev->port = PORT_FIBRE; 76320b2af32SRussell King 76420b2af32SRussell King return 0; 76520b2af32SRussell King } 76620b2af32SRussell King 767c84786faSRussell King static int mv3310_read_status_copper(struct phy_device *phydev) 76820b2af32SRussell King { 769c84786faSRussell King int cssr1, speed, val; 77020b2af32SRussell King 771998a8a83SHeiner Kallweit val = genphy_c45_read_link(phydev); 77220b2af32SRussell King if (val < 0) 77320b2af32SRussell King return val; 77420b2af32SRussell King 77520b2af32SRussell King val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); 77620b2af32SRussell King if (val < 0) 77720b2af32SRussell King return val; 77820b2af32SRussell King 779c84786faSRussell King cssr1 = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_CSSR1); 780c84786faSRussell King if (cssr1 < 0) 781c84786faSRussell King return val; 782c84786faSRussell King 783c84786faSRussell King /* If the link settings are not resolved, mark the link down */ 784c84786faSRussell King if (!(cssr1 & MV_PCS_CSSR1_RESOLVED)) { 785c84786faSRussell King phydev->link = 0; 786c84786faSRussell King return 0; 787c84786faSRussell King } 788c84786faSRussell King 789c84786faSRussell King /* Read the copper link settings */ 790c84786faSRussell King speed = cssr1 & MV_PCS_CSSR1_SPD1_MASK; 791c84786faSRussell King if (speed == MV_PCS_CSSR1_SPD1_SPD2) 792c84786faSRussell King speed |= cssr1 & MV_PCS_CSSR1_SPD2_MASK; 793c84786faSRussell King 794c84786faSRussell King switch (speed) { 795c84786faSRussell King case MV_PCS_CSSR1_SPD1_SPD2 | MV_PCS_CSSR1_SPD2_10000: 796c84786faSRussell King phydev->speed = SPEED_10000; 797c84786faSRussell King break; 798c84786faSRussell King 799c84786faSRussell King case MV_PCS_CSSR1_SPD1_SPD2 | MV_PCS_CSSR1_SPD2_5000: 800c84786faSRussell King phydev->speed = SPEED_5000; 801c84786faSRussell King break; 802c84786faSRussell King 803c84786faSRussell King case MV_PCS_CSSR1_SPD1_SPD2 | MV_PCS_CSSR1_SPD2_2500: 804c84786faSRussell King phydev->speed = SPEED_2500; 805c84786faSRussell King break; 806c84786faSRussell King 807c84786faSRussell King case MV_PCS_CSSR1_SPD1_1000: 808c84786faSRussell King phydev->speed = SPEED_1000; 809c84786faSRussell King break; 810c84786faSRussell King 811c84786faSRussell King case MV_PCS_CSSR1_SPD1_100: 812c84786faSRussell King phydev->speed = SPEED_100; 813c84786faSRussell King break; 814c84786faSRussell King 815c84786faSRussell King case MV_PCS_CSSR1_SPD1_10: 816c84786faSRussell King phydev->speed = SPEED_10; 817c84786faSRussell King break; 818c84786faSRussell King } 819c84786faSRussell King 820c84786faSRussell King phydev->duplex = cssr1 & MV_PCS_CSSR1_DUPLEX_FULL ? 821c84786faSRussell King DUPLEX_FULL : DUPLEX_HALF; 8224217a64eSMichael Walle phydev->port = PORT_TP; 823c84786faSRussell King phydev->mdix = cssr1 & MV_PCS_CSSR1_MDIX ? 824c84786faSRussell King ETH_TP_MDI_X : ETH_TP_MDI; 825c84786faSRussell King 82620b2af32SRussell King if (val & MDIO_AN_STAT1_COMPLETE) { 82720b2af32SRussell King val = genphy_c45_read_lpa(phydev); 82820b2af32SRussell King if (val < 0) 82920b2af32SRussell King return val; 83020b2af32SRussell King 831cc1122b0SColin Ian King /* Read the link partner's 1G advertisement */ 83220b2af32SRussell King val = phy_read_mmd(phydev, MDIO_MMD_AN, MV_AN_STAT1000); 83320b2af32SRussell King if (val < 0) 83420b2af32SRussell King return val; 83520b2af32SRussell King 83678a24df3SAndrew Lunn mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val); 83720b2af32SRussell King 838c84786faSRussell King /* Update the pause status */ 839c84786faSRussell King phy_resolve_aneg_pause(phydev); 84020b2af32SRussell King } 84120b2af32SRussell King 842c84786faSRussell King return 0; 84320b2af32SRussell King } 84420b2af32SRussell King 845c84786faSRussell King static int mv3310_read_status(struct phy_device *phydev) 846c84786faSRussell King { 847c84786faSRussell King int err, val; 848ea4efe25SRussell King 849c84786faSRussell King phydev->speed = SPEED_UNKNOWN; 850c84786faSRussell King phydev->duplex = DUPLEX_UNKNOWN; 851c84786faSRussell King linkmode_zero(phydev->lp_advertising); 852c84786faSRussell King phydev->link = 0; 853c84786faSRussell King phydev->pause = 0; 854c84786faSRussell King phydev->asym_pause = 0; 855ea4efe25SRussell King phydev->mdix = ETH_TP_MDI_INVALID; 856ea4efe25SRussell King 857c84786faSRussell King val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1); 858c84786faSRussell King if (val < 0) 859c84786faSRussell King return val; 860c84786faSRussell King 861c84786faSRussell King if (val & MDIO_STAT1_LSTATUS) 862c84786faSRussell King err = mv3310_read_status_10gbaser(phydev); 863c84786faSRussell King else 864c84786faSRussell King err = mv3310_read_status_copper(phydev); 865c84786faSRussell King if (err < 0) 866c84786faSRussell King return err; 867c84786faSRussell King 868c84786faSRussell King if (phydev->link) 86936c4449aSRussell King mv3310_update_interface(phydev); 87020b2af32SRussell King 87120b2af32SRussell King return 0; 87220b2af32SRussell King } 87320b2af32SRussell King 874a585c03eSRussell King static int mv3310_get_tunable(struct phy_device *phydev, 875a585c03eSRussell King struct ethtool_tunable *tuna, void *data) 876a585c03eSRussell King { 877a585c03eSRussell King switch (tuna->id) { 878a585c03eSRussell King case ETHTOOL_PHY_EDPD: 879a585c03eSRussell King return mv3310_get_edpd(phydev, data); 880a585c03eSRussell King default: 881a585c03eSRussell King return -EOPNOTSUPP; 882a585c03eSRussell King } 883a585c03eSRussell King } 884a585c03eSRussell King 885a585c03eSRussell King static int mv3310_set_tunable(struct phy_device *phydev, 886a585c03eSRussell King struct ethtool_tunable *tuna, const void *data) 887a585c03eSRussell King { 888a585c03eSRussell King switch (tuna->id) { 889a585c03eSRussell King case ETHTOOL_PHY_EDPD: 890a585c03eSRussell King return mv3310_set_edpd(phydev, *(u16 *)data); 891a585c03eSRussell King default: 892a585c03eSRussell King return -EOPNOTSUPP; 893a585c03eSRussell King } 894a585c03eSRussell King } 895a585c03eSRussell King 896261a74c6SMarek Behún static void mv3310_init_supported_interfaces(unsigned long *mask) 897261a74c6SMarek Behún { 898261a74c6SMarek Behún __set_bit(PHY_INTERFACE_MODE_SGMII, mask); 899261a74c6SMarek Behún __set_bit(PHY_INTERFACE_MODE_2500BASEX, mask); 900261a74c6SMarek Behún __set_bit(PHY_INTERFACE_MODE_5GBASER, mask); 901261a74c6SMarek Behún __set_bit(PHY_INTERFACE_MODE_XAUI, mask); 902261a74c6SMarek Behún __set_bit(PHY_INTERFACE_MODE_RXAUI, mask); 903261a74c6SMarek Behún __set_bit(PHY_INTERFACE_MODE_10GBASER, mask); 904261a74c6SMarek Behún __set_bit(PHY_INTERFACE_MODE_USXGMII, mask); 905261a74c6SMarek Behún } 906261a74c6SMarek Behún 9079885d016SMarek Behún static void mv3340_init_supported_interfaces(unsigned long *mask) 9089885d016SMarek Behún { 9099885d016SMarek Behún __set_bit(PHY_INTERFACE_MODE_SGMII, mask); 9109885d016SMarek Behún __set_bit(PHY_INTERFACE_MODE_2500BASEX, mask); 9119885d016SMarek Behún __set_bit(PHY_INTERFACE_MODE_5GBASER, mask); 9129885d016SMarek Behún __set_bit(PHY_INTERFACE_MODE_RXAUI, mask); 9139885d016SMarek Behún __set_bit(PHY_INTERFACE_MODE_10GBASER, mask); 9149885d016SMarek Behún __set_bit(PHY_INTERFACE_MODE_USXGMII, mask); 9159885d016SMarek Behún } 9169885d016SMarek Behún 917261a74c6SMarek Behún static void mv2110_init_supported_interfaces(unsigned long *mask) 918261a74c6SMarek Behún { 919261a74c6SMarek Behún __set_bit(PHY_INTERFACE_MODE_SGMII, mask); 920261a74c6SMarek Behún __set_bit(PHY_INTERFACE_MODE_2500BASEX, mask); 921261a74c6SMarek Behún __set_bit(PHY_INTERFACE_MODE_5GBASER, mask); 922261a74c6SMarek Behún __set_bit(PHY_INTERFACE_MODE_10GBASER, mask); 923261a74c6SMarek Behún __set_bit(PHY_INTERFACE_MODE_USXGMII, mask); 924261a74c6SMarek Behún } 925261a74c6SMarek Behún 9260fca947cSMarek Behún static void mv2111_init_supported_interfaces(unsigned long *mask) 9270fca947cSMarek Behún { 9280fca947cSMarek Behún __set_bit(PHY_INTERFACE_MODE_SGMII, mask); 9290fca947cSMarek Behún __set_bit(PHY_INTERFACE_MODE_2500BASEX, mask); 9300fca947cSMarek Behún __set_bit(PHY_INTERFACE_MODE_10GBASER, mask); 9310fca947cSMarek Behún __set_bit(PHY_INTERFACE_MODE_USXGMII, mask); 9320fca947cSMarek Behún } 9330fca947cSMarek Behún 93497bbe3bdSMarek Behún static const struct mv3310_chip mv3310_type = { 935261a74c6SMarek Behún .init_supported_interfaces = mv3310_init_supported_interfaces, 93697bbe3bdSMarek Behún .get_mactype = mv3310_get_mactype, 93797bbe3bdSMarek Behún .init_interface = mv3310_init_interface, 938884d9a67SMarek Behún 939884d9a67SMarek Behún #ifdef CONFIG_HWMON 940884d9a67SMarek Behún .hwmon_read_temp_reg = mv3310_hwmon_read_temp_reg, 941884d9a67SMarek Behún #endif 94297bbe3bdSMarek Behún }; 94397bbe3bdSMarek Behún 9449885d016SMarek Behún static const struct mv3310_chip mv3340_type = { 9459885d016SMarek Behún .init_supported_interfaces = mv3340_init_supported_interfaces, 9469885d016SMarek Behún .get_mactype = mv3310_get_mactype, 9479885d016SMarek Behún .init_interface = mv3340_init_interface, 9489885d016SMarek Behún 9499885d016SMarek Behún #ifdef CONFIG_HWMON 9509885d016SMarek Behún .hwmon_read_temp_reg = mv3310_hwmon_read_temp_reg, 9519885d016SMarek Behún #endif 9529885d016SMarek Behún }; 9539885d016SMarek Behún 95497bbe3bdSMarek Behún static const struct mv3310_chip mv2110_type = { 955261a74c6SMarek Behún .init_supported_interfaces = mv2110_init_supported_interfaces, 95697bbe3bdSMarek Behún .get_mactype = mv2110_get_mactype, 95797bbe3bdSMarek Behún .init_interface = mv2110_init_interface, 958884d9a67SMarek Behún 959884d9a67SMarek Behún #ifdef CONFIG_HWMON 960884d9a67SMarek Behún .hwmon_read_temp_reg = mv2110_hwmon_read_temp_reg, 961884d9a67SMarek Behún #endif 96297bbe3bdSMarek Behún }; 96397bbe3bdSMarek Behún 9640fca947cSMarek Behún static const struct mv3310_chip mv2111_type = { 9650fca947cSMarek Behún .init_supported_interfaces = mv2111_init_supported_interfaces, 9660fca947cSMarek Behún .get_mactype = mv2110_get_mactype, 9670fca947cSMarek Behún .init_interface = mv2110_init_interface, 9680fca947cSMarek Behún 9690fca947cSMarek Behún #ifdef CONFIG_HWMON 9700fca947cSMarek Behún .hwmon_read_temp_reg = mv2110_hwmon_read_temp_reg, 9710fca947cSMarek Behún #endif 9720fca947cSMarek Behún }; 9730fca947cSMarek Behún 974a5de4be0SMarek Behún static int mv3310_get_number_of_ports(struct phy_device *phydev) 975a5de4be0SMarek Behún { 976a5de4be0SMarek Behún int ret; 977a5de4be0SMarek Behún 978a5de4be0SMarek Behún ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_PORT_INFO); 979a5de4be0SMarek Behún if (ret < 0) 980a5de4be0SMarek Behún return ret; 981a5de4be0SMarek Behún 982a5de4be0SMarek Behún ret &= MV_PCS_PORT_INFO_NPORTS_MASK; 983a5de4be0SMarek Behún ret >>= MV_PCS_PORT_INFO_NPORTS_SHIFT; 984a5de4be0SMarek Behún 985a5de4be0SMarek Behún return ret + 1; 986a5de4be0SMarek Behún } 987a5de4be0SMarek Behún 988a5de4be0SMarek Behún static int mv3310_match_phy_device(struct phy_device *phydev) 989a5de4be0SMarek Behún { 990*0d55649dSVladimir Oltean if ((phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] & 991*0d55649dSVladimir Oltean MARVELL_PHY_ID_MASK) != MARVELL_PHY_ID_88X3310) 992*0d55649dSVladimir Oltean return 0; 993*0d55649dSVladimir Oltean 994a5de4be0SMarek Behún return mv3310_get_number_of_ports(phydev) == 1; 995a5de4be0SMarek Behún } 996a5de4be0SMarek Behún 997a5de4be0SMarek Behún static int mv3340_match_phy_device(struct phy_device *phydev) 998a5de4be0SMarek Behún { 999*0d55649dSVladimir Oltean if ((phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] & 1000*0d55649dSVladimir Oltean MARVELL_PHY_ID_MASK) != MARVELL_PHY_ID_88X3310) 1001*0d55649dSVladimir Oltean return 0; 1002*0d55649dSVladimir Oltean 1003a5de4be0SMarek Behún return mv3310_get_number_of_ports(phydev) == 4; 1004a5de4be0SMarek Behún } 1005a5de4be0SMarek Behún 10060fca947cSMarek Behún static int mv211x_match_phy_device(struct phy_device *phydev, bool has_5g) 10070fca947cSMarek Behún { 10080fca947cSMarek Behún int val; 10090fca947cSMarek Behún 10100fca947cSMarek Behún if ((phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] & 10110fca947cSMarek Behún MARVELL_PHY_ID_MASK) != MARVELL_PHY_ID_88E2110) 10120fca947cSMarek Behún return 0; 10130fca947cSMarek Behún 10140fca947cSMarek Behún val = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_SPEED); 10150fca947cSMarek Behún if (val < 0) 10160fca947cSMarek Behún return val; 10170fca947cSMarek Behún 10180fca947cSMarek Behún return !!(val & MDIO_PCS_SPEED_5G) == has_5g; 10190fca947cSMarek Behún } 10200fca947cSMarek Behún 10210fca947cSMarek Behún static int mv2110_match_phy_device(struct phy_device *phydev) 10220fca947cSMarek Behún { 10230fca947cSMarek Behún return mv211x_match_phy_device(phydev, true); 10240fca947cSMarek Behún } 10250fca947cSMarek Behún 10260fca947cSMarek Behún static int mv2111_match_phy_device(struct phy_device *phydev) 10270fca947cSMarek Behún { 10280fca947cSMarek Behún return mv211x_match_phy_device(phydev, false); 10290fca947cSMarek Behún } 10300fca947cSMarek Behún 103120b2af32SRussell King static struct phy_driver mv3310_drivers[] = { 103220b2af32SRussell King { 1033631ba906SMaxime Chevallier .phy_id = MARVELL_PHY_ID_88X3310, 1034a5de4be0SMarek Behún .phy_id_mask = MARVELL_PHY_ID_MASK, 1035a5de4be0SMarek Behún .match_phy_device = mv3310_match_phy_device, 103620b2af32SRussell King .name = "mv88x3310", 103797bbe3bdSMarek Behún .driver_data = &mv3310_type, 103874145424SMaxime Chevallier .get_features = mv3310_get_features, 103920b2af32SRussell King .config_init = mv3310_config_init, 10400d3ad854SRussell King .probe = mv3310_probe, 10410d3ad854SRussell King .suspend = mv3310_suspend, 10420d3ad854SRussell King .resume = mv3310_resume, 104320b2af32SRussell King .config_aneg = mv3310_config_aneg, 104420b2af32SRussell King .aneg_done = mv3310_aneg_done, 104520b2af32SRussell King .read_status = mv3310_read_status, 1046a585c03eSRussell King .get_tunable = mv3310_get_tunable, 1047a585c03eSRussell King .set_tunable = mv3310_set_tunable, 10481b8ef142SMarek Behún .remove = mv3310_remove, 1049d137c70dSWong Vee Khee .set_loopback = genphy_c45_loopback, 105020b2af32SRussell King }, 105162d01535SMaxime Chevallier { 1052a5de4be0SMarek Behún .phy_id = MARVELL_PHY_ID_88X3310, 1053a5de4be0SMarek Behún .phy_id_mask = MARVELL_PHY_ID_MASK, 1054a5de4be0SMarek Behún .match_phy_device = mv3340_match_phy_device, 10559885d016SMarek Behún .name = "mv88x3340", 10569885d016SMarek Behún .driver_data = &mv3340_type, 10579885d016SMarek Behún .get_features = mv3310_get_features, 10589885d016SMarek Behún .config_init = mv3310_config_init, 10599885d016SMarek Behún .probe = mv3310_probe, 10609885d016SMarek Behún .suspend = mv3310_suspend, 10619885d016SMarek Behún .resume = mv3310_resume, 10629885d016SMarek Behún .config_aneg = mv3310_config_aneg, 10639885d016SMarek Behún .aneg_done = mv3310_aneg_done, 10649885d016SMarek Behún .read_status = mv3310_read_status, 10659885d016SMarek Behún .get_tunable = mv3310_get_tunable, 10669885d016SMarek Behún .set_tunable = mv3310_set_tunable, 10679885d016SMarek Behún .remove = mv3310_remove, 10689885d016SMarek Behún .set_loopback = genphy_c45_loopback, 10699885d016SMarek Behún }, 10709885d016SMarek Behún { 107162d01535SMaxime Chevallier .phy_id = MARVELL_PHY_ID_88E2110, 107262d01535SMaxime Chevallier .phy_id_mask = MARVELL_PHY_ID_MASK, 10730fca947cSMarek Behún .match_phy_device = mv2110_match_phy_device, 1074c89f27d4SMarek Behún .name = "mv88e2110", 107597bbe3bdSMarek Behún .driver_data = &mv2110_type, 107662d01535SMaxime Chevallier .probe = mv3310_probe, 1077e02c4a9dSAntoine Tenart .suspend = mv3310_suspend, 1078e02c4a9dSAntoine Tenart .resume = mv3310_resume, 107962d01535SMaxime Chevallier .config_init = mv3310_config_init, 108062d01535SMaxime Chevallier .config_aneg = mv3310_config_aneg, 108162d01535SMaxime Chevallier .aneg_done = mv3310_aneg_done, 108262d01535SMaxime Chevallier .read_status = mv3310_read_status, 1083a585c03eSRussell King .get_tunable = mv3310_get_tunable, 1084a585c03eSRussell King .set_tunable = mv3310_set_tunable, 10851b8ef142SMarek Behún .remove = mv3310_remove, 1086d137c70dSWong Vee Khee .set_loopback = genphy_c45_loopback, 108762d01535SMaxime Chevallier }, 10880fca947cSMarek Behún { 10890fca947cSMarek Behún .phy_id = MARVELL_PHY_ID_88E2110, 10900fca947cSMarek Behún .phy_id_mask = MARVELL_PHY_ID_MASK, 10910fca947cSMarek Behún .match_phy_device = mv2111_match_phy_device, 10920fca947cSMarek Behún .name = "mv88e2111", 10930fca947cSMarek Behún .driver_data = &mv2111_type, 10940fca947cSMarek Behún .probe = mv3310_probe, 10950fca947cSMarek Behún .suspend = mv3310_suspend, 10960fca947cSMarek Behún .resume = mv3310_resume, 10970fca947cSMarek Behún .config_init = mv3310_config_init, 10980fca947cSMarek Behún .config_aneg = mv3310_config_aneg, 10990fca947cSMarek Behún .aneg_done = mv3310_aneg_done, 11000fca947cSMarek Behún .read_status = mv3310_read_status, 11010fca947cSMarek Behún .get_tunable = mv3310_get_tunable, 11020fca947cSMarek Behún .set_tunable = mv3310_set_tunable, 11030fca947cSMarek Behún .remove = mv3310_remove, 11040fca947cSMarek Behún .set_loopback = genphy_c45_loopback, 11050fca947cSMarek Behún }, 110620b2af32SRussell King }; 110720b2af32SRussell King 110820b2af32SRussell King module_phy_driver(mv3310_drivers); 110920b2af32SRussell King 111020b2af32SRussell King static struct mdio_device_id __maybe_unused mv3310_tbl[] = { 1111a5de4be0SMarek Behún { MARVELL_PHY_ID_88X3310, MARVELL_PHY_ID_MASK }, 111262d01535SMaxime Chevallier { MARVELL_PHY_ID_88E2110, MARVELL_PHY_ID_MASK }, 111320b2af32SRussell King { }, 111420b2af32SRussell King }; 111520b2af32SRussell King MODULE_DEVICE_TABLE(mdio, mv3310_tbl); 1116c7dce05eSMarek Behún MODULE_DESCRIPTION("Marvell Alaska X/M multi-gigabit Ethernet PHY driver"); 111720b2af32SRussell King MODULE_LICENSE("GPL"); 1118