1 /* 2 * drivers/net/phy/marvell.c 3 * 4 * Driver for Marvell PHYs 5 * 6 * Author: Andy Fleming 7 * 8 * Copyright (c) 2004 Freescale Semiconductor, Inc. 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License as published by the 12 * Free Software Foundation; either version 2 of the License, or (at your 13 * option) any later version. 14 * 15 */ 16 #include <linux/kernel.h> 17 #include <linux/string.h> 18 #include <linux/errno.h> 19 #include <linux/unistd.h> 20 #include <linux/slab.h> 21 #include <linux/interrupt.h> 22 #include <linux/init.h> 23 #include <linux/delay.h> 24 #include <linux/netdevice.h> 25 #include <linux/etherdevice.h> 26 #include <linux/skbuff.h> 27 #include <linux/spinlock.h> 28 #include <linux/mm.h> 29 #include <linux/module.h> 30 #include <linux/mii.h> 31 #include <linux/ethtool.h> 32 #include <linux/phy.h> 33 34 #include <asm/io.h> 35 #include <asm/irq.h> 36 #include <asm/uaccess.h> 37 38 #define MII_M1011_IEVENT 0x13 39 #define MII_M1011_IEVENT_CLEAR 0x0000 40 41 #define MII_M1011_IMASK 0x12 42 #define MII_M1011_IMASK_INIT 0x6400 43 #define MII_M1011_IMASK_CLEAR 0x0000 44 45 #define MII_M1011_PHY_SCR 0x10 46 #define MII_M1011_PHY_SCR_AUTO_CROSS 0x0060 47 48 #define MII_M1145_PHY_EXT_CR 0x14 49 #define MII_M1145_RGMII_RX_DELAY 0x0080 50 #define MII_M1145_RGMII_TX_DELAY 0x0002 51 52 #define M1145_DEV_FLAGS_RESISTANCE 0x00000001 53 54 #define MII_M1111_PHY_LED_CONTROL 0x18 55 #define MII_M1111_PHY_LED_DIRECT 0x4100 56 #define MII_M1111_PHY_LED_COMBINE 0x411c 57 #define MII_M1111_PHY_EXT_CR 0x14 58 #define MII_M1111_RX_DELAY 0x80 59 #define MII_M1111_TX_DELAY 0x2 60 #define MII_M1111_PHY_EXT_SR 0x1b 61 62 #define MII_M1111_HWCFG_MODE_MASK 0xf 63 #define MII_M1111_HWCFG_MODE_COPPER_RGMII 0xb 64 #define MII_M1111_HWCFG_MODE_FIBER_RGMII 0x3 65 #define MII_M1111_HWCFG_MODE_SGMII_NO_CLK 0x4 66 #define MII_M1111_HWCFG_FIBER_COPPER_AUTO 0x8000 67 #define MII_M1111_HWCFG_FIBER_COPPER_RES 0x2000 68 69 #define MII_M1111_COPPER 0 70 #define MII_M1111_FIBER 1 71 72 #define MII_88E1121_PHY_LED_CTRL 16 73 #define MII_88E1121_PHY_LED_PAGE 3 74 #define MII_88E1121_PHY_LED_DEF 0x0030 75 #define MII_88E1121_PHY_PAGE 22 76 77 #define MII_M1011_PHY_STATUS 0x11 78 #define MII_M1011_PHY_STATUS_1000 0x8000 79 #define MII_M1011_PHY_STATUS_100 0x4000 80 #define MII_M1011_PHY_STATUS_SPD_MASK 0xc000 81 #define MII_M1011_PHY_STATUS_FULLDUPLEX 0x2000 82 #define MII_M1011_PHY_STATUS_RESOLVED 0x0800 83 #define MII_M1011_PHY_STATUS_LINK 0x0400 84 85 86 MODULE_DESCRIPTION("Marvell PHY driver"); 87 MODULE_AUTHOR("Andy Fleming"); 88 MODULE_LICENSE("GPL"); 89 90 static int marvell_ack_interrupt(struct phy_device *phydev) 91 { 92 int err; 93 94 /* Clear the interrupts by reading the reg */ 95 err = phy_read(phydev, MII_M1011_IEVENT); 96 97 if (err < 0) 98 return err; 99 100 return 0; 101 } 102 103 static int marvell_config_intr(struct phy_device *phydev) 104 { 105 int err; 106 107 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) 108 err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_INIT); 109 else 110 err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR); 111 112 return err; 113 } 114 115 static int marvell_config_aneg(struct phy_device *phydev) 116 { 117 int err; 118 119 /* The Marvell PHY has an errata which requires 120 * that certain registers get written in order 121 * to restart autonegotiation */ 122 err = phy_write(phydev, MII_BMCR, BMCR_RESET); 123 124 if (err < 0) 125 return err; 126 127 err = phy_write(phydev, 0x1d, 0x1f); 128 if (err < 0) 129 return err; 130 131 err = phy_write(phydev, 0x1e, 0x200c); 132 if (err < 0) 133 return err; 134 135 err = phy_write(phydev, 0x1d, 0x5); 136 if (err < 0) 137 return err; 138 139 err = phy_write(phydev, 0x1e, 0); 140 if (err < 0) 141 return err; 142 143 err = phy_write(phydev, 0x1e, 0x100); 144 if (err < 0) 145 return err; 146 147 err = phy_write(phydev, MII_M1011_PHY_SCR, 148 MII_M1011_PHY_SCR_AUTO_CROSS); 149 if (err < 0) 150 return err; 151 152 err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL, 153 MII_M1111_PHY_LED_DIRECT); 154 if (err < 0) 155 return err; 156 157 err = genphy_config_aneg(phydev); 158 if (err < 0) 159 return err; 160 161 if (phydev->autoneg != AUTONEG_ENABLE) { 162 int bmcr; 163 164 /* 165 * A write to speed/duplex bits (that is performed by 166 * genphy_config_aneg() call above) must be followed by 167 * a software reset. Otherwise, the write has no effect. 168 */ 169 bmcr = phy_read(phydev, MII_BMCR); 170 if (bmcr < 0) 171 return bmcr; 172 173 err = phy_write(phydev, MII_BMCR, bmcr | BMCR_RESET); 174 if (err < 0) 175 return err; 176 } 177 178 return 0; 179 } 180 181 static int m88e1121_config_aneg(struct phy_device *phydev) 182 { 183 int err, temp; 184 185 err = phy_write(phydev, MII_BMCR, BMCR_RESET); 186 if (err < 0) 187 return err; 188 189 err = phy_write(phydev, MII_M1011_PHY_SCR, 190 MII_M1011_PHY_SCR_AUTO_CROSS); 191 if (err < 0) 192 return err; 193 194 temp = phy_read(phydev, MII_88E1121_PHY_PAGE); 195 196 phy_write(phydev, MII_88E1121_PHY_PAGE, MII_88E1121_PHY_LED_PAGE); 197 phy_write(phydev, MII_88E1121_PHY_LED_CTRL, MII_88E1121_PHY_LED_DEF); 198 phy_write(phydev, MII_88E1121_PHY_PAGE, temp); 199 200 err = genphy_config_aneg(phydev); 201 202 return err; 203 } 204 205 static int m88e1111_config_init(struct phy_device *phydev) 206 { 207 int err; 208 int temp; 209 210 /* Enable Fiber/Copper auto selection */ 211 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR); 212 temp &= ~MII_M1111_HWCFG_FIBER_COPPER_AUTO; 213 phy_write(phydev, MII_M1111_PHY_EXT_SR, temp); 214 215 temp = phy_read(phydev, MII_BMCR); 216 temp |= BMCR_RESET; 217 phy_write(phydev, MII_BMCR, temp); 218 219 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) || 220 (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) || 221 (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) || 222 (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) { 223 224 temp = phy_read(phydev, MII_M1111_PHY_EXT_CR); 225 if (temp < 0) 226 return temp; 227 228 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) { 229 temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY); 230 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) { 231 temp &= ~MII_M1111_TX_DELAY; 232 temp |= MII_M1111_RX_DELAY; 233 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) { 234 temp &= ~MII_M1111_RX_DELAY; 235 temp |= MII_M1111_TX_DELAY; 236 } 237 238 err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp); 239 if (err < 0) 240 return err; 241 242 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR); 243 if (temp < 0) 244 return temp; 245 246 temp &= ~(MII_M1111_HWCFG_MODE_MASK); 247 248 if (temp & MII_M1111_HWCFG_FIBER_COPPER_RES) 249 temp |= MII_M1111_HWCFG_MODE_FIBER_RGMII; 250 else 251 temp |= MII_M1111_HWCFG_MODE_COPPER_RGMII; 252 253 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp); 254 if (err < 0) 255 return err; 256 } 257 258 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { 259 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR); 260 if (temp < 0) 261 return temp; 262 263 temp &= ~(MII_M1111_HWCFG_MODE_MASK); 264 temp |= MII_M1111_HWCFG_MODE_SGMII_NO_CLK; 265 temp |= MII_M1111_HWCFG_FIBER_COPPER_AUTO; 266 267 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp); 268 if (err < 0) 269 return err; 270 } 271 272 err = phy_write(phydev, MII_BMCR, BMCR_RESET); 273 if (err < 0) 274 return err; 275 276 return 0; 277 } 278 279 static int m88e1118_config_aneg(struct phy_device *phydev) 280 { 281 int err; 282 283 err = phy_write(phydev, MII_BMCR, BMCR_RESET); 284 if (err < 0) 285 return err; 286 287 err = phy_write(phydev, MII_M1011_PHY_SCR, 288 MII_M1011_PHY_SCR_AUTO_CROSS); 289 if (err < 0) 290 return err; 291 292 err = genphy_config_aneg(phydev); 293 return 0; 294 } 295 296 static int m88e1118_config_init(struct phy_device *phydev) 297 { 298 int err; 299 300 /* Change address */ 301 err = phy_write(phydev, 0x16, 0x0002); 302 if (err < 0) 303 return err; 304 305 /* Enable 1000 Mbit */ 306 err = phy_write(phydev, 0x15, 0x1070); 307 if (err < 0) 308 return err; 309 310 /* Change address */ 311 err = phy_write(phydev, 0x16, 0x0003); 312 if (err < 0) 313 return err; 314 315 /* Adjust LED Control */ 316 err = phy_write(phydev, 0x10, 0x021e); 317 if (err < 0) 318 return err; 319 320 /* Reset address */ 321 err = phy_write(phydev, 0x16, 0x0); 322 if (err < 0) 323 return err; 324 325 err = phy_write(phydev, MII_BMCR, BMCR_RESET); 326 if (err < 0) 327 return err; 328 329 return 0; 330 } 331 332 static int m88e1145_config_init(struct phy_device *phydev) 333 { 334 int err; 335 336 /* Take care of errata E0 & E1 */ 337 err = phy_write(phydev, 0x1d, 0x001b); 338 if (err < 0) 339 return err; 340 341 err = phy_write(phydev, 0x1e, 0x418f); 342 if (err < 0) 343 return err; 344 345 err = phy_write(phydev, 0x1d, 0x0016); 346 if (err < 0) 347 return err; 348 349 err = phy_write(phydev, 0x1e, 0xa2da); 350 if (err < 0) 351 return err; 352 353 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) { 354 int temp = phy_read(phydev, MII_M1145_PHY_EXT_CR); 355 if (temp < 0) 356 return temp; 357 358 temp |= (MII_M1145_RGMII_RX_DELAY | MII_M1145_RGMII_TX_DELAY); 359 360 err = phy_write(phydev, MII_M1145_PHY_EXT_CR, temp); 361 if (err < 0) 362 return err; 363 364 if (phydev->dev_flags & M1145_DEV_FLAGS_RESISTANCE) { 365 err = phy_write(phydev, 0x1d, 0x0012); 366 if (err < 0) 367 return err; 368 369 temp = phy_read(phydev, 0x1e); 370 if (temp < 0) 371 return temp; 372 373 temp &= 0xf03f; 374 temp |= 2 << 9; /* 36 ohm */ 375 temp |= 2 << 6; /* 39 ohm */ 376 377 err = phy_write(phydev, 0x1e, temp); 378 if (err < 0) 379 return err; 380 381 err = phy_write(phydev, 0x1d, 0x3); 382 if (err < 0) 383 return err; 384 385 err = phy_write(phydev, 0x1e, 0x8000); 386 if (err < 0) 387 return err; 388 } 389 } 390 391 return 0; 392 } 393 394 /* marvell_read_status 395 * 396 * Generic status code does not detect Fiber correctly! 397 * Description: 398 * Check the link, then figure out the current state 399 * by comparing what we advertise with what the link partner 400 * advertises. Start by checking the gigabit possibilities, 401 * then move on to 10/100. 402 */ 403 static int marvell_read_status(struct phy_device *phydev) 404 { 405 int adv; 406 int err; 407 int lpa; 408 int status = 0; 409 410 /* Update the link, but return if there 411 * was an error */ 412 err = genphy_update_link(phydev); 413 if (err) 414 return err; 415 416 if (AUTONEG_ENABLE == phydev->autoneg) { 417 status = phy_read(phydev, MII_M1011_PHY_STATUS); 418 if (status < 0) 419 return status; 420 421 lpa = phy_read(phydev, MII_LPA); 422 if (lpa < 0) 423 return lpa; 424 425 adv = phy_read(phydev, MII_ADVERTISE); 426 if (adv < 0) 427 return adv; 428 429 lpa &= adv; 430 431 if (status & MII_M1011_PHY_STATUS_FULLDUPLEX) 432 phydev->duplex = DUPLEX_FULL; 433 else 434 phydev->duplex = DUPLEX_HALF; 435 436 status = status & MII_M1011_PHY_STATUS_SPD_MASK; 437 phydev->pause = phydev->asym_pause = 0; 438 439 switch (status) { 440 case MII_M1011_PHY_STATUS_1000: 441 phydev->speed = SPEED_1000; 442 break; 443 444 case MII_M1011_PHY_STATUS_100: 445 phydev->speed = SPEED_100; 446 break; 447 448 default: 449 phydev->speed = SPEED_10; 450 break; 451 } 452 453 if (phydev->duplex == DUPLEX_FULL) { 454 phydev->pause = lpa & LPA_PAUSE_CAP ? 1 : 0; 455 phydev->asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0; 456 } 457 } else { 458 int bmcr = phy_read(phydev, MII_BMCR); 459 460 if (bmcr < 0) 461 return bmcr; 462 463 if (bmcr & BMCR_FULLDPLX) 464 phydev->duplex = DUPLEX_FULL; 465 else 466 phydev->duplex = DUPLEX_HALF; 467 468 if (bmcr & BMCR_SPEED1000) 469 phydev->speed = SPEED_1000; 470 else if (bmcr & BMCR_SPEED100) 471 phydev->speed = SPEED_100; 472 else 473 phydev->speed = SPEED_10; 474 475 phydev->pause = phydev->asym_pause = 0; 476 } 477 478 return 0; 479 } 480 481 static int m88e1121_did_interrupt(struct phy_device *phydev) 482 { 483 int imask; 484 485 imask = phy_read(phydev, MII_M1011_IEVENT); 486 487 if (imask & MII_M1011_IMASK_INIT) 488 return 1; 489 490 return 0; 491 } 492 493 static struct phy_driver marvell_drivers[] = { 494 { 495 .phy_id = 0x01410c60, 496 .phy_id_mask = 0xfffffff0, 497 .name = "Marvell 88E1101", 498 .features = PHY_GBIT_FEATURES, 499 .flags = PHY_HAS_INTERRUPT, 500 .config_aneg = &marvell_config_aneg, 501 .read_status = &genphy_read_status, 502 .ack_interrupt = &marvell_ack_interrupt, 503 .config_intr = &marvell_config_intr, 504 .driver = { .owner = THIS_MODULE }, 505 }, 506 { 507 .phy_id = 0x01410c90, 508 .phy_id_mask = 0xfffffff0, 509 .name = "Marvell 88E1112", 510 .features = PHY_GBIT_FEATURES, 511 .flags = PHY_HAS_INTERRUPT, 512 .config_init = &m88e1111_config_init, 513 .config_aneg = &marvell_config_aneg, 514 .read_status = &genphy_read_status, 515 .ack_interrupt = &marvell_ack_interrupt, 516 .config_intr = &marvell_config_intr, 517 .driver = { .owner = THIS_MODULE }, 518 }, 519 { 520 .phy_id = 0x01410cc0, 521 .phy_id_mask = 0xfffffff0, 522 .name = "Marvell 88E1111", 523 .features = PHY_GBIT_FEATURES, 524 .flags = PHY_HAS_INTERRUPT, 525 .config_init = &m88e1111_config_init, 526 .config_aneg = &marvell_config_aneg, 527 .read_status = &marvell_read_status, 528 .ack_interrupt = &marvell_ack_interrupt, 529 .config_intr = &marvell_config_intr, 530 .driver = { .owner = THIS_MODULE }, 531 }, 532 { 533 .phy_id = 0x01410e10, 534 .phy_id_mask = 0xfffffff0, 535 .name = "Marvell 88E1118", 536 .features = PHY_GBIT_FEATURES, 537 .flags = PHY_HAS_INTERRUPT, 538 .config_init = &m88e1118_config_init, 539 .config_aneg = &m88e1118_config_aneg, 540 .read_status = &genphy_read_status, 541 .ack_interrupt = &marvell_ack_interrupt, 542 .config_intr = &marvell_config_intr, 543 .driver = {.owner = THIS_MODULE,}, 544 }, 545 { 546 .phy_id = 0x01410cb0, 547 .phy_id_mask = 0xfffffff0, 548 .name = "Marvell 88E1121R", 549 .features = PHY_GBIT_FEATURES, 550 .flags = PHY_HAS_INTERRUPT, 551 .config_aneg = &m88e1121_config_aneg, 552 .read_status = &marvell_read_status, 553 .ack_interrupt = &marvell_ack_interrupt, 554 .config_intr = &marvell_config_intr, 555 .did_interrupt = &m88e1121_did_interrupt, 556 .driver = { .owner = THIS_MODULE }, 557 }, 558 { 559 .phy_id = 0x01410cd0, 560 .phy_id_mask = 0xfffffff0, 561 .name = "Marvell 88E1145", 562 .features = PHY_GBIT_FEATURES, 563 .flags = PHY_HAS_INTERRUPT, 564 .config_init = &m88e1145_config_init, 565 .config_aneg = &marvell_config_aneg, 566 .read_status = &genphy_read_status, 567 .ack_interrupt = &marvell_ack_interrupt, 568 .config_intr = &marvell_config_intr, 569 .driver = { .owner = THIS_MODULE }, 570 }, 571 { 572 .phy_id = 0x01410e30, 573 .phy_id_mask = 0xfffffff0, 574 .name = "Marvell 88E1240", 575 .features = PHY_GBIT_FEATURES, 576 .flags = PHY_HAS_INTERRUPT, 577 .config_init = &m88e1111_config_init, 578 .config_aneg = &marvell_config_aneg, 579 .read_status = &genphy_read_status, 580 .ack_interrupt = &marvell_ack_interrupt, 581 .config_intr = &marvell_config_intr, 582 .driver = { .owner = THIS_MODULE }, 583 }, 584 }; 585 586 static int __init marvell_init(void) 587 { 588 int ret; 589 int i; 590 591 for (i = 0; i < ARRAY_SIZE(marvell_drivers); i++) { 592 ret = phy_driver_register(&marvell_drivers[i]); 593 594 if (ret) { 595 while (i-- > 0) 596 phy_driver_unregister(&marvell_drivers[i]); 597 return ret; 598 } 599 } 600 601 return 0; 602 } 603 604 static void __exit marvell_exit(void) 605 { 606 int i; 607 608 for (i = 0; i < ARRAY_SIZE(marvell_drivers); i++) 609 phy_driver_unregister(&marvell_drivers[i]); 610 } 611 612 module_init(marvell_init); 613 module_exit(marvell_exit); 614