1 /* 2 * drivers/net/phy/marvell.c 3 * 4 * Driver for Marvell PHYs 5 * 6 * Author: Andy Fleming 7 * 8 * Copyright (c) 2004 Freescale Semiconductor, Inc. 9 * 10 * Copyright (c) 2013 Michael Stapelberg <michael@stapelberg.de> 11 * 12 * This program is free software; you can redistribute it and/or modify it 13 * under the terms of the GNU General Public License as published by the 14 * Free Software Foundation; either version 2 of the License, or (at your 15 * option) any later version. 16 * 17 */ 18 #include <linux/kernel.h> 19 #include <linux/string.h> 20 #include <linux/errno.h> 21 #include <linux/unistd.h> 22 #include <linux/interrupt.h> 23 #include <linux/init.h> 24 #include <linux/delay.h> 25 #include <linux/netdevice.h> 26 #include <linux/etherdevice.h> 27 #include <linux/skbuff.h> 28 #include <linux/spinlock.h> 29 #include <linux/mm.h> 30 #include <linux/module.h> 31 #include <linux/mii.h> 32 #include <linux/ethtool.h> 33 #include <linux/phy.h> 34 #include <linux/marvell_phy.h> 35 #include <linux/of.h> 36 37 #include <asm/io.h> 38 #include <asm/irq.h> 39 #include <asm/uaccess.h> 40 41 #define MII_MARVELL_PHY_PAGE 22 42 43 #define MII_M1011_IEVENT 0x13 44 #define MII_M1011_IEVENT_CLEAR 0x0000 45 46 #define MII_M1011_IMASK 0x12 47 #define MII_M1011_IMASK_INIT 0x6400 48 #define MII_M1011_IMASK_CLEAR 0x0000 49 50 #define MII_M1011_PHY_SCR 0x10 51 #define MII_M1011_PHY_SCR_AUTO_CROSS 0x0060 52 53 #define MII_M1145_PHY_EXT_CR 0x14 54 #define MII_M1145_RGMII_RX_DELAY 0x0080 55 #define MII_M1145_RGMII_TX_DELAY 0x0002 56 57 #define MII_M1111_PHY_LED_CONTROL 0x18 58 #define MII_M1111_PHY_LED_DIRECT 0x4100 59 #define MII_M1111_PHY_LED_COMBINE 0x411c 60 #define MII_M1111_PHY_EXT_CR 0x14 61 #define MII_M1111_RX_DELAY 0x80 62 #define MII_M1111_TX_DELAY 0x2 63 #define MII_M1111_PHY_EXT_SR 0x1b 64 65 #define MII_M1111_HWCFG_MODE_MASK 0xf 66 #define MII_M1111_HWCFG_MODE_COPPER_RGMII 0xb 67 #define MII_M1111_HWCFG_MODE_FIBER_RGMII 0x3 68 #define MII_M1111_HWCFG_MODE_SGMII_NO_CLK 0x4 69 #define MII_M1111_HWCFG_MODE_COPPER_RTBI 0x9 70 #define MII_M1111_HWCFG_FIBER_COPPER_AUTO 0x8000 71 #define MII_M1111_HWCFG_FIBER_COPPER_RES 0x2000 72 73 #define MII_M1111_COPPER 0 74 #define MII_M1111_FIBER 1 75 76 #define MII_88E1121_PHY_MSCR_PAGE 2 77 #define MII_88E1121_PHY_MSCR_REG 21 78 #define MII_88E1121_PHY_MSCR_RX_DELAY BIT(5) 79 #define MII_88E1121_PHY_MSCR_TX_DELAY BIT(4) 80 #define MII_88E1121_PHY_MSCR_DELAY_MASK (~(0x3 << 4)) 81 82 #define MII_88E1318S_PHY_MSCR1_REG 16 83 #define MII_88E1318S_PHY_MSCR1_PAD_ODD BIT(6) 84 85 /* Copper Specific Interrupt Enable Register */ 86 #define MII_88E1318S_PHY_CSIER 0x12 87 /* WOL Event Interrupt Enable */ 88 #define MII_88E1318S_PHY_CSIER_WOL_EIE BIT(7) 89 90 /* LED Timer Control Register */ 91 #define MII_88E1318S_PHY_LED_PAGE 0x03 92 #define MII_88E1318S_PHY_LED_TCR 0x12 93 #define MII_88E1318S_PHY_LED_TCR_FORCE_INT BIT(15) 94 #define MII_88E1318S_PHY_LED_TCR_INTn_ENABLE BIT(7) 95 #define MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW BIT(11) 96 97 /* Magic Packet MAC address registers */ 98 #define MII_88E1318S_PHY_MAGIC_PACKET_WORD2 0x17 99 #define MII_88E1318S_PHY_MAGIC_PACKET_WORD1 0x18 100 #define MII_88E1318S_PHY_MAGIC_PACKET_WORD0 0x19 101 102 #define MII_88E1318S_PHY_WOL_PAGE 0x11 103 #define MII_88E1318S_PHY_WOL_CTRL 0x10 104 #define MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS BIT(12) 105 #define MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE BIT(14) 106 107 #define MII_88E1121_PHY_LED_CTRL 16 108 #define MII_88E1121_PHY_LED_PAGE 3 109 #define MII_88E1121_PHY_LED_DEF 0x0030 110 111 #define MII_M1011_PHY_STATUS 0x11 112 #define MII_M1011_PHY_STATUS_1000 0x8000 113 #define MII_M1011_PHY_STATUS_100 0x4000 114 #define MII_M1011_PHY_STATUS_SPD_MASK 0xc000 115 #define MII_M1011_PHY_STATUS_FULLDUPLEX 0x2000 116 #define MII_M1011_PHY_STATUS_RESOLVED 0x0800 117 #define MII_M1011_PHY_STATUS_LINK 0x0400 118 119 120 MODULE_DESCRIPTION("Marvell PHY driver"); 121 MODULE_AUTHOR("Andy Fleming"); 122 MODULE_LICENSE("GPL"); 123 124 static int marvell_ack_interrupt(struct phy_device *phydev) 125 { 126 int err; 127 128 /* Clear the interrupts by reading the reg */ 129 err = phy_read(phydev, MII_M1011_IEVENT); 130 131 if (err < 0) 132 return err; 133 134 return 0; 135 } 136 137 static int marvell_config_intr(struct phy_device *phydev) 138 { 139 int err; 140 141 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) 142 err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_INIT); 143 else 144 err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR); 145 146 return err; 147 } 148 149 static int marvell_config_aneg(struct phy_device *phydev) 150 { 151 int err; 152 153 /* The Marvell PHY has an errata which requires 154 * that certain registers get written in order 155 * to restart autonegotiation */ 156 err = phy_write(phydev, MII_BMCR, BMCR_RESET); 157 158 if (err < 0) 159 return err; 160 161 err = phy_write(phydev, 0x1d, 0x1f); 162 if (err < 0) 163 return err; 164 165 err = phy_write(phydev, 0x1e, 0x200c); 166 if (err < 0) 167 return err; 168 169 err = phy_write(phydev, 0x1d, 0x5); 170 if (err < 0) 171 return err; 172 173 err = phy_write(phydev, 0x1e, 0); 174 if (err < 0) 175 return err; 176 177 err = phy_write(phydev, 0x1e, 0x100); 178 if (err < 0) 179 return err; 180 181 err = phy_write(phydev, MII_M1011_PHY_SCR, 182 MII_M1011_PHY_SCR_AUTO_CROSS); 183 if (err < 0) 184 return err; 185 186 err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL, 187 MII_M1111_PHY_LED_DIRECT); 188 if (err < 0) 189 return err; 190 191 err = genphy_config_aneg(phydev); 192 if (err < 0) 193 return err; 194 195 if (phydev->autoneg != AUTONEG_ENABLE) { 196 int bmcr; 197 198 /* 199 * A write to speed/duplex bits (that is performed by 200 * genphy_config_aneg() call above) must be followed by 201 * a software reset. Otherwise, the write has no effect. 202 */ 203 bmcr = phy_read(phydev, MII_BMCR); 204 if (bmcr < 0) 205 return bmcr; 206 207 err = phy_write(phydev, MII_BMCR, bmcr | BMCR_RESET); 208 if (err < 0) 209 return err; 210 } 211 212 return 0; 213 } 214 215 #ifdef CONFIG_OF_MDIO 216 /* 217 * Set and/or override some configuration registers based on the 218 * marvell,reg-init property stored in the of_node for the phydev. 219 * 220 * marvell,reg-init = <reg-page reg mask value>,...; 221 * 222 * There may be one or more sets of <reg-page reg mask value>: 223 * 224 * reg-page: which register bank to use. 225 * reg: the register. 226 * mask: if non-zero, ANDed with existing register value. 227 * value: ORed with the masked value and written to the regiser. 228 * 229 */ 230 static int marvell_of_reg_init(struct phy_device *phydev) 231 { 232 const __be32 *paddr; 233 int len, i, saved_page, current_page, page_changed, ret; 234 235 if (!phydev->dev.of_node) 236 return 0; 237 238 paddr = of_get_property(phydev->dev.of_node, "marvell,reg-init", &len); 239 if (!paddr || len < (4 * sizeof(*paddr))) 240 return 0; 241 242 saved_page = phy_read(phydev, MII_MARVELL_PHY_PAGE); 243 if (saved_page < 0) 244 return saved_page; 245 page_changed = 0; 246 current_page = saved_page; 247 248 ret = 0; 249 len /= sizeof(*paddr); 250 for (i = 0; i < len - 3; i += 4) { 251 u16 reg_page = be32_to_cpup(paddr + i); 252 u16 reg = be32_to_cpup(paddr + i + 1); 253 u16 mask = be32_to_cpup(paddr + i + 2); 254 u16 val_bits = be32_to_cpup(paddr + i + 3); 255 int val; 256 257 if (reg_page != current_page) { 258 current_page = reg_page; 259 page_changed = 1; 260 ret = phy_write(phydev, MII_MARVELL_PHY_PAGE, reg_page); 261 if (ret < 0) 262 goto err; 263 } 264 265 val = 0; 266 if (mask) { 267 val = phy_read(phydev, reg); 268 if (val < 0) { 269 ret = val; 270 goto err; 271 } 272 val &= mask; 273 } 274 val |= val_bits; 275 276 ret = phy_write(phydev, reg, val); 277 if (ret < 0) 278 goto err; 279 280 } 281 err: 282 if (page_changed) { 283 i = phy_write(phydev, MII_MARVELL_PHY_PAGE, saved_page); 284 if (ret == 0) 285 ret = i; 286 } 287 return ret; 288 } 289 #else 290 static int marvell_of_reg_init(struct phy_device *phydev) 291 { 292 return 0; 293 } 294 #endif /* CONFIG_OF_MDIO */ 295 296 static int m88e1121_config_aneg(struct phy_device *phydev) 297 { 298 int err, oldpage, mscr; 299 300 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE); 301 302 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 303 MII_88E1121_PHY_MSCR_PAGE); 304 if (err < 0) 305 return err; 306 307 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) || 308 (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) || 309 (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) || 310 (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) { 311 312 mscr = phy_read(phydev, MII_88E1121_PHY_MSCR_REG) & 313 MII_88E1121_PHY_MSCR_DELAY_MASK; 314 315 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) 316 mscr |= (MII_88E1121_PHY_MSCR_RX_DELAY | 317 MII_88E1121_PHY_MSCR_TX_DELAY); 318 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) 319 mscr |= MII_88E1121_PHY_MSCR_RX_DELAY; 320 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) 321 mscr |= MII_88E1121_PHY_MSCR_TX_DELAY; 322 323 err = phy_write(phydev, MII_88E1121_PHY_MSCR_REG, mscr); 324 if (err < 0) 325 return err; 326 } 327 328 phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage); 329 330 err = phy_write(phydev, MII_BMCR, BMCR_RESET); 331 if (err < 0) 332 return err; 333 334 err = phy_write(phydev, MII_M1011_PHY_SCR, 335 MII_M1011_PHY_SCR_AUTO_CROSS); 336 if (err < 0) 337 return err; 338 339 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE); 340 341 phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_88E1121_PHY_LED_PAGE); 342 phy_write(phydev, MII_88E1121_PHY_LED_CTRL, MII_88E1121_PHY_LED_DEF); 343 phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage); 344 345 err = genphy_config_aneg(phydev); 346 347 return err; 348 } 349 350 static int m88e1318_config_aneg(struct phy_device *phydev) 351 { 352 int err, oldpage, mscr; 353 354 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE); 355 356 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 357 MII_88E1121_PHY_MSCR_PAGE); 358 if (err < 0) 359 return err; 360 361 mscr = phy_read(phydev, MII_88E1318S_PHY_MSCR1_REG); 362 mscr |= MII_88E1318S_PHY_MSCR1_PAD_ODD; 363 364 err = phy_write(phydev, MII_88E1318S_PHY_MSCR1_REG, mscr); 365 if (err < 0) 366 return err; 367 368 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage); 369 if (err < 0) 370 return err; 371 372 return m88e1121_config_aneg(phydev); 373 } 374 375 static int m88e1111_config_init(struct phy_device *phydev) 376 { 377 int err; 378 int temp; 379 380 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) || 381 (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) || 382 (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) || 383 (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) { 384 385 temp = phy_read(phydev, MII_M1111_PHY_EXT_CR); 386 if (temp < 0) 387 return temp; 388 389 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) { 390 temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY); 391 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) { 392 temp &= ~MII_M1111_TX_DELAY; 393 temp |= MII_M1111_RX_DELAY; 394 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) { 395 temp &= ~MII_M1111_RX_DELAY; 396 temp |= MII_M1111_TX_DELAY; 397 } 398 399 err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp); 400 if (err < 0) 401 return err; 402 403 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR); 404 if (temp < 0) 405 return temp; 406 407 temp &= ~(MII_M1111_HWCFG_MODE_MASK); 408 409 if (temp & MII_M1111_HWCFG_FIBER_COPPER_RES) 410 temp |= MII_M1111_HWCFG_MODE_FIBER_RGMII; 411 else 412 temp |= MII_M1111_HWCFG_MODE_COPPER_RGMII; 413 414 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp); 415 if (err < 0) 416 return err; 417 } 418 419 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { 420 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR); 421 if (temp < 0) 422 return temp; 423 424 temp &= ~(MII_M1111_HWCFG_MODE_MASK); 425 temp |= MII_M1111_HWCFG_MODE_SGMII_NO_CLK; 426 temp |= MII_M1111_HWCFG_FIBER_COPPER_AUTO; 427 428 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp); 429 if (err < 0) 430 return err; 431 } 432 433 if (phydev->interface == PHY_INTERFACE_MODE_RTBI) { 434 temp = phy_read(phydev, MII_M1111_PHY_EXT_CR); 435 if (temp < 0) 436 return temp; 437 temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY); 438 err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp); 439 if (err < 0) 440 return err; 441 442 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR); 443 if (temp < 0) 444 return temp; 445 temp &= ~(MII_M1111_HWCFG_MODE_MASK | MII_M1111_HWCFG_FIBER_COPPER_RES); 446 temp |= 0x7 | MII_M1111_HWCFG_FIBER_COPPER_AUTO; 447 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp); 448 if (err < 0) 449 return err; 450 451 /* soft reset */ 452 err = phy_write(phydev, MII_BMCR, BMCR_RESET); 453 if (err < 0) 454 return err; 455 do 456 temp = phy_read(phydev, MII_BMCR); 457 while (temp & BMCR_RESET); 458 459 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR); 460 if (temp < 0) 461 return temp; 462 temp &= ~(MII_M1111_HWCFG_MODE_MASK | MII_M1111_HWCFG_FIBER_COPPER_RES); 463 temp |= MII_M1111_HWCFG_MODE_COPPER_RTBI | MII_M1111_HWCFG_FIBER_COPPER_AUTO; 464 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp); 465 if (err < 0) 466 return err; 467 } 468 469 err = marvell_of_reg_init(phydev); 470 if (err < 0) 471 return err; 472 473 return phy_write(phydev, MII_BMCR, BMCR_RESET); 474 } 475 476 static int m88e1118_config_aneg(struct phy_device *phydev) 477 { 478 int err; 479 480 err = phy_write(phydev, MII_BMCR, BMCR_RESET); 481 if (err < 0) 482 return err; 483 484 err = phy_write(phydev, MII_M1011_PHY_SCR, 485 MII_M1011_PHY_SCR_AUTO_CROSS); 486 if (err < 0) 487 return err; 488 489 err = genphy_config_aneg(phydev); 490 return 0; 491 } 492 493 static int m88e1118_config_init(struct phy_device *phydev) 494 { 495 int err; 496 497 /* Change address */ 498 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0002); 499 if (err < 0) 500 return err; 501 502 /* Enable 1000 Mbit */ 503 err = phy_write(phydev, 0x15, 0x1070); 504 if (err < 0) 505 return err; 506 507 /* Change address */ 508 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0003); 509 if (err < 0) 510 return err; 511 512 /* Adjust LED Control */ 513 if (phydev->dev_flags & MARVELL_PHY_M1118_DNS323_LEDS) 514 err = phy_write(phydev, 0x10, 0x1100); 515 else 516 err = phy_write(phydev, 0x10, 0x021e); 517 if (err < 0) 518 return err; 519 520 err = marvell_of_reg_init(phydev); 521 if (err < 0) 522 return err; 523 524 /* Reset address */ 525 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0); 526 if (err < 0) 527 return err; 528 529 return phy_write(phydev, MII_BMCR, BMCR_RESET); 530 } 531 532 static int m88e1149_config_init(struct phy_device *phydev) 533 { 534 int err; 535 536 /* Change address */ 537 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0002); 538 if (err < 0) 539 return err; 540 541 /* Enable 1000 Mbit */ 542 err = phy_write(phydev, 0x15, 0x1048); 543 if (err < 0) 544 return err; 545 546 err = marvell_of_reg_init(phydev); 547 if (err < 0) 548 return err; 549 550 /* Reset address */ 551 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0); 552 if (err < 0) 553 return err; 554 555 return phy_write(phydev, MII_BMCR, BMCR_RESET); 556 } 557 558 static int m88e1145_config_init(struct phy_device *phydev) 559 { 560 int err; 561 562 /* Take care of errata E0 & E1 */ 563 err = phy_write(phydev, 0x1d, 0x001b); 564 if (err < 0) 565 return err; 566 567 err = phy_write(phydev, 0x1e, 0x418f); 568 if (err < 0) 569 return err; 570 571 err = phy_write(phydev, 0x1d, 0x0016); 572 if (err < 0) 573 return err; 574 575 err = phy_write(phydev, 0x1e, 0xa2da); 576 if (err < 0) 577 return err; 578 579 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) { 580 int temp = phy_read(phydev, MII_M1145_PHY_EXT_CR); 581 if (temp < 0) 582 return temp; 583 584 temp |= (MII_M1145_RGMII_RX_DELAY | MII_M1145_RGMII_TX_DELAY); 585 586 err = phy_write(phydev, MII_M1145_PHY_EXT_CR, temp); 587 if (err < 0) 588 return err; 589 590 if (phydev->dev_flags & MARVELL_PHY_M1145_FLAGS_RESISTANCE) { 591 err = phy_write(phydev, 0x1d, 0x0012); 592 if (err < 0) 593 return err; 594 595 temp = phy_read(phydev, 0x1e); 596 if (temp < 0) 597 return temp; 598 599 temp &= 0xf03f; 600 temp |= 2 << 9; /* 36 ohm */ 601 temp |= 2 << 6; /* 39 ohm */ 602 603 err = phy_write(phydev, 0x1e, temp); 604 if (err < 0) 605 return err; 606 607 err = phy_write(phydev, 0x1d, 0x3); 608 if (err < 0) 609 return err; 610 611 err = phy_write(phydev, 0x1e, 0x8000); 612 if (err < 0) 613 return err; 614 } 615 } 616 617 err = marvell_of_reg_init(phydev); 618 if (err < 0) 619 return err; 620 621 return 0; 622 } 623 624 /* marvell_read_status 625 * 626 * Generic status code does not detect Fiber correctly! 627 * Description: 628 * Check the link, then figure out the current state 629 * by comparing what we advertise with what the link partner 630 * advertises. Start by checking the gigabit possibilities, 631 * then move on to 10/100. 632 */ 633 static int marvell_read_status(struct phy_device *phydev) 634 { 635 int adv; 636 int err; 637 int lpa; 638 int status = 0; 639 640 /* Update the link, but return if there 641 * was an error */ 642 err = genphy_update_link(phydev); 643 if (err) 644 return err; 645 646 if (AUTONEG_ENABLE == phydev->autoneg) { 647 status = phy_read(phydev, MII_M1011_PHY_STATUS); 648 if (status < 0) 649 return status; 650 651 lpa = phy_read(phydev, MII_LPA); 652 if (lpa < 0) 653 return lpa; 654 655 adv = phy_read(phydev, MII_ADVERTISE); 656 if (adv < 0) 657 return adv; 658 659 lpa &= adv; 660 661 if (status & MII_M1011_PHY_STATUS_FULLDUPLEX) 662 phydev->duplex = DUPLEX_FULL; 663 else 664 phydev->duplex = DUPLEX_HALF; 665 666 status = status & MII_M1011_PHY_STATUS_SPD_MASK; 667 phydev->pause = phydev->asym_pause = 0; 668 669 switch (status) { 670 case MII_M1011_PHY_STATUS_1000: 671 phydev->speed = SPEED_1000; 672 break; 673 674 case MII_M1011_PHY_STATUS_100: 675 phydev->speed = SPEED_100; 676 break; 677 678 default: 679 phydev->speed = SPEED_10; 680 break; 681 } 682 683 if (phydev->duplex == DUPLEX_FULL) { 684 phydev->pause = lpa & LPA_PAUSE_CAP ? 1 : 0; 685 phydev->asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0; 686 } 687 } else { 688 int bmcr = phy_read(phydev, MII_BMCR); 689 690 if (bmcr < 0) 691 return bmcr; 692 693 if (bmcr & BMCR_FULLDPLX) 694 phydev->duplex = DUPLEX_FULL; 695 else 696 phydev->duplex = DUPLEX_HALF; 697 698 if (bmcr & BMCR_SPEED1000) 699 phydev->speed = SPEED_1000; 700 else if (bmcr & BMCR_SPEED100) 701 phydev->speed = SPEED_100; 702 else 703 phydev->speed = SPEED_10; 704 705 phydev->pause = phydev->asym_pause = 0; 706 } 707 708 return 0; 709 } 710 711 static int m88e1121_did_interrupt(struct phy_device *phydev) 712 { 713 int imask; 714 715 imask = phy_read(phydev, MII_M1011_IEVENT); 716 717 if (imask & MII_M1011_IMASK_INIT) 718 return 1; 719 720 return 0; 721 } 722 723 static void m88e1318_get_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol) 724 { 725 wol->supported = WAKE_MAGIC; 726 wol->wolopts = 0; 727 728 if (phy_write(phydev, MII_MARVELL_PHY_PAGE, 729 MII_88E1318S_PHY_WOL_PAGE) < 0) 730 return; 731 732 if (phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL) & 733 MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE) 734 wol->wolopts |= WAKE_MAGIC; 735 736 if (phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x00) < 0) 737 return; 738 } 739 740 static int m88e1318_set_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol) 741 { 742 int err, oldpage, temp; 743 744 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE); 745 746 if (wol->wolopts & WAKE_MAGIC) { 747 /* Explicitly switch to page 0x00, just to be sure */ 748 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x00); 749 if (err < 0) 750 return err; 751 752 /* Enable the WOL interrupt */ 753 temp = phy_read(phydev, MII_88E1318S_PHY_CSIER); 754 temp |= MII_88E1318S_PHY_CSIER_WOL_EIE; 755 err = phy_write(phydev, MII_88E1318S_PHY_CSIER, temp); 756 if (err < 0) 757 return err; 758 759 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 760 MII_88E1318S_PHY_LED_PAGE); 761 if (err < 0) 762 return err; 763 764 /* Setup LED[2] as interrupt pin (active low) */ 765 temp = phy_read(phydev, MII_88E1318S_PHY_LED_TCR); 766 temp &= ~MII_88E1318S_PHY_LED_TCR_FORCE_INT; 767 temp |= MII_88E1318S_PHY_LED_TCR_INTn_ENABLE; 768 temp |= MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW; 769 err = phy_write(phydev, MII_88E1318S_PHY_LED_TCR, temp); 770 if (err < 0) 771 return err; 772 773 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 774 MII_88E1318S_PHY_WOL_PAGE); 775 if (err < 0) 776 return err; 777 778 /* Store the device address for the magic packet */ 779 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD2, 780 ((phydev->attached_dev->dev_addr[5] << 8) | 781 phydev->attached_dev->dev_addr[4])); 782 if (err < 0) 783 return err; 784 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD1, 785 ((phydev->attached_dev->dev_addr[3] << 8) | 786 phydev->attached_dev->dev_addr[2])); 787 if (err < 0) 788 return err; 789 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD0, 790 ((phydev->attached_dev->dev_addr[1] << 8) | 791 phydev->attached_dev->dev_addr[0])); 792 if (err < 0) 793 return err; 794 795 /* Clear WOL status and enable magic packet matching */ 796 temp = phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL); 797 temp |= MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS; 798 temp |= MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE; 799 err = phy_write(phydev, MII_88E1318S_PHY_WOL_CTRL, temp); 800 if (err < 0) 801 return err; 802 } else { 803 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 804 MII_88E1318S_PHY_WOL_PAGE); 805 if (err < 0) 806 return err; 807 808 /* Clear WOL status and disable magic packet matching */ 809 temp = phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL); 810 temp |= MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS; 811 temp &= ~MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE; 812 err = phy_write(phydev, MII_88E1318S_PHY_WOL_CTRL, temp); 813 if (err < 0) 814 return err; 815 } 816 817 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage); 818 if (err < 0) 819 return err; 820 821 return 0; 822 } 823 824 static struct phy_driver marvell_drivers[] = { 825 { 826 .phy_id = MARVELL_PHY_ID_88E1101, 827 .phy_id_mask = MARVELL_PHY_ID_MASK, 828 .name = "Marvell 88E1101", 829 .features = PHY_GBIT_FEATURES, 830 .flags = PHY_HAS_INTERRUPT, 831 .config_aneg = &marvell_config_aneg, 832 .read_status = &genphy_read_status, 833 .ack_interrupt = &marvell_ack_interrupt, 834 .config_intr = &marvell_config_intr, 835 .driver = { .owner = THIS_MODULE }, 836 }, 837 { 838 .phy_id = MARVELL_PHY_ID_88E1112, 839 .phy_id_mask = MARVELL_PHY_ID_MASK, 840 .name = "Marvell 88E1112", 841 .features = PHY_GBIT_FEATURES, 842 .flags = PHY_HAS_INTERRUPT, 843 .config_init = &m88e1111_config_init, 844 .config_aneg = &marvell_config_aneg, 845 .read_status = &genphy_read_status, 846 .ack_interrupt = &marvell_ack_interrupt, 847 .config_intr = &marvell_config_intr, 848 .driver = { .owner = THIS_MODULE }, 849 }, 850 { 851 .phy_id = MARVELL_PHY_ID_88E1111, 852 .phy_id_mask = MARVELL_PHY_ID_MASK, 853 .name = "Marvell 88E1111", 854 .features = PHY_GBIT_FEATURES, 855 .flags = PHY_HAS_INTERRUPT, 856 .config_init = &m88e1111_config_init, 857 .config_aneg = &marvell_config_aneg, 858 .read_status = &marvell_read_status, 859 .ack_interrupt = &marvell_ack_interrupt, 860 .config_intr = &marvell_config_intr, 861 .driver = { .owner = THIS_MODULE }, 862 }, 863 { 864 .phy_id = MARVELL_PHY_ID_88E1118, 865 .phy_id_mask = MARVELL_PHY_ID_MASK, 866 .name = "Marvell 88E1118", 867 .features = PHY_GBIT_FEATURES, 868 .flags = PHY_HAS_INTERRUPT, 869 .config_init = &m88e1118_config_init, 870 .config_aneg = &m88e1118_config_aneg, 871 .read_status = &genphy_read_status, 872 .ack_interrupt = &marvell_ack_interrupt, 873 .config_intr = &marvell_config_intr, 874 .driver = {.owner = THIS_MODULE,}, 875 }, 876 { 877 .phy_id = MARVELL_PHY_ID_88E1121R, 878 .phy_id_mask = MARVELL_PHY_ID_MASK, 879 .name = "Marvell 88E1121R", 880 .features = PHY_GBIT_FEATURES, 881 .flags = PHY_HAS_INTERRUPT, 882 .config_aneg = &m88e1121_config_aneg, 883 .read_status = &marvell_read_status, 884 .ack_interrupt = &marvell_ack_interrupt, 885 .config_intr = &marvell_config_intr, 886 .did_interrupt = &m88e1121_did_interrupt, 887 .driver = { .owner = THIS_MODULE }, 888 }, 889 { 890 .phy_id = MARVELL_PHY_ID_88E1318S, 891 .phy_id_mask = MARVELL_PHY_ID_MASK, 892 .name = "Marvell 88E1318S", 893 .features = PHY_GBIT_FEATURES, 894 .flags = PHY_HAS_INTERRUPT, 895 .config_aneg = &m88e1318_config_aneg, 896 .read_status = &marvell_read_status, 897 .ack_interrupt = &marvell_ack_interrupt, 898 .config_intr = &marvell_config_intr, 899 .did_interrupt = &m88e1121_did_interrupt, 900 .get_wol = &m88e1318_get_wol, 901 .set_wol = &m88e1318_set_wol, 902 .driver = { .owner = THIS_MODULE }, 903 }, 904 { 905 .phy_id = MARVELL_PHY_ID_88E1145, 906 .phy_id_mask = MARVELL_PHY_ID_MASK, 907 .name = "Marvell 88E1145", 908 .features = PHY_GBIT_FEATURES, 909 .flags = PHY_HAS_INTERRUPT, 910 .config_init = &m88e1145_config_init, 911 .config_aneg = &marvell_config_aneg, 912 .read_status = &genphy_read_status, 913 .ack_interrupt = &marvell_ack_interrupt, 914 .config_intr = &marvell_config_intr, 915 .driver = { .owner = THIS_MODULE }, 916 }, 917 { 918 .phy_id = MARVELL_PHY_ID_88E1149R, 919 .phy_id_mask = MARVELL_PHY_ID_MASK, 920 .name = "Marvell 88E1149R", 921 .features = PHY_GBIT_FEATURES, 922 .flags = PHY_HAS_INTERRUPT, 923 .config_init = &m88e1149_config_init, 924 .config_aneg = &m88e1118_config_aneg, 925 .read_status = &genphy_read_status, 926 .ack_interrupt = &marvell_ack_interrupt, 927 .config_intr = &marvell_config_intr, 928 .driver = { .owner = THIS_MODULE }, 929 }, 930 { 931 .phy_id = MARVELL_PHY_ID_88E1240, 932 .phy_id_mask = MARVELL_PHY_ID_MASK, 933 .name = "Marvell 88E1240", 934 .features = PHY_GBIT_FEATURES, 935 .flags = PHY_HAS_INTERRUPT, 936 .config_init = &m88e1111_config_init, 937 .config_aneg = &marvell_config_aneg, 938 .read_status = &genphy_read_status, 939 .ack_interrupt = &marvell_ack_interrupt, 940 .config_intr = &marvell_config_intr, 941 .driver = { .owner = THIS_MODULE }, 942 }, 943 }; 944 945 static int __init marvell_init(void) 946 { 947 return phy_drivers_register(marvell_drivers, 948 ARRAY_SIZE(marvell_drivers)); 949 } 950 951 static void __exit marvell_exit(void) 952 { 953 phy_drivers_unregister(marvell_drivers, 954 ARRAY_SIZE(marvell_drivers)); 955 } 956 957 module_init(marvell_init); 958 module_exit(marvell_exit); 959 960 static struct mdio_device_id __maybe_unused marvell_tbl[] = { 961 { 0x01410c60, 0xfffffff0 }, 962 { 0x01410c90, 0xfffffff0 }, 963 { 0x01410cc0, 0xfffffff0 }, 964 { 0x01410e10, 0xfffffff0 }, 965 { 0x01410cb0, 0xfffffff0 }, 966 { 0x01410cd0, 0xfffffff0 }, 967 { 0x01410e50, 0xfffffff0 }, 968 { 0x01410e30, 0xfffffff0 }, 969 { 0x01410e90, 0xfffffff0 }, 970 { } 971 }; 972 973 MODULE_DEVICE_TABLE(mdio, marvell_tbl); 974