1 /* 2 * drivers/net/phy/marvell.c 3 * 4 * Driver for Marvell PHYs 5 * 6 * Author: Andy Fleming 7 * 8 * Copyright (c) 2004 Freescale Semiconductor, Inc. 9 * 10 * Copyright (c) 2013 Michael Stapelberg <michael@stapelberg.de> 11 * 12 * This program is free software; you can redistribute it and/or modify it 13 * under the terms of the GNU General Public License as published by the 14 * Free Software Foundation; either version 2 of the License, or (at your 15 * option) any later version. 16 * 17 */ 18 #include <linux/kernel.h> 19 #include <linux/string.h> 20 #include <linux/errno.h> 21 #include <linux/unistd.h> 22 #include <linux/interrupt.h> 23 #include <linux/init.h> 24 #include <linux/delay.h> 25 #include <linux/netdevice.h> 26 #include <linux/etherdevice.h> 27 #include <linux/skbuff.h> 28 #include <linux/spinlock.h> 29 #include <linux/mm.h> 30 #include <linux/module.h> 31 #include <linux/mii.h> 32 #include <linux/ethtool.h> 33 #include <linux/phy.h> 34 #include <linux/marvell_phy.h> 35 #include <linux/of.h> 36 37 #include <linux/io.h> 38 #include <asm/irq.h> 39 #include <linux/uaccess.h> 40 41 #define MII_MARVELL_PHY_PAGE 22 42 43 #define MII_M1011_IEVENT 0x13 44 #define MII_M1011_IEVENT_CLEAR 0x0000 45 46 #define MII_M1011_IMASK 0x12 47 #define MII_M1011_IMASK_INIT 0x6400 48 #define MII_M1011_IMASK_CLEAR 0x0000 49 50 #define MII_M1011_PHY_SCR 0x10 51 #define MII_M1011_PHY_SCR_MDI 0x0000 52 #define MII_M1011_PHY_SCR_MDI_X 0x0020 53 #define MII_M1011_PHY_SCR_AUTO_CROSS 0x0060 54 55 #define MII_M1145_PHY_EXT_ADDR_PAGE 0x16 56 #define MII_M1145_PHY_EXT_SR 0x1b 57 #define MII_M1145_PHY_EXT_CR 0x14 58 #define MII_M1145_RGMII_RX_DELAY 0x0080 59 #define MII_M1145_RGMII_TX_DELAY 0x0002 60 #define MII_M1145_HWCFG_MODE_SGMII_NO_CLK 0x4 61 #define MII_M1145_HWCFG_MODE_MASK 0xf 62 #define MII_M1145_HWCFG_FIBER_COPPER_AUTO 0x8000 63 64 #define MII_M1145_HWCFG_MODE_SGMII_NO_CLK 0x4 65 #define MII_M1145_HWCFG_MODE_MASK 0xf 66 #define MII_M1145_HWCFG_FIBER_COPPER_AUTO 0x8000 67 68 #define MII_M1111_PHY_LED_CONTROL 0x18 69 #define MII_M1111_PHY_LED_DIRECT 0x4100 70 #define MII_M1111_PHY_LED_COMBINE 0x411c 71 #define MII_M1111_PHY_EXT_CR 0x14 72 #define MII_M1111_RX_DELAY 0x80 73 #define MII_M1111_TX_DELAY 0x2 74 #define MII_M1111_PHY_EXT_SR 0x1b 75 76 #define MII_M1111_HWCFG_MODE_MASK 0xf 77 #define MII_M1111_HWCFG_MODE_COPPER_RGMII 0xb 78 #define MII_M1111_HWCFG_MODE_FIBER_RGMII 0x3 79 #define MII_M1111_HWCFG_MODE_SGMII_NO_CLK 0x4 80 #define MII_M1111_HWCFG_MODE_COPPER_RTBI 0x9 81 #define MII_M1111_HWCFG_FIBER_COPPER_AUTO 0x8000 82 #define MII_M1111_HWCFG_FIBER_COPPER_RES 0x2000 83 84 #define MII_M1111_COPPER 0 85 #define MII_M1111_FIBER 1 86 87 #define MII_88E1121_PHY_MSCR_PAGE 2 88 #define MII_88E1121_PHY_MSCR_REG 21 89 #define MII_88E1121_PHY_MSCR_RX_DELAY BIT(5) 90 #define MII_88E1121_PHY_MSCR_TX_DELAY BIT(4) 91 #define MII_88E1121_PHY_MSCR_DELAY_MASK (~(0x3 << 4)) 92 93 #define MII_88E1318S_PHY_MSCR1_REG 16 94 #define MII_88E1318S_PHY_MSCR1_PAD_ODD BIT(6) 95 96 /* Copper Specific Interrupt Enable Register */ 97 #define MII_88E1318S_PHY_CSIER 0x12 98 /* WOL Event Interrupt Enable */ 99 #define MII_88E1318S_PHY_CSIER_WOL_EIE BIT(7) 100 101 /* LED Timer Control Register */ 102 #define MII_88E1318S_PHY_LED_PAGE 0x03 103 #define MII_88E1318S_PHY_LED_TCR 0x12 104 #define MII_88E1318S_PHY_LED_TCR_FORCE_INT BIT(15) 105 #define MII_88E1318S_PHY_LED_TCR_INTn_ENABLE BIT(7) 106 #define MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW BIT(11) 107 108 /* Magic Packet MAC address registers */ 109 #define MII_88E1318S_PHY_MAGIC_PACKET_WORD2 0x17 110 #define MII_88E1318S_PHY_MAGIC_PACKET_WORD1 0x18 111 #define MII_88E1318S_PHY_MAGIC_PACKET_WORD0 0x19 112 113 #define MII_88E1318S_PHY_WOL_PAGE 0x11 114 #define MII_88E1318S_PHY_WOL_CTRL 0x10 115 #define MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS BIT(12) 116 #define MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE BIT(14) 117 118 #define MII_88E1121_PHY_LED_CTRL 16 119 #define MII_88E1121_PHY_LED_PAGE 3 120 #define MII_88E1121_PHY_LED_DEF 0x0030 121 122 #define MII_M1011_PHY_STATUS 0x11 123 #define MII_M1011_PHY_STATUS_1000 0x8000 124 #define MII_M1011_PHY_STATUS_100 0x4000 125 #define MII_M1011_PHY_STATUS_SPD_MASK 0xc000 126 #define MII_M1011_PHY_STATUS_FULLDUPLEX 0x2000 127 #define MII_M1011_PHY_STATUS_RESOLVED 0x0800 128 #define MII_M1011_PHY_STATUS_LINK 0x0400 129 130 #define MII_M1116R_CONTROL_REG_MAC 21 131 132 #define MII_88E3016_PHY_SPEC_CTRL 0x10 133 #define MII_88E3016_DISABLE_SCRAMBLER 0x0200 134 #define MII_88E3016_AUTO_MDIX_CROSSOVER 0x0030 135 136 #define MII_88E1510_GEN_CTRL_REG_1 0x14 137 #define MII_88E1510_GEN_CTRL_REG_1_MODE_MASK 0x7 138 #define MII_88E1510_GEN_CTRL_REG_1_MODE_SGMII 0x1 /* SGMII to copper */ 139 #define MII_88E1510_GEN_CTRL_REG_1_RESET 0x8000 /* Soft reset */ 140 141 MODULE_DESCRIPTION("Marvell PHY driver"); 142 MODULE_AUTHOR("Andy Fleming"); 143 MODULE_LICENSE("GPL"); 144 145 struct marvell_hw_stat { 146 const char *string; 147 u8 page; 148 u8 reg; 149 u8 bits; 150 }; 151 152 static struct marvell_hw_stat marvell_hw_stats[] = { 153 { "phy_receive_errors", 0, 21, 16}, 154 { "phy_idle_errors", 0, 10, 8 }, 155 }; 156 157 struct marvell_priv { 158 u64 stats[ARRAY_SIZE(marvell_hw_stats)]; 159 }; 160 161 static int marvell_ack_interrupt(struct phy_device *phydev) 162 { 163 int err; 164 165 /* Clear the interrupts by reading the reg */ 166 err = phy_read(phydev, MII_M1011_IEVENT); 167 168 if (err < 0) 169 return err; 170 171 return 0; 172 } 173 174 static int marvell_config_intr(struct phy_device *phydev) 175 { 176 int err; 177 178 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) 179 err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_INIT); 180 else 181 err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR); 182 183 return err; 184 } 185 186 static int marvell_set_polarity(struct phy_device *phydev, int polarity) 187 { 188 int reg; 189 int err; 190 int val; 191 192 /* get the current settings */ 193 reg = phy_read(phydev, MII_M1011_PHY_SCR); 194 if (reg < 0) 195 return reg; 196 197 val = reg; 198 val &= ~MII_M1011_PHY_SCR_AUTO_CROSS; 199 switch (polarity) { 200 case ETH_TP_MDI: 201 val |= MII_M1011_PHY_SCR_MDI; 202 break; 203 case ETH_TP_MDI_X: 204 val |= MII_M1011_PHY_SCR_MDI_X; 205 break; 206 case ETH_TP_MDI_AUTO: 207 case ETH_TP_MDI_INVALID: 208 default: 209 val |= MII_M1011_PHY_SCR_AUTO_CROSS; 210 break; 211 } 212 213 if (val != reg) { 214 /* Set the new polarity value in the register */ 215 err = phy_write(phydev, MII_M1011_PHY_SCR, val); 216 if (err) 217 return err; 218 } 219 220 return 0; 221 } 222 223 static int marvell_config_aneg(struct phy_device *phydev) 224 { 225 int err; 226 227 /* The Marvell PHY has an errata which requires 228 * that certain registers get written in order 229 * to restart autonegotiation */ 230 err = phy_write(phydev, MII_BMCR, BMCR_RESET); 231 232 if (err < 0) 233 return err; 234 235 err = phy_write(phydev, 0x1d, 0x1f); 236 if (err < 0) 237 return err; 238 239 err = phy_write(phydev, 0x1e, 0x200c); 240 if (err < 0) 241 return err; 242 243 err = phy_write(phydev, 0x1d, 0x5); 244 if (err < 0) 245 return err; 246 247 err = phy_write(phydev, 0x1e, 0); 248 if (err < 0) 249 return err; 250 251 err = phy_write(phydev, 0x1e, 0x100); 252 if (err < 0) 253 return err; 254 255 err = marvell_set_polarity(phydev, phydev->mdix); 256 if (err < 0) 257 return err; 258 259 err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL, 260 MII_M1111_PHY_LED_DIRECT); 261 if (err < 0) 262 return err; 263 264 err = genphy_config_aneg(phydev); 265 if (err < 0) 266 return err; 267 268 if (phydev->autoneg != AUTONEG_ENABLE) { 269 int bmcr; 270 271 /* 272 * A write to speed/duplex bits (that is performed by 273 * genphy_config_aneg() call above) must be followed by 274 * a software reset. Otherwise, the write has no effect. 275 */ 276 bmcr = phy_read(phydev, MII_BMCR); 277 if (bmcr < 0) 278 return bmcr; 279 280 err = phy_write(phydev, MII_BMCR, bmcr | BMCR_RESET); 281 if (err < 0) 282 return err; 283 } 284 285 return 0; 286 } 287 288 static int m88e1111_config_aneg(struct phy_device *phydev) 289 { 290 int err; 291 292 /* The Marvell PHY has an errata which requires 293 * that certain registers get written in order 294 * to restart autonegotiation 295 */ 296 err = phy_write(phydev, MII_BMCR, BMCR_RESET); 297 298 err = marvell_set_polarity(phydev, phydev->mdix); 299 if (err < 0) 300 return err; 301 302 err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL, 303 MII_M1111_PHY_LED_DIRECT); 304 if (err < 0) 305 return err; 306 307 err = genphy_config_aneg(phydev); 308 if (err < 0) 309 return err; 310 311 if (phydev->autoneg != AUTONEG_ENABLE) { 312 int bmcr; 313 314 /* A write to speed/duplex bits (that is performed by 315 * genphy_config_aneg() call above) must be followed by 316 * a software reset. Otherwise, the write has no effect. 317 */ 318 bmcr = phy_read(phydev, MII_BMCR); 319 if (bmcr < 0) 320 return bmcr; 321 322 err = phy_write(phydev, MII_BMCR, bmcr | BMCR_RESET); 323 if (err < 0) 324 return err; 325 } 326 327 return 0; 328 } 329 330 #ifdef CONFIG_OF_MDIO 331 /* 332 * Set and/or override some configuration registers based on the 333 * marvell,reg-init property stored in the of_node for the phydev. 334 * 335 * marvell,reg-init = <reg-page reg mask value>,...; 336 * 337 * There may be one or more sets of <reg-page reg mask value>: 338 * 339 * reg-page: which register bank to use. 340 * reg: the register. 341 * mask: if non-zero, ANDed with existing register value. 342 * value: ORed with the masked value and written to the regiser. 343 * 344 */ 345 static int marvell_of_reg_init(struct phy_device *phydev) 346 { 347 const __be32 *paddr; 348 int len, i, saved_page, current_page, page_changed, ret; 349 350 if (!phydev->mdio.dev.of_node) 351 return 0; 352 353 paddr = of_get_property(phydev->mdio.dev.of_node, 354 "marvell,reg-init", &len); 355 if (!paddr || len < (4 * sizeof(*paddr))) 356 return 0; 357 358 saved_page = phy_read(phydev, MII_MARVELL_PHY_PAGE); 359 if (saved_page < 0) 360 return saved_page; 361 page_changed = 0; 362 current_page = saved_page; 363 364 ret = 0; 365 len /= sizeof(*paddr); 366 for (i = 0; i < len - 3; i += 4) { 367 u16 reg_page = be32_to_cpup(paddr + i); 368 u16 reg = be32_to_cpup(paddr + i + 1); 369 u16 mask = be32_to_cpup(paddr + i + 2); 370 u16 val_bits = be32_to_cpup(paddr + i + 3); 371 int val; 372 373 if (reg_page != current_page) { 374 current_page = reg_page; 375 page_changed = 1; 376 ret = phy_write(phydev, MII_MARVELL_PHY_PAGE, reg_page); 377 if (ret < 0) 378 goto err; 379 } 380 381 val = 0; 382 if (mask) { 383 val = phy_read(phydev, reg); 384 if (val < 0) { 385 ret = val; 386 goto err; 387 } 388 val &= mask; 389 } 390 val |= val_bits; 391 392 ret = phy_write(phydev, reg, val); 393 if (ret < 0) 394 goto err; 395 396 } 397 err: 398 if (page_changed) { 399 i = phy_write(phydev, MII_MARVELL_PHY_PAGE, saved_page); 400 if (ret == 0) 401 ret = i; 402 } 403 return ret; 404 } 405 #else 406 static int marvell_of_reg_init(struct phy_device *phydev) 407 { 408 return 0; 409 } 410 #endif /* CONFIG_OF_MDIO */ 411 412 static int m88e1121_config_aneg(struct phy_device *phydev) 413 { 414 int err, oldpage, mscr; 415 416 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE); 417 418 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 419 MII_88E1121_PHY_MSCR_PAGE); 420 if (err < 0) 421 return err; 422 423 if (phy_interface_is_rgmii(phydev)) { 424 425 mscr = phy_read(phydev, MII_88E1121_PHY_MSCR_REG) & 426 MII_88E1121_PHY_MSCR_DELAY_MASK; 427 428 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) 429 mscr |= (MII_88E1121_PHY_MSCR_RX_DELAY | 430 MII_88E1121_PHY_MSCR_TX_DELAY); 431 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) 432 mscr |= MII_88E1121_PHY_MSCR_RX_DELAY; 433 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) 434 mscr |= MII_88E1121_PHY_MSCR_TX_DELAY; 435 436 err = phy_write(phydev, MII_88E1121_PHY_MSCR_REG, mscr); 437 if (err < 0) 438 return err; 439 } 440 441 phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage); 442 443 err = phy_write(phydev, MII_BMCR, BMCR_RESET); 444 if (err < 0) 445 return err; 446 447 err = phy_write(phydev, MII_M1011_PHY_SCR, 448 MII_M1011_PHY_SCR_AUTO_CROSS); 449 if (err < 0) 450 return err; 451 452 return genphy_config_aneg(phydev); 453 } 454 455 static int m88e1318_config_aneg(struct phy_device *phydev) 456 { 457 int err, oldpage, mscr; 458 459 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE); 460 461 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 462 MII_88E1121_PHY_MSCR_PAGE); 463 if (err < 0) 464 return err; 465 466 mscr = phy_read(phydev, MII_88E1318S_PHY_MSCR1_REG); 467 mscr |= MII_88E1318S_PHY_MSCR1_PAD_ODD; 468 469 err = phy_write(phydev, MII_88E1318S_PHY_MSCR1_REG, mscr); 470 if (err < 0) 471 return err; 472 473 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage); 474 if (err < 0) 475 return err; 476 477 return m88e1121_config_aneg(phydev); 478 } 479 480 static int m88e1510_config_aneg(struct phy_device *phydev) 481 { 482 int err; 483 484 err = m88e1318_config_aneg(phydev); 485 if (err < 0) 486 return err; 487 488 return 0; 489 } 490 491 static int marvell_config_init(struct phy_device *phydev) 492 { 493 /* Set registers from marvell,reg-init DT property */ 494 return marvell_of_reg_init(phydev); 495 } 496 497 static int m88e1116r_config_init(struct phy_device *phydev) 498 { 499 int temp; 500 int err; 501 502 temp = phy_read(phydev, MII_BMCR); 503 temp |= BMCR_RESET; 504 err = phy_write(phydev, MII_BMCR, temp); 505 if (err < 0) 506 return err; 507 508 mdelay(500); 509 510 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0); 511 if (err < 0) 512 return err; 513 514 temp = phy_read(phydev, MII_M1011_PHY_SCR); 515 temp |= (7 << 12); /* max number of gigabit attempts */ 516 temp |= (1 << 11); /* enable downshift */ 517 temp |= MII_M1011_PHY_SCR_AUTO_CROSS; 518 err = phy_write(phydev, MII_M1011_PHY_SCR, temp); 519 if (err < 0) 520 return err; 521 522 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 2); 523 if (err < 0) 524 return err; 525 temp = phy_read(phydev, MII_M1116R_CONTROL_REG_MAC); 526 temp |= (1 << 5); 527 temp |= (1 << 4); 528 err = phy_write(phydev, MII_M1116R_CONTROL_REG_MAC, temp); 529 if (err < 0) 530 return err; 531 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0); 532 if (err < 0) 533 return err; 534 535 temp = phy_read(phydev, MII_BMCR); 536 temp |= BMCR_RESET; 537 err = phy_write(phydev, MII_BMCR, temp); 538 if (err < 0) 539 return err; 540 541 mdelay(500); 542 543 return marvell_config_init(phydev); 544 } 545 546 static int m88e3016_config_init(struct phy_device *phydev) 547 { 548 int reg; 549 550 /* Enable Scrambler and Auto-Crossover */ 551 reg = phy_read(phydev, MII_88E3016_PHY_SPEC_CTRL); 552 if (reg < 0) 553 return reg; 554 555 reg &= ~MII_88E3016_DISABLE_SCRAMBLER; 556 reg |= MII_88E3016_AUTO_MDIX_CROSSOVER; 557 558 reg = phy_write(phydev, MII_88E3016_PHY_SPEC_CTRL, reg); 559 if (reg < 0) 560 return reg; 561 562 return marvell_config_init(phydev); 563 } 564 565 static int m88e1111_config_init(struct phy_device *phydev) 566 { 567 int err; 568 int temp; 569 570 if (phy_interface_is_rgmii(phydev)) { 571 572 temp = phy_read(phydev, MII_M1111_PHY_EXT_CR); 573 if (temp < 0) 574 return temp; 575 576 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) { 577 temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY); 578 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) { 579 temp &= ~MII_M1111_TX_DELAY; 580 temp |= MII_M1111_RX_DELAY; 581 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) { 582 temp &= ~MII_M1111_RX_DELAY; 583 temp |= MII_M1111_TX_DELAY; 584 } 585 586 err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp); 587 if (err < 0) 588 return err; 589 590 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR); 591 if (temp < 0) 592 return temp; 593 594 temp &= ~(MII_M1111_HWCFG_MODE_MASK); 595 596 if (temp & MII_M1111_HWCFG_FIBER_COPPER_RES) 597 temp |= MII_M1111_HWCFG_MODE_FIBER_RGMII; 598 else 599 temp |= MII_M1111_HWCFG_MODE_COPPER_RGMII; 600 601 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp); 602 if (err < 0) 603 return err; 604 } 605 606 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { 607 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR); 608 if (temp < 0) 609 return temp; 610 611 temp &= ~(MII_M1111_HWCFG_MODE_MASK); 612 temp |= MII_M1111_HWCFG_MODE_SGMII_NO_CLK; 613 temp |= MII_M1111_HWCFG_FIBER_COPPER_AUTO; 614 615 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp); 616 if (err < 0) 617 return err; 618 619 /* make sure copper is selected */ 620 err = phy_read(phydev, MII_M1145_PHY_EXT_ADDR_PAGE); 621 if (err < 0) 622 return err; 623 624 err = phy_write(phydev, MII_M1145_PHY_EXT_ADDR_PAGE, 625 err & (~0xff)); 626 if (err < 0) 627 return err; 628 } 629 630 if (phydev->interface == PHY_INTERFACE_MODE_RTBI) { 631 temp = phy_read(phydev, MII_M1111_PHY_EXT_CR); 632 if (temp < 0) 633 return temp; 634 temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY); 635 err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp); 636 if (err < 0) 637 return err; 638 639 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR); 640 if (temp < 0) 641 return temp; 642 temp &= ~(MII_M1111_HWCFG_MODE_MASK | MII_M1111_HWCFG_FIBER_COPPER_RES); 643 temp |= 0x7 | MII_M1111_HWCFG_FIBER_COPPER_AUTO; 644 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp); 645 if (err < 0) 646 return err; 647 648 /* soft reset */ 649 err = phy_write(phydev, MII_BMCR, BMCR_RESET); 650 if (err < 0) 651 return err; 652 do 653 temp = phy_read(phydev, MII_BMCR); 654 while (temp & BMCR_RESET); 655 656 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR); 657 if (temp < 0) 658 return temp; 659 temp &= ~(MII_M1111_HWCFG_MODE_MASK | MII_M1111_HWCFG_FIBER_COPPER_RES); 660 temp |= MII_M1111_HWCFG_MODE_COPPER_RTBI | MII_M1111_HWCFG_FIBER_COPPER_AUTO; 661 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp); 662 if (err < 0) 663 return err; 664 } 665 666 err = marvell_of_reg_init(phydev); 667 if (err < 0) 668 return err; 669 670 return phy_write(phydev, MII_BMCR, BMCR_RESET); 671 } 672 673 static int m88e1121_config_init(struct phy_device *phydev) 674 { 675 int err, oldpage; 676 677 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE); 678 679 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_88E1121_PHY_LED_PAGE); 680 if (err < 0) 681 return err; 682 683 /* Default PHY LED config: LED[0] .. Link, LED[1] .. Activity */ 684 err = phy_write(phydev, MII_88E1121_PHY_LED_CTRL, 685 MII_88E1121_PHY_LED_DEF); 686 if (err < 0) 687 return err; 688 689 phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage); 690 691 /* Set marvell,reg-init configuration from device tree */ 692 return marvell_config_init(phydev); 693 } 694 695 static int m88e1510_config_init(struct phy_device *phydev) 696 { 697 int err; 698 int temp; 699 700 /* SGMII-to-Copper mode initialization */ 701 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { 702 /* Select page 18 */ 703 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 18); 704 if (err < 0) 705 return err; 706 707 /* In reg 20, write MODE[2:0] = 0x1 (SGMII to Copper) */ 708 temp = phy_read(phydev, MII_88E1510_GEN_CTRL_REG_1); 709 temp &= ~MII_88E1510_GEN_CTRL_REG_1_MODE_MASK; 710 temp |= MII_88E1510_GEN_CTRL_REG_1_MODE_SGMII; 711 err = phy_write(phydev, MII_88E1510_GEN_CTRL_REG_1, temp); 712 if (err < 0) 713 return err; 714 715 /* PHY reset is necessary after changing MODE[2:0] */ 716 temp |= MII_88E1510_GEN_CTRL_REG_1_RESET; 717 err = phy_write(phydev, MII_88E1510_GEN_CTRL_REG_1, temp); 718 if (err < 0) 719 return err; 720 721 /* Reset page selection */ 722 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0); 723 if (err < 0) 724 return err; 725 } 726 727 return m88e1121_config_init(phydev); 728 } 729 730 static int m88e1118_config_aneg(struct phy_device *phydev) 731 { 732 int err; 733 734 err = phy_write(phydev, MII_BMCR, BMCR_RESET); 735 if (err < 0) 736 return err; 737 738 err = phy_write(phydev, MII_M1011_PHY_SCR, 739 MII_M1011_PHY_SCR_AUTO_CROSS); 740 if (err < 0) 741 return err; 742 743 err = genphy_config_aneg(phydev); 744 return 0; 745 } 746 747 static int m88e1118_config_init(struct phy_device *phydev) 748 { 749 int err; 750 751 /* Change address */ 752 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0002); 753 if (err < 0) 754 return err; 755 756 /* Enable 1000 Mbit */ 757 err = phy_write(phydev, 0x15, 0x1070); 758 if (err < 0) 759 return err; 760 761 /* Change address */ 762 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0003); 763 if (err < 0) 764 return err; 765 766 /* Adjust LED Control */ 767 if (phydev->dev_flags & MARVELL_PHY_M1118_DNS323_LEDS) 768 err = phy_write(phydev, 0x10, 0x1100); 769 else 770 err = phy_write(phydev, 0x10, 0x021e); 771 if (err < 0) 772 return err; 773 774 err = marvell_of_reg_init(phydev); 775 if (err < 0) 776 return err; 777 778 /* Reset address */ 779 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0); 780 if (err < 0) 781 return err; 782 783 return phy_write(phydev, MII_BMCR, BMCR_RESET); 784 } 785 786 static int m88e1149_config_init(struct phy_device *phydev) 787 { 788 int err; 789 790 /* Change address */ 791 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0002); 792 if (err < 0) 793 return err; 794 795 /* Enable 1000 Mbit */ 796 err = phy_write(phydev, 0x15, 0x1048); 797 if (err < 0) 798 return err; 799 800 err = marvell_of_reg_init(phydev); 801 if (err < 0) 802 return err; 803 804 /* Reset address */ 805 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0); 806 if (err < 0) 807 return err; 808 809 return phy_write(phydev, MII_BMCR, BMCR_RESET); 810 } 811 812 static int m88e1145_config_init(struct phy_device *phydev) 813 { 814 int err; 815 int temp; 816 817 /* Take care of errata E0 & E1 */ 818 err = phy_write(phydev, 0x1d, 0x001b); 819 if (err < 0) 820 return err; 821 822 err = phy_write(phydev, 0x1e, 0x418f); 823 if (err < 0) 824 return err; 825 826 err = phy_write(phydev, 0x1d, 0x0016); 827 if (err < 0) 828 return err; 829 830 err = phy_write(phydev, 0x1e, 0xa2da); 831 if (err < 0) 832 return err; 833 834 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) { 835 int temp = phy_read(phydev, MII_M1145_PHY_EXT_CR); 836 if (temp < 0) 837 return temp; 838 839 temp |= (MII_M1145_RGMII_RX_DELAY | MII_M1145_RGMII_TX_DELAY); 840 841 err = phy_write(phydev, MII_M1145_PHY_EXT_CR, temp); 842 if (err < 0) 843 return err; 844 845 if (phydev->dev_flags & MARVELL_PHY_M1145_FLAGS_RESISTANCE) { 846 err = phy_write(phydev, 0x1d, 0x0012); 847 if (err < 0) 848 return err; 849 850 temp = phy_read(phydev, 0x1e); 851 if (temp < 0) 852 return temp; 853 854 temp &= 0xf03f; 855 temp |= 2 << 9; /* 36 ohm */ 856 temp |= 2 << 6; /* 39 ohm */ 857 858 err = phy_write(phydev, 0x1e, temp); 859 if (err < 0) 860 return err; 861 862 err = phy_write(phydev, 0x1d, 0x3); 863 if (err < 0) 864 return err; 865 866 err = phy_write(phydev, 0x1e, 0x8000); 867 if (err < 0) 868 return err; 869 } 870 } 871 872 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { 873 temp = phy_read(phydev, MII_M1145_PHY_EXT_SR); 874 if (temp < 0) 875 return temp; 876 877 temp &= ~MII_M1145_HWCFG_MODE_MASK; 878 temp |= MII_M1145_HWCFG_MODE_SGMII_NO_CLK; 879 temp |= MII_M1145_HWCFG_FIBER_COPPER_AUTO; 880 881 err = phy_write(phydev, MII_M1145_PHY_EXT_SR, temp); 882 if (err < 0) 883 return err; 884 } 885 886 err = marvell_of_reg_init(phydev); 887 if (err < 0) 888 return err; 889 890 return 0; 891 } 892 893 /* marvell_read_status 894 * 895 * Generic status code does not detect Fiber correctly! 896 * Description: 897 * Check the link, then figure out the current state 898 * by comparing what we advertise with what the link partner 899 * advertises. Start by checking the gigabit possibilities, 900 * then move on to 10/100. 901 */ 902 static int marvell_read_status(struct phy_device *phydev) 903 { 904 int adv; 905 int err; 906 int lpa; 907 int lpagb; 908 int status = 0; 909 910 /* Update the link, but return if there 911 * was an error */ 912 err = genphy_update_link(phydev); 913 if (err) 914 return err; 915 916 if (AUTONEG_ENABLE == phydev->autoneg) { 917 status = phy_read(phydev, MII_M1011_PHY_STATUS); 918 if (status < 0) 919 return status; 920 921 lpa = phy_read(phydev, MII_LPA); 922 if (lpa < 0) 923 return lpa; 924 925 lpagb = phy_read(phydev, MII_STAT1000); 926 if (lpagb < 0) 927 return lpagb; 928 929 adv = phy_read(phydev, MII_ADVERTISE); 930 if (adv < 0) 931 return adv; 932 933 phydev->lp_advertising = mii_stat1000_to_ethtool_lpa_t(lpagb) | 934 mii_lpa_to_ethtool_lpa_t(lpa); 935 936 lpa &= adv; 937 938 if (status & MII_M1011_PHY_STATUS_FULLDUPLEX) 939 phydev->duplex = DUPLEX_FULL; 940 else 941 phydev->duplex = DUPLEX_HALF; 942 943 status = status & MII_M1011_PHY_STATUS_SPD_MASK; 944 phydev->pause = phydev->asym_pause = 0; 945 946 switch (status) { 947 case MII_M1011_PHY_STATUS_1000: 948 phydev->speed = SPEED_1000; 949 break; 950 951 case MII_M1011_PHY_STATUS_100: 952 phydev->speed = SPEED_100; 953 break; 954 955 default: 956 phydev->speed = SPEED_10; 957 break; 958 } 959 960 if (phydev->duplex == DUPLEX_FULL) { 961 phydev->pause = lpa & LPA_PAUSE_CAP ? 1 : 0; 962 phydev->asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0; 963 } 964 } else { 965 int bmcr = phy_read(phydev, MII_BMCR); 966 967 if (bmcr < 0) 968 return bmcr; 969 970 if (bmcr & BMCR_FULLDPLX) 971 phydev->duplex = DUPLEX_FULL; 972 else 973 phydev->duplex = DUPLEX_HALF; 974 975 if (bmcr & BMCR_SPEED1000) 976 phydev->speed = SPEED_1000; 977 else if (bmcr & BMCR_SPEED100) 978 phydev->speed = SPEED_100; 979 else 980 phydev->speed = SPEED_10; 981 982 phydev->pause = phydev->asym_pause = 0; 983 phydev->lp_advertising = 0; 984 } 985 986 return 0; 987 } 988 989 static int marvell_aneg_done(struct phy_device *phydev) 990 { 991 int retval = phy_read(phydev, MII_M1011_PHY_STATUS); 992 return (retval < 0) ? retval : (retval & MII_M1011_PHY_STATUS_RESOLVED); 993 } 994 995 static int m88e1121_did_interrupt(struct phy_device *phydev) 996 { 997 int imask; 998 999 imask = phy_read(phydev, MII_M1011_IEVENT); 1000 1001 if (imask & MII_M1011_IMASK_INIT) 1002 return 1; 1003 1004 return 0; 1005 } 1006 1007 static void m88e1318_get_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol) 1008 { 1009 wol->supported = WAKE_MAGIC; 1010 wol->wolopts = 0; 1011 1012 if (phy_write(phydev, MII_MARVELL_PHY_PAGE, 1013 MII_88E1318S_PHY_WOL_PAGE) < 0) 1014 return; 1015 1016 if (phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL) & 1017 MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE) 1018 wol->wolopts |= WAKE_MAGIC; 1019 1020 if (phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x00) < 0) 1021 return; 1022 } 1023 1024 static int m88e1318_set_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol) 1025 { 1026 int err, oldpage, temp; 1027 1028 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE); 1029 1030 if (wol->wolopts & WAKE_MAGIC) { 1031 /* Explicitly switch to page 0x00, just to be sure */ 1032 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x00); 1033 if (err < 0) 1034 return err; 1035 1036 /* Enable the WOL interrupt */ 1037 temp = phy_read(phydev, MII_88E1318S_PHY_CSIER); 1038 temp |= MII_88E1318S_PHY_CSIER_WOL_EIE; 1039 err = phy_write(phydev, MII_88E1318S_PHY_CSIER, temp); 1040 if (err < 0) 1041 return err; 1042 1043 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 1044 MII_88E1318S_PHY_LED_PAGE); 1045 if (err < 0) 1046 return err; 1047 1048 /* Setup LED[2] as interrupt pin (active low) */ 1049 temp = phy_read(phydev, MII_88E1318S_PHY_LED_TCR); 1050 temp &= ~MII_88E1318S_PHY_LED_TCR_FORCE_INT; 1051 temp |= MII_88E1318S_PHY_LED_TCR_INTn_ENABLE; 1052 temp |= MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW; 1053 err = phy_write(phydev, MII_88E1318S_PHY_LED_TCR, temp); 1054 if (err < 0) 1055 return err; 1056 1057 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 1058 MII_88E1318S_PHY_WOL_PAGE); 1059 if (err < 0) 1060 return err; 1061 1062 /* Store the device address for the magic packet */ 1063 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD2, 1064 ((phydev->attached_dev->dev_addr[5] << 8) | 1065 phydev->attached_dev->dev_addr[4])); 1066 if (err < 0) 1067 return err; 1068 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD1, 1069 ((phydev->attached_dev->dev_addr[3] << 8) | 1070 phydev->attached_dev->dev_addr[2])); 1071 if (err < 0) 1072 return err; 1073 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD0, 1074 ((phydev->attached_dev->dev_addr[1] << 8) | 1075 phydev->attached_dev->dev_addr[0])); 1076 if (err < 0) 1077 return err; 1078 1079 /* Clear WOL status and enable magic packet matching */ 1080 temp = phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL); 1081 temp |= MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS; 1082 temp |= MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE; 1083 err = phy_write(phydev, MII_88E1318S_PHY_WOL_CTRL, temp); 1084 if (err < 0) 1085 return err; 1086 } else { 1087 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 1088 MII_88E1318S_PHY_WOL_PAGE); 1089 if (err < 0) 1090 return err; 1091 1092 /* Clear WOL status and disable magic packet matching */ 1093 temp = phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL); 1094 temp |= MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS; 1095 temp &= ~MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE; 1096 err = phy_write(phydev, MII_88E1318S_PHY_WOL_CTRL, temp); 1097 if (err < 0) 1098 return err; 1099 } 1100 1101 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage); 1102 if (err < 0) 1103 return err; 1104 1105 return 0; 1106 } 1107 1108 static int marvell_get_sset_count(struct phy_device *phydev) 1109 { 1110 return ARRAY_SIZE(marvell_hw_stats); 1111 } 1112 1113 static void marvell_get_strings(struct phy_device *phydev, u8 *data) 1114 { 1115 int i; 1116 1117 for (i = 0; i < ARRAY_SIZE(marvell_hw_stats); i++) { 1118 memcpy(data + i * ETH_GSTRING_LEN, 1119 marvell_hw_stats[i].string, ETH_GSTRING_LEN); 1120 } 1121 } 1122 1123 #ifndef UINT64_MAX 1124 #define UINT64_MAX (u64)(~((u64)0)) 1125 #endif 1126 static u64 marvell_get_stat(struct phy_device *phydev, int i) 1127 { 1128 struct marvell_hw_stat stat = marvell_hw_stats[i]; 1129 struct marvell_priv *priv = phydev->priv; 1130 int err, oldpage, val; 1131 u64 ret; 1132 1133 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE); 1134 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 1135 stat.page); 1136 if (err < 0) 1137 return UINT64_MAX; 1138 1139 val = phy_read(phydev, stat.reg); 1140 if (val < 0) { 1141 ret = UINT64_MAX; 1142 } else { 1143 val = val & ((1 << stat.bits) - 1); 1144 priv->stats[i] += val; 1145 ret = priv->stats[i]; 1146 } 1147 1148 phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage); 1149 1150 return ret; 1151 } 1152 1153 static void marvell_get_stats(struct phy_device *phydev, 1154 struct ethtool_stats *stats, u64 *data) 1155 { 1156 int i; 1157 1158 for (i = 0; i < ARRAY_SIZE(marvell_hw_stats); i++) 1159 data[i] = marvell_get_stat(phydev, i); 1160 } 1161 1162 static int marvell_probe(struct phy_device *phydev) 1163 { 1164 struct marvell_priv *priv; 1165 1166 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); 1167 if (!priv) 1168 return -ENOMEM; 1169 1170 phydev->priv = priv; 1171 1172 return 0; 1173 } 1174 1175 static struct phy_driver marvell_drivers[] = { 1176 { 1177 .phy_id = MARVELL_PHY_ID_88E1101, 1178 .phy_id_mask = MARVELL_PHY_ID_MASK, 1179 .name = "Marvell 88E1101", 1180 .features = PHY_GBIT_FEATURES, 1181 .probe = marvell_probe, 1182 .flags = PHY_HAS_INTERRUPT, 1183 .config_init = &marvell_config_init, 1184 .config_aneg = &marvell_config_aneg, 1185 .read_status = &genphy_read_status, 1186 .ack_interrupt = &marvell_ack_interrupt, 1187 .config_intr = &marvell_config_intr, 1188 .resume = &genphy_resume, 1189 .suspend = &genphy_suspend, 1190 .get_sset_count = marvell_get_sset_count, 1191 .get_strings = marvell_get_strings, 1192 .get_stats = marvell_get_stats, 1193 }, 1194 { 1195 .phy_id = MARVELL_PHY_ID_88E1112, 1196 .phy_id_mask = MARVELL_PHY_ID_MASK, 1197 .name = "Marvell 88E1112", 1198 .features = PHY_GBIT_FEATURES, 1199 .flags = PHY_HAS_INTERRUPT, 1200 .probe = marvell_probe, 1201 .config_init = &m88e1111_config_init, 1202 .config_aneg = &marvell_config_aneg, 1203 .read_status = &genphy_read_status, 1204 .ack_interrupt = &marvell_ack_interrupt, 1205 .config_intr = &marvell_config_intr, 1206 .resume = &genphy_resume, 1207 .suspend = &genphy_suspend, 1208 .get_sset_count = marvell_get_sset_count, 1209 .get_strings = marvell_get_strings, 1210 .get_stats = marvell_get_stats, 1211 }, 1212 { 1213 .phy_id = MARVELL_PHY_ID_88E1111, 1214 .phy_id_mask = MARVELL_PHY_ID_MASK, 1215 .name = "Marvell 88E1111", 1216 .features = PHY_GBIT_FEATURES, 1217 .flags = PHY_HAS_INTERRUPT, 1218 .probe = marvell_probe, 1219 .config_init = &m88e1111_config_init, 1220 .config_aneg = &m88e1111_config_aneg, 1221 .read_status = &marvell_read_status, 1222 .ack_interrupt = &marvell_ack_interrupt, 1223 .config_intr = &marvell_config_intr, 1224 .resume = &genphy_resume, 1225 .suspend = &genphy_suspend, 1226 .get_sset_count = marvell_get_sset_count, 1227 .get_strings = marvell_get_strings, 1228 .get_stats = marvell_get_stats, 1229 }, 1230 { 1231 .phy_id = MARVELL_PHY_ID_88E1118, 1232 .phy_id_mask = MARVELL_PHY_ID_MASK, 1233 .name = "Marvell 88E1118", 1234 .features = PHY_GBIT_FEATURES, 1235 .flags = PHY_HAS_INTERRUPT, 1236 .probe = marvell_probe, 1237 .config_init = &m88e1118_config_init, 1238 .config_aneg = &m88e1118_config_aneg, 1239 .read_status = &genphy_read_status, 1240 .ack_interrupt = &marvell_ack_interrupt, 1241 .config_intr = &marvell_config_intr, 1242 .resume = &genphy_resume, 1243 .suspend = &genphy_suspend, 1244 .get_sset_count = marvell_get_sset_count, 1245 .get_strings = marvell_get_strings, 1246 .get_stats = marvell_get_stats, 1247 }, 1248 { 1249 .phy_id = MARVELL_PHY_ID_88E1121R, 1250 .phy_id_mask = MARVELL_PHY_ID_MASK, 1251 .name = "Marvell 88E1121R", 1252 .features = PHY_GBIT_FEATURES, 1253 .flags = PHY_HAS_INTERRUPT, 1254 .probe = marvell_probe, 1255 .config_init = &m88e1121_config_init, 1256 .config_aneg = &m88e1121_config_aneg, 1257 .read_status = &marvell_read_status, 1258 .ack_interrupt = &marvell_ack_interrupt, 1259 .config_intr = &marvell_config_intr, 1260 .did_interrupt = &m88e1121_did_interrupt, 1261 .resume = &genphy_resume, 1262 .suspend = &genphy_suspend, 1263 .get_sset_count = marvell_get_sset_count, 1264 .get_strings = marvell_get_strings, 1265 .get_stats = marvell_get_stats, 1266 }, 1267 { 1268 .phy_id = MARVELL_PHY_ID_88E1318S, 1269 .phy_id_mask = MARVELL_PHY_ID_MASK, 1270 .name = "Marvell 88E1318S", 1271 .features = PHY_GBIT_FEATURES, 1272 .flags = PHY_HAS_INTERRUPT, 1273 .probe = marvell_probe, 1274 .config_init = &m88e1121_config_init, 1275 .config_aneg = &m88e1318_config_aneg, 1276 .read_status = &marvell_read_status, 1277 .ack_interrupt = &marvell_ack_interrupt, 1278 .config_intr = &marvell_config_intr, 1279 .did_interrupt = &m88e1121_did_interrupt, 1280 .get_wol = &m88e1318_get_wol, 1281 .set_wol = &m88e1318_set_wol, 1282 .resume = &genphy_resume, 1283 .suspend = &genphy_suspend, 1284 .get_sset_count = marvell_get_sset_count, 1285 .get_strings = marvell_get_strings, 1286 .get_stats = marvell_get_stats, 1287 }, 1288 { 1289 .phy_id = MARVELL_PHY_ID_88E1145, 1290 .phy_id_mask = MARVELL_PHY_ID_MASK, 1291 .name = "Marvell 88E1145", 1292 .features = PHY_GBIT_FEATURES, 1293 .flags = PHY_HAS_INTERRUPT, 1294 .probe = marvell_probe, 1295 .config_init = &m88e1145_config_init, 1296 .config_aneg = &marvell_config_aneg, 1297 .read_status = &genphy_read_status, 1298 .ack_interrupt = &marvell_ack_interrupt, 1299 .config_intr = &marvell_config_intr, 1300 .resume = &genphy_resume, 1301 .suspend = &genphy_suspend, 1302 .get_sset_count = marvell_get_sset_count, 1303 .get_strings = marvell_get_strings, 1304 .get_stats = marvell_get_stats, 1305 }, 1306 { 1307 .phy_id = MARVELL_PHY_ID_88E1149R, 1308 .phy_id_mask = MARVELL_PHY_ID_MASK, 1309 .name = "Marvell 88E1149R", 1310 .features = PHY_GBIT_FEATURES, 1311 .flags = PHY_HAS_INTERRUPT, 1312 .probe = marvell_probe, 1313 .config_init = &m88e1149_config_init, 1314 .config_aneg = &m88e1118_config_aneg, 1315 .read_status = &genphy_read_status, 1316 .ack_interrupt = &marvell_ack_interrupt, 1317 .config_intr = &marvell_config_intr, 1318 .resume = &genphy_resume, 1319 .suspend = &genphy_suspend, 1320 .get_sset_count = marvell_get_sset_count, 1321 .get_strings = marvell_get_strings, 1322 .get_stats = marvell_get_stats, 1323 }, 1324 { 1325 .phy_id = MARVELL_PHY_ID_88E1240, 1326 .phy_id_mask = MARVELL_PHY_ID_MASK, 1327 .name = "Marvell 88E1240", 1328 .features = PHY_GBIT_FEATURES, 1329 .flags = PHY_HAS_INTERRUPT, 1330 .probe = marvell_probe, 1331 .config_init = &m88e1111_config_init, 1332 .config_aneg = &marvell_config_aneg, 1333 .read_status = &genphy_read_status, 1334 .ack_interrupt = &marvell_ack_interrupt, 1335 .config_intr = &marvell_config_intr, 1336 .resume = &genphy_resume, 1337 .suspend = &genphy_suspend, 1338 .get_sset_count = marvell_get_sset_count, 1339 .get_strings = marvell_get_strings, 1340 .get_stats = marvell_get_stats, 1341 }, 1342 { 1343 .phy_id = MARVELL_PHY_ID_88E1116R, 1344 .phy_id_mask = MARVELL_PHY_ID_MASK, 1345 .name = "Marvell 88E1116R", 1346 .features = PHY_GBIT_FEATURES, 1347 .flags = PHY_HAS_INTERRUPT, 1348 .probe = marvell_probe, 1349 .config_init = &m88e1116r_config_init, 1350 .config_aneg = &genphy_config_aneg, 1351 .read_status = &genphy_read_status, 1352 .ack_interrupt = &marvell_ack_interrupt, 1353 .config_intr = &marvell_config_intr, 1354 .resume = &genphy_resume, 1355 .suspend = &genphy_suspend, 1356 .get_sset_count = marvell_get_sset_count, 1357 .get_strings = marvell_get_strings, 1358 .get_stats = marvell_get_stats, 1359 }, 1360 { 1361 .phy_id = MARVELL_PHY_ID_88E1510, 1362 .phy_id_mask = MARVELL_PHY_ID_MASK, 1363 .name = "Marvell 88E1510", 1364 .features = PHY_GBIT_FEATURES, 1365 .flags = PHY_HAS_INTERRUPT, 1366 .probe = marvell_probe, 1367 .config_init = &m88e1510_config_init, 1368 .config_aneg = &m88e1510_config_aneg, 1369 .read_status = &marvell_read_status, 1370 .ack_interrupt = &marvell_ack_interrupt, 1371 .config_intr = &marvell_config_intr, 1372 .did_interrupt = &m88e1121_did_interrupt, 1373 .resume = &genphy_resume, 1374 .suspend = &genphy_suspend, 1375 .get_sset_count = marvell_get_sset_count, 1376 .get_strings = marvell_get_strings, 1377 .get_stats = marvell_get_stats, 1378 }, 1379 { 1380 .phy_id = MARVELL_PHY_ID_88E1540, 1381 .phy_id_mask = MARVELL_PHY_ID_MASK, 1382 .name = "Marvell 88E1540", 1383 .features = PHY_GBIT_FEATURES, 1384 .flags = PHY_HAS_INTERRUPT, 1385 .probe = marvell_probe, 1386 .config_init = &marvell_config_init, 1387 .config_aneg = &m88e1510_config_aneg, 1388 .read_status = &marvell_read_status, 1389 .ack_interrupt = &marvell_ack_interrupt, 1390 .config_intr = &marvell_config_intr, 1391 .did_interrupt = &m88e1121_did_interrupt, 1392 .resume = &genphy_resume, 1393 .suspend = &genphy_suspend, 1394 .get_sset_count = marvell_get_sset_count, 1395 .get_strings = marvell_get_strings, 1396 .get_stats = marvell_get_stats, 1397 }, 1398 { 1399 .phy_id = MARVELL_PHY_ID_88E3016, 1400 .phy_id_mask = MARVELL_PHY_ID_MASK, 1401 .name = "Marvell 88E3016", 1402 .features = PHY_BASIC_FEATURES, 1403 .flags = PHY_HAS_INTERRUPT, 1404 .probe = marvell_probe, 1405 .config_aneg = &genphy_config_aneg, 1406 .config_init = &m88e3016_config_init, 1407 .aneg_done = &marvell_aneg_done, 1408 .read_status = &marvell_read_status, 1409 .ack_interrupt = &marvell_ack_interrupt, 1410 .config_intr = &marvell_config_intr, 1411 .did_interrupt = &m88e1121_did_interrupt, 1412 .resume = &genphy_resume, 1413 .suspend = &genphy_suspend, 1414 .get_sset_count = marvell_get_sset_count, 1415 .get_strings = marvell_get_strings, 1416 .get_stats = marvell_get_stats, 1417 }, 1418 }; 1419 1420 module_phy_driver(marvell_drivers); 1421 1422 static struct mdio_device_id __maybe_unused marvell_tbl[] = { 1423 { MARVELL_PHY_ID_88E1101, MARVELL_PHY_ID_MASK }, 1424 { MARVELL_PHY_ID_88E1112, MARVELL_PHY_ID_MASK }, 1425 { MARVELL_PHY_ID_88E1111, MARVELL_PHY_ID_MASK }, 1426 { MARVELL_PHY_ID_88E1118, MARVELL_PHY_ID_MASK }, 1427 { MARVELL_PHY_ID_88E1121R, MARVELL_PHY_ID_MASK }, 1428 { MARVELL_PHY_ID_88E1145, MARVELL_PHY_ID_MASK }, 1429 { MARVELL_PHY_ID_88E1149R, MARVELL_PHY_ID_MASK }, 1430 { MARVELL_PHY_ID_88E1240, MARVELL_PHY_ID_MASK }, 1431 { MARVELL_PHY_ID_88E1318S, MARVELL_PHY_ID_MASK }, 1432 { MARVELL_PHY_ID_88E1116R, MARVELL_PHY_ID_MASK }, 1433 { MARVELL_PHY_ID_88E1510, MARVELL_PHY_ID_MASK }, 1434 { MARVELL_PHY_ID_88E1540, MARVELL_PHY_ID_MASK }, 1435 { MARVELL_PHY_ID_88E3016, MARVELL_PHY_ID_MASK }, 1436 { } 1437 }; 1438 1439 MODULE_DEVICE_TABLE(mdio, marvell_tbl); 1440