1 /* 2 * drivers/net/phy/lxt.c 3 * 4 * Driver for Intel LXT PHYs 5 * 6 * Author: Andy Fleming 7 * 8 * Copyright (c) 2004 Freescale Semiconductor, Inc. 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License as published by the 12 * Free Software Foundation; either version 2 of the License, or (at your 13 * option) any later version. 14 * 15 */ 16 #include <linux/kernel.h> 17 #include <linux/string.h> 18 #include <linux/errno.h> 19 #include <linux/unistd.h> 20 #include <linux/interrupt.h> 21 #include <linux/init.h> 22 #include <linux/delay.h> 23 #include <linux/netdevice.h> 24 #include <linux/etherdevice.h> 25 #include <linux/skbuff.h> 26 #include <linux/spinlock.h> 27 #include <linux/mm.h> 28 #include <linux/module.h> 29 #include <linux/mii.h> 30 #include <linux/ethtool.h> 31 #include <linux/phy.h> 32 33 #include <asm/io.h> 34 #include <asm/irq.h> 35 #include <linux/uaccess.h> 36 37 /* The Level one LXT970 is used by many boards */ 38 39 #define MII_LXT970_IER 17 /* Interrupt Enable Register */ 40 41 #define MII_LXT970_IER_IEN 0x0002 42 43 #define MII_LXT970_ISR 18 /* Interrupt Status Register */ 44 45 #define MII_LXT970_CONFIG 19 /* Configuration Register */ 46 47 /* ------------------------------------------------------------------------- */ 48 /* The Level one LXT971 is used on some of my custom boards */ 49 50 /* register definitions for the 971 */ 51 #define MII_LXT971_IER 18 /* Interrupt Enable Register */ 52 #define MII_LXT971_IER_IEN 0x00f2 53 54 #define MII_LXT971_ISR 19 /* Interrupt Status Register */ 55 56 /* register definitions for the 973 */ 57 #define MII_LXT973_PCR 16 /* Port Configuration Register */ 58 #define PCR_FIBER_SELECT 1 59 60 MODULE_DESCRIPTION("Intel LXT PHY driver"); 61 MODULE_AUTHOR("Andy Fleming"); 62 MODULE_LICENSE("GPL"); 63 64 static int lxt970_ack_interrupt(struct phy_device *phydev) 65 { 66 int err; 67 68 err = phy_read(phydev, MII_BMSR); 69 70 if (err < 0) 71 return err; 72 73 err = phy_read(phydev, MII_LXT970_ISR); 74 75 if (err < 0) 76 return err; 77 78 return 0; 79 } 80 81 static int lxt970_config_intr(struct phy_device *phydev) 82 { 83 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) 84 return phy_write(phydev, MII_LXT970_IER, MII_LXT970_IER_IEN); 85 else 86 return phy_write(phydev, MII_LXT970_IER, 0); 87 } 88 89 static int lxt970_config_init(struct phy_device *phydev) 90 { 91 return phy_write(phydev, MII_LXT970_CONFIG, 0); 92 } 93 94 95 static int lxt971_ack_interrupt(struct phy_device *phydev) 96 { 97 int err = phy_read(phydev, MII_LXT971_ISR); 98 99 if (err < 0) 100 return err; 101 102 return 0; 103 } 104 105 static int lxt971_config_intr(struct phy_device *phydev) 106 { 107 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) 108 return phy_write(phydev, MII_LXT971_IER, MII_LXT971_IER_IEN); 109 else 110 return phy_write(phydev, MII_LXT971_IER, 0); 111 } 112 113 /* 114 * A2 version of LXT973 chip has an ERRATA: it randomly return the contents 115 * of the previous even register when you read a odd register regularly 116 */ 117 118 static int lxt973a2_update_link(struct phy_device *phydev) 119 { 120 int status; 121 int control; 122 int retry = 8; /* we try 8 times */ 123 124 /* Do a fake read */ 125 status = phy_read(phydev, MII_BMSR); 126 127 if (status < 0) 128 return status; 129 130 control = phy_read(phydev, MII_BMCR); 131 if (control < 0) 132 return control; 133 134 do { 135 /* Read link and autonegotiation status */ 136 status = phy_read(phydev, MII_BMSR); 137 } while (status >= 0 && retry-- && status == control); 138 139 if (status < 0) 140 return status; 141 142 if ((status & BMSR_LSTATUS) == 0) 143 phydev->link = 0; 144 else 145 phydev->link = 1; 146 147 return 0; 148 } 149 150 static int lxt973a2_read_status(struct phy_device *phydev) 151 { 152 int adv; 153 int err; 154 int lpa; 155 156 /* Update the link, but return if there was an error */ 157 err = lxt973a2_update_link(phydev); 158 if (err) 159 return err; 160 161 if (AUTONEG_ENABLE == phydev->autoneg) { 162 int retry = 1; 163 164 adv = phy_read(phydev, MII_ADVERTISE); 165 166 if (adv < 0) 167 return adv; 168 169 do { 170 lpa = phy_read(phydev, MII_LPA); 171 172 if (lpa < 0) 173 return lpa; 174 175 /* If both registers are equal, it is suspect but not 176 * impossible, hence a new try 177 */ 178 } while (lpa == adv && retry--); 179 180 phydev->lp_advertising = mii_lpa_to_ethtool_lpa_t(lpa); 181 182 lpa &= adv; 183 184 phydev->speed = SPEED_10; 185 phydev->duplex = DUPLEX_HALF; 186 phydev->pause = phydev->asym_pause = 0; 187 188 if (lpa & (LPA_100FULL | LPA_100HALF)) { 189 phydev->speed = SPEED_100; 190 191 if (lpa & LPA_100FULL) 192 phydev->duplex = DUPLEX_FULL; 193 } else { 194 if (lpa & LPA_10FULL) 195 phydev->duplex = DUPLEX_FULL; 196 } 197 198 if (phydev->duplex == DUPLEX_FULL) { 199 phydev->pause = lpa & LPA_PAUSE_CAP ? 1 : 0; 200 phydev->asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0; 201 } 202 } else { 203 int bmcr = phy_read(phydev, MII_BMCR); 204 205 if (bmcr < 0) 206 return bmcr; 207 208 if (bmcr & BMCR_FULLDPLX) 209 phydev->duplex = DUPLEX_FULL; 210 else 211 phydev->duplex = DUPLEX_HALF; 212 213 if (bmcr & BMCR_SPEED1000) 214 phydev->speed = SPEED_1000; 215 else if (bmcr & BMCR_SPEED100) 216 phydev->speed = SPEED_100; 217 else 218 phydev->speed = SPEED_10; 219 220 phydev->pause = phydev->asym_pause = 0; 221 phydev->lp_advertising = 0; 222 } 223 224 return 0; 225 } 226 227 static int lxt973_probe(struct phy_device *phydev) 228 { 229 int val = phy_read(phydev, MII_LXT973_PCR); 230 231 if (val & PCR_FIBER_SELECT) { 232 /* 233 * If fiber is selected, then the only correct setting 234 * is 100Mbps, full duplex, and auto negotiation off. 235 */ 236 val = phy_read(phydev, MII_BMCR); 237 val |= (BMCR_SPEED100 | BMCR_FULLDPLX); 238 val &= ~BMCR_ANENABLE; 239 phy_write(phydev, MII_BMCR, val); 240 /* Remember that the port is in fiber mode. */ 241 phydev->priv = lxt973_probe; 242 } else { 243 phydev->priv = NULL; 244 } 245 return 0; 246 } 247 248 static int lxt973_config_aneg(struct phy_device *phydev) 249 { 250 /* Do nothing if port is in fiber mode. */ 251 return phydev->priv ? 0 : genphy_config_aneg(phydev); 252 } 253 254 static struct phy_driver lxt97x_driver[] = { 255 { 256 .phy_id = 0x78100000, 257 .name = "LXT970", 258 .phy_id_mask = 0xfffffff0, 259 .features = PHY_BASIC_FEATURES, 260 .flags = PHY_HAS_INTERRUPT, 261 .config_init = lxt970_config_init, 262 .config_aneg = genphy_config_aneg, 263 .read_status = genphy_read_status, 264 .ack_interrupt = lxt970_ack_interrupt, 265 .config_intr = lxt970_config_intr, 266 }, { 267 .phy_id = 0x001378e0, 268 .name = "LXT971", 269 .phy_id_mask = 0xfffffff0, 270 .features = PHY_BASIC_FEATURES, 271 .flags = PHY_HAS_INTERRUPT, 272 .config_aneg = genphy_config_aneg, 273 .read_status = genphy_read_status, 274 .ack_interrupt = lxt971_ack_interrupt, 275 .config_intr = lxt971_config_intr, 276 }, { 277 .phy_id = 0x00137a10, 278 .name = "LXT973-A2", 279 .phy_id_mask = 0xffffffff, 280 .features = PHY_BASIC_FEATURES, 281 .flags = 0, 282 .probe = lxt973_probe, 283 .config_aneg = lxt973_config_aneg, 284 .read_status = lxt973a2_read_status, 285 }, { 286 .phy_id = 0x00137a10, 287 .name = "LXT973", 288 .phy_id_mask = 0xfffffff0, 289 .features = PHY_BASIC_FEATURES, 290 .flags = 0, 291 .probe = lxt973_probe, 292 .config_aneg = lxt973_config_aneg, 293 .read_status = genphy_read_status, 294 } }; 295 296 module_phy_driver(lxt97x_driver); 297 298 static struct mdio_device_id __maybe_unused lxt_tbl[] = { 299 { 0x78100000, 0xfffffff0 }, 300 { 0x001378e0, 0xfffffff0 }, 301 { 0x00137a10, 0xfffffff0 }, 302 { } 303 }; 304 305 MODULE_DEVICE_TABLE(mdio, lxt_tbl); 306