1 /* 2 * Copyright (C) 2012 Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> 3 * Copyright (C) 2016 Hauke Mehrtens <hauke@hauke-m.de> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #include <linux/mdio.h> 17 #include <linux/module.h> 18 #include <linux/phy.h> 19 #include <linux/of.h> 20 21 #define XWAY_MDIO_IMASK 0x19 /* interrupt mask */ 22 #define XWAY_MDIO_ISTAT 0x1A /* interrupt status */ 23 24 #define XWAY_MDIO_INIT_WOL BIT(15) /* Wake-On-LAN */ 25 #define XWAY_MDIO_INIT_MSRE BIT(14) 26 #define XWAY_MDIO_INIT_NPRX BIT(13) 27 #define XWAY_MDIO_INIT_NPTX BIT(12) 28 #define XWAY_MDIO_INIT_ANE BIT(11) /* Auto-Neg error */ 29 #define XWAY_MDIO_INIT_ANC BIT(10) /* Auto-Neg complete */ 30 #define XWAY_MDIO_INIT_ADSC BIT(5) /* Link auto-downspeed detect */ 31 #define XWAY_MDIO_INIT_MPIPC BIT(4) 32 #define XWAY_MDIO_INIT_MDIXC BIT(3) 33 #define XWAY_MDIO_INIT_DXMC BIT(2) /* Duplex mode change */ 34 #define XWAY_MDIO_INIT_LSPC BIT(1) /* Link speed change */ 35 #define XWAY_MDIO_INIT_LSTC BIT(0) /* Link state change */ 36 #define XWAY_MDIO_INIT_MASK (XWAY_MDIO_INIT_LSTC | \ 37 XWAY_MDIO_INIT_ADSC) 38 39 #define ADVERTISED_MPD BIT(10) /* Multi-port device */ 40 41 /* LED Configuration */ 42 #define XWAY_MMD_LEDCH 0x01E0 43 /* Inverse of SCAN Function */ 44 #define XWAY_MMD_LEDCH_NACS_NONE 0x0000 45 #define XWAY_MMD_LEDCH_NACS_LINK 0x0001 46 #define XWAY_MMD_LEDCH_NACS_PDOWN 0x0002 47 #define XWAY_MMD_LEDCH_NACS_EEE 0x0003 48 #define XWAY_MMD_LEDCH_NACS_ANEG 0x0004 49 #define XWAY_MMD_LEDCH_NACS_ABIST 0x0005 50 #define XWAY_MMD_LEDCH_NACS_CDIAG 0x0006 51 #define XWAY_MMD_LEDCH_NACS_TEST 0x0007 52 /* Slow Blink Frequency */ 53 #define XWAY_MMD_LEDCH_SBF_F02HZ 0x0000 54 #define XWAY_MMD_LEDCH_SBF_F04HZ 0x0010 55 #define XWAY_MMD_LEDCH_SBF_F08HZ 0x0020 56 #define XWAY_MMD_LEDCH_SBF_F16HZ 0x0030 57 /* Fast Blink Frequency */ 58 #define XWAY_MMD_LEDCH_FBF_F02HZ 0x0000 59 #define XWAY_MMD_LEDCH_FBF_F04HZ 0x0040 60 #define XWAY_MMD_LEDCH_FBF_F08HZ 0x0080 61 #define XWAY_MMD_LEDCH_FBF_F16HZ 0x00C0 62 /* LED Configuration */ 63 #define XWAY_MMD_LEDCL 0x01E1 64 /* Complex Blinking Configuration */ 65 #define XWAY_MMD_LEDCH_CBLINK_NONE 0x0000 66 #define XWAY_MMD_LEDCH_CBLINK_LINK 0x0001 67 #define XWAY_MMD_LEDCH_CBLINK_PDOWN 0x0002 68 #define XWAY_MMD_LEDCH_CBLINK_EEE 0x0003 69 #define XWAY_MMD_LEDCH_CBLINK_ANEG 0x0004 70 #define XWAY_MMD_LEDCH_CBLINK_ABIST 0x0005 71 #define XWAY_MMD_LEDCH_CBLINK_CDIAG 0x0006 72 #define XWAY_MMD_LEDCH_CBLINK_TEST 0x0007 73 /* Complex SCAN Configuration */ 74 #define XWAY_MMD_LEDCH_SCAN_NONE 0x0000 75 #define XWAY_MMD_LEDCH_SCAN_LINK 0x0010 76 #define XWAY_MMD_LEDCH_SCAN_PDOWN 0x0020 77 #define XWAY_MMD_LEDCH_SCAN_EEE 0x0030 78 #define XWAY_MMD_LEDCH_SCAN_ANEG 0x0040 79 #define XWAY_MMD_LEDCH_SCAN_ABIST 0x0050 80 #define XWAY_MMD_LEDCH_SCAN_CDIAG 0x0060 81 #define XWAY_MMD_LEDCH_SCAN_TEST 0x0070 82 /* Configuration for LED Pin x */ 83 #define XWAY_MMD_LED0H 0x01E2 84 /* Fast Blinking Configuration */ 85 #define XWAY_MMD_LEDxH_BLINKF_MASK 0x000F 86 #define XWAY_MMD_LEDxH_BLINKF_NONE 0x0000 87 #define XWAY_MMD_LEDxH_BLINKF_LINK10 0x0001 88 #define XWAY_MMD_LEDxH_BLINKF_LINK100 0x0002 89 #define XWAY_MMD_LEDxH_BLINKF_LINK10X 0x0003 90 #define XWAY_MMD_LEDxH_BLINKF_LINK1000 0x0004 91 #define XWAY_MMD_LEDxH_BLINKF_LINK10_0 0x0005 92 #define XWAY_MMD_LEDxH_BLINKF_LINK100X 0x0006 93 #define XWAY_MMD_LEDxH_BLINKF_LINK10XX 0x0007 94 #define XWAY_MMD_LEDxH_BLINKF_PDOWN 0x0008 95 #define XWAY_MMD_LEDxH_BLINKF_EEE 0x0009 96 #define XWAY_MMD_LEDxH_BLINKF_ANEG 0x000A 97 #define XWAY_MMD_LEDxH_BLINKF_ABIST 0x000B 98 #define XWAY_MMD_LEDxH_BLINKF_CDIAG 0x000C 99 /* Constant On Configuration */ 100 #define XWAY_MMD_LEDxH_CON_MASK 0x00F0 101 #define XWAY_MMD_LEDxH_CON_NONE 0x0000 102 #define XWAY_MMD_LEDxH_CON_LINK10 0x0010 103 #define XWAY_MMD_LEDxH_CON_LINK100 0x0020 104 #define XWAY_MMD_LEDxH_CON_LINK10X 0x0030 105 #define XWAY_MMD_LEDxH_CON_LINK1000 0x0040 106 #define XWAY_MMD_LEDxH_CON_LINK10_0 0x0050 107 #define XWAY_MMD_LEDxH_CON_LINK100X 0x0060 108 #define XWAY_MMD_LEDxH_CON_LINK10XX 0x0070 109 #define XWAY_MMD_LEDxH_CON_PDOWN 0x0080 110 #define XWAY_MMD_LEDxH_CON_EEE 0x0090 111 #define XWAY_MMD_LEDxH_CON_ANEG 0x00A0 112 #define XWAY_MMD_LEDxH_CON_ABIST 0x00B0 113 #define XWAY_MMD_LEDxH_CON_CDIAG 0x00C0 114 #define XWAY_MMD_LEDxH_CON_COPPER 0x00D0 115 #define XWAY_MMD_LEDxH_CON_FIBER 0x00E0 116 /* Configuration for LED Pin x */ 117 #define XWAY_MMD_LED0L 0x01E3 118 /* Pulsing Configuration */ 119 #define XWAY_MMD_LEDxL_PULSE_MASK 0x000F 120 #define XWAY_MMD_LEDxL_PULSE_NONE 0x0000 121 #define XWAY_MMD_LEDxL_PULSE_TXACT 0x0001 122 #define XWAY_MMD_LEDxL_PULSE_RXACT 0x0002 123 #define XWAY_MMD_LEDxL_PULSE_COL 0x0004 124 /* Slow Blinking Configuration */ 125 #define XWAY_MMD_LEDxL_BLINKS_MASK 0x00F0 126 #define XWAY_MMD_LEDxL_BLINKS_NONE 0x0000 127 #define XWAY_MMD_LEDxL_BLINKS_LINK10 0x0010 128 #define XWAY_MMD_LEDxL_BLINKS_LINK100 0x0020 129 #define XWAY_MMD_LEDxL_BLINKS_LINK10X 0x0030 130 #define XWAY_MMD_LEDxL_BLINKS_LINK1000 0x0040 131 #define XWAY_MMD_LEDxL_BLINKS_LINK10_0 0x0050 132 #define XWAY_MMD_LEDxL_BLINKS_LINK100X 0x0060 133 #define XWAY_MMD_LEDxL_BLINKS_LINK10XX 0x0070 134 #define XWAY_MMD_LEDxL_BLINKS_PDOWN 0x0080 135 #define XWAY_MMD_LEDxL_BLINKS_EEE 0x0090 136 #define XWAY_MMD_LEDxL_BLINKS_ANEG 0x00A0 137 #define XWAY_MMD_LEDxL_BLINKS_ABIST 0x00B0 138 #define XWAY_MMD_LEDxL_BLINKS_CDIAG 0x00C0 139 #define XWAY_MMD_LED1H 0x01E4 140 #define XWAY_MMD_LED1L 0x01E5 141 #define XWAY_MMD_LED2H 0x01E6 142 #define XWAY_MMD_LED2L 0x01E7 143 #define XWAY_MMD_LED3H 0x01E8 144 #define XWAY_MMD_LED3L 0x01E9 145 146 #define PHY_ID_PHY11G_1_3 0x030260D1 147 #define PHY_ID_PHY22F_1_3 0x030260E1 148 #define PHY_ID_PHY11G_1_4 0xD565A400 149 #define PHY_ID_PHY22F_1_4 0xD565A410 150 #define PHY_ID_PHY11G_1_5 0xD565A401 151 #define PHY_ID_PHY22F_1_5 0xD565A411 152 #define PHY_ID_PHY11G_VR9_1_1 0xD565A408 153 #define PHY_ID_PHY22F_VR9_1_1 0xD565A418 154 #define PHY_ID_PHY11G_VR9_1_2 0xD565A409 155 #define PHY_ID_PHY22F_VR9_1_2 0xD565A419 156 157 static int xway_gphy_config_init(struct phy_device *phydev) 158 { 159 int err; 160 u32 ledxh; 161 u32 ledxl; 162 163 /* Mask all interrupts */ 164 err = phy_write(phydev, XWAY_MDIO_IMASK, 0); 165 if (err) 166 return err; 167 168 /* Clear all pending interrupts */ 169 phy_read(phydev, XWAY_MDIO_ISTAT); 170 171 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDCH, 172 XWAY_MMD_LEDCH_NACS_NONE | 173 XWAY_MMD_LEDCH_SBF_F02HZ | 174 XWAY_MMD_LEDCH_FBF_F16HZ); 175 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDCL, 176 XWAY_MMD_LEDCH_CBLINK_NONE | 177 XWAY_MMD_LEDCH_SCAN_NONE); 178 179 /** 180 * In most cases only one LED is connected to this phy, so 181 * configure them all to constant on and pulse mode. LED3 is 182 * only available in some packages, leave it in its reset 183 * configuration. 184 */ 185 ledxh = XWAY_MMD_LEDxH_BLINKF_NONE | XWAY_MMD_LEDxH_CON_LINK10XX; 186 ledxl = XWAY_MMD_LEDxL_PULSE_TXACT | XWAY_MMD_LEDxL_PULSE_RXACT | 187 XWAY_MMD_LEDxL_BLINKS_NONE; 188 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED0H, ledxh); 189 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED0L, ledxl); 190 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED1H, ledxh); 191 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED1L, ledxl); 192 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2H, ledxh); 193 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2L, ledxl); 194 195 return 0; 196 } 197 198 static int xway_gphy14_config_aneg(struct phy_device *phydev) 199 { 200 int reg, err; 201 202 /* Advertise as multi-port device, see IEEE802.3-2002 40.5.1.1 */ 203 /* This is a workaround for an errata in rev < 1.5 devices */ 204 reg = phy_read(phydev, MII_CTRL1000); 205 reg |= ADVERTISED_MPD; 206 err = phy_write(phydev, MII_CTRL1000, reg); 207 if (err) 208 return err; 209 210 return genphy_config_aneg(phydev); 211 } 212 213 static int xway_gphy_ack_interrupt(struct phy_device *phydev) 214 { 215 int reg; 216 217 reg = phy_read(phydev, XWAY_MDIO_ISTAT); 218 return (reg < 0) ? reg : 0; 219 } 220 221 static int xway_gphy_did_interrupt(struct phy_device *phydev) 222 { 223 int reg; 224 225 reg = phy_read(phydev, XWAY_MDIO_ISTAT); 226 return reg & XWAY_MDIO_INIT_MASK; 227 } 228 229 static int xway_gphy_config_intr(struct phy_device *phydev) 230 { 231 u16 mask = 0; 232 233 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) 234 mask = XWAY_MDIO_INIT_MASK; 235 236 return phy_write(phydev, XWAY_MDIO_IMASK, mask); 237 } 238 239 static struct phy_driver xway_gphy[] = { 240 { 241 .phy_id = PHY_ID_PHY11G_1_3, 242 .phy_id_mask = 0xffffffff, 243 .name = "Intel XWAY PHY11G (PEF 7071/PEF 7072) v1.3", 244 .features = PHY_GBIT_FEATURES, 245 .config_init = xway_gphy_config_init, 246 .config_aneg = xway_gphy14_config_aneg, 247 .ack_interrupt = xway_gphy_ack_interrupt, 248 .did_interrupt = xway_gphy_did_interrupt, 249 .config_intr = xway_gphy_config_intr, 250 .suspend = genphy_suspend, 251 .resume = genphy_resume, 252 }, { 253 .phy_id = PHY_ID_PHY22F_1_3, 254 .phy_id_mask = 0xffffffff, 255 .name = "Intel XWAY PHY22F (PEF 7061) v1.3", 256 .features = PHY_BASIC_FEATURES, 257 .config_init = xway_gphy_config_init, 258 .config_aneg = xway_gphy14_config_aneg, 259 .ack_interrupt = xway_gphy_ack_interrupt, 260 .did_interrupt = xway_gphy_did_interrupt, 261 .config_intr = xway_gphy_config_intr, 262 .suspend = genphy_suspend, 263 .resume = genphy_resume, 264 }, { 265 .phy_id = PHY_ID_PHY11G_1_4, 266 .phy_id_mask = 0xffffffff, 267 .name = "Intel XWAY PHY11G (PEF 7071/PEF 7072) v1.4", 268 .features = PHY_GBIT_FEATURES, 269 .config_init = xway_gphy_config_init, 270 .config_aneg = xway_gphy14_config_aneg, 271 .ack_interrupt = xway_gphy_ack_interrupt, 272 .did_interrupt = xway_gphy_did_interrupt, 273 .config_intr = xway_gphy_config_intr, 274 .suspend = genphy_suspend, 275 .resume = genphy_resume, 276 }, { 277 .phy_id = PHY_ID_PHY22F_1_4, 278 .phy_id_mask = 0xffffffff, 279 .name = "Intel XWAY PHY22F (PEF 7061) v1.4", 280 .features = PHY_BASIC_FEATURES, 281 .config_init = xway_gphy_config_init, 282 .config_aneg = xway_gphy14_config_aneg, 283 .ack_interrupt = xway_gphy_ack_interrupt, 284 .did_interrupt = xway_gphy_did_interrupt, 285 .config_intr = xway_gphy_config_intr, 286 .suspend = genphy_suspend, 287 .resume = genphy_resume, 288 }, { 289 .phy_id = PHY_ID_PHY11G_1_5, 290 .phy_id_mask = 0xffffffff, 291 .name = "Intel XWAY PHY11G (PEF 7071/PEF 7072) v1.5 / v1.6", 292 .features = PHY_GBIT_FEATURES, 293 .config_init = xway_gphy_config_init, 294 .ack_interrupt = xway_gphy_ack_interrupt, 295 .did_interrupt = xway_gphy_did_interrupt, 296 .config_intr = xway_gphy_config_intr, 297 .suspend = genphy_suspend, 298 .resume = genphy_resume, 299 }, { 300 .phy_id = PHY_ID_PHY22F_1_5, 301 .phy_id_mask = 0xffffffff, 302 .name = "Intel XWAY PHY22F (PEF 7061) v1.5 / v1.6", 303 .features = PHY_BASIC_FEATURES, 304 .config_init = xway_gphy_config_init, 305 .ack_interrupt = xway_gphy_ack_interrupt, 306 .did_interrupt = xway_gphy_did_interrupt, 307 .config_intr = xway_gphy_config_intr, 308 .suspend = genphy_suspend, 309 .resume = genphy_resume, 310 }, { 311 .phy_id = PHY_ID_PHY11G_VR9_1_1, 312 .phy_id_mask = 0xffffffff, 313 .name = "Intel XWAY PHY11G (xRX v1.1 integrated)", 314 .features = PHY_GBIT_FEATURES, 315 .config_init = xway_gphy_config_init, 316 .ack_interrupt = xway_gphy_ack_interrupt, 317 .did_interrupt = xway_gphy_did_interrupt, 318 .config_intr = xway_gphy_config_intr, 319 .suspend = genphy_suspend, 320 .resume = genphy_resume, 321 }, { 322 .phy_id = PHY_ID_PHY22F_VR9_1_1, 323 .phy_id_mask = 0xffffffff, 324 .name = "Intel XWAY PHY22F (xRX v1.1 integrated)", 325 .features = PHY_BASIC_FEATURES, 326 .config_init = xway_gphy_config_init, 327 .ack_interrupt = xway_gphy_ack_interrupt, 328 .did_interrupt = xway_gphy_did_interrupt, 329 .config_intr = xway_gphy_config_intr, 330 .suspend = genphy_suspend, 331 .resume = genphy_resume, 332 }, { 333 .phy_id = PHY_ID_PHY11G_VR9_1_2, 334 .phy_id_mask = 0xffffffff, 335 .name = "Intel XWAY PHY11G (xRX v1.2 integrated)", 336 .features = PHY_GBIT_FEATURES, 337 .config_init = xway_gphy_config_init, 338 .ack_interrupt = xway_gphy_ack_interrupt, 339 .did_interrupt = xway_gphy_did_interrupt, 340 .config_intr = xway_gphy_config_intr, 341 .suspend = genphy_suspend, 342 .resume = genphy_resume, 343 }, { 344 .phy_id = PHY_ID_PHY22F_VR9_1_2, 345 .phy_id_mask = 0xffffffff, 346 .name = "Intel XWAY PHY22F (xRX v1.2 integrated)", 347 .features = PHY_BASIC_FEATURES, 348 .config_init = xway_gphy_config_init, 349 .ack_interrupt = xway_gphy_ack_interrupt, 350 .did_interrupt = xway_gphy_did_interrupt, 351 .config_intr = xway_gphy_config_intr, 352 .suspend = genphy_suspend, 353 .resume = genphy_resume, 354 }, 355 }; 356 module_phy_driver(xway_gphy); 357 358 static struct mdio_device_id __maybe_unused xway_gphy_tbl[] = { 359 { PHY_ID_PHY11G_1_3, 0xffffffff }, 360 { PHY_ID_PHY22F_1_3, 0xffffffff }, 361 { PHY_ID_PHY11G_1_4, 0xffffffff }, 362 { PHY_ID_PHY22F_1_4, 0xffffffff }, 363 { PHY_ID_PHY11G_1_5, 0xffffffff }, 364 { PHY_ID_PHY22F_1_5, 0xffffffff }, 365 { PHY_ID_PHY11G_VR9_1_1, 0xffffffff }, 366 { PHY_ID_PHY22F_VR9_1_1, 0xffffffff }, 367 { PHY_ID_PHY11G_VR9_1_2, 0xffffffff }, 368 { PHY_ID_PHY22F_VR9_1_2, 0xffffffff }, 369 { } 370 }; 371 MODULE_DEVICE_TABLE(mdio, xway_gphy_tbl); 372 373 MODULE_DESCRIPTION("Intel XWAY PHY driver"); 374 MODULE_LICENSE("GPL"); 375