1 // SPDX-License-Identifier: GPL-2.0 2 /* Driver for the Texas Instruments DP83869 PHY 3 * Copyright (C) 2019 Texas Instruments Inc. 4 */ 5 6 #include <linux/ethtool.h> 7 #include <linux/etherdevice.h> 8 #include <linux/kernel.h> 9 #include <linux/mii.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/phy.h> 13 #include <linux/delay.h> 14 #include <linux/bitfield.h> 15 16 #include <dt-bindings/net/ti-dp83869.h> 17 18 #define DP83869_PHY_ID 0x2000a0f1 19 #define DP83869_DEVADDR 0x1f 20 21 #define MII_DP83869_PHYCTRL 0x10 22 #define MII_DP83869_MICR 0x12 23 #define MII_DP83869_ISR 0x13 24 #define DP83869_CFG2 0x14 25 #define DP83869_CTRL 0x1f 26 #define DP83869_CFG4 0x1e 27 28 /* Extended Registers */ 29 #define DP83869_GEN_CFG3 0x0031 30 #define DP83869_RGMIICTL 0x0032 31 #define DP83869_STRAP_STS1 0x006e 32 #define DP83869_RGMIIDCTL 0x0086 33 #define DP83869_RXFCFG 0x0134 34 #define DP83869_RXFPMD1 0x0136 35 #define DP83869_RXFPMD2 0x0137 36 #define DP83869_RXFPMD3 0x0138 37 #define DP83869_RXFSOP1 0x0139 38 #define DP83869_RXFSOP2 0x013A 39 #define DP83869_RXFSOP3 0x013B 40 #define DP83869_IO_MUX_CFG 0x0170 41 #define DP83869_OP_MODE 0x01df 42 #define DP83869_FX_CTRL 0x0c00 43 44 #define DP83869_SW_RESET BIT(15) 45 #define DP83869_SW_RESTART BIT(14) 46 47 /* MICR Interrupt bits */ 48 #define MII_DP83869_MICR_AN_ERR_INT_EN BIT(15) 49 #define MII_DP83869_MICR_SPEED_CHNG_INT_EN BIT(14) 50 #define MII_DP83869_MICR_DUP_MODE_CHNG_INT_EN BIT(13) 51 #define MII_DP83869_MICR_PAGE_RXD_INT_EN BIT(12) 52 #define MII_DP83869_MICR_AUTONEG_COMP_INT_EN BIT(11) 53 #define MII_DP83869_MICR_LINK_STS_CHNG_INT_EN BIT(10) 54 #define MII_DP83869_MICR_FALSE_CARRIER_INT_EN BIT(8) 55 #define MII_DP83869_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4) 56 #define MII_DP83869_MICR_WOL_INT_EN BIT(3) 57 #define MII_DP83869_MICR_XGMII_ERR_INT_EN BIT(2) 58 #define MII_DP83869_MICR_POL_CHNG_INT_EN BIT(1) 59 #define MII_DP83869_MICR_JABBER_INT_EN BIT(0) 60 61 #define MII_DP83869_BMCR_DEFAULT (BMCR_ANENABLE | \ 62 BMCR_FULLDPLX | \ 63 BMCR_SPEED1000) 64 65 #define MII_DP83869_FIBER_ADVERTISE (ADVERTISED_FIBRE | \ 66 ADVERTISED_Pause | \ 67 ADVERTISED_Asym_Pause) 68 69 /* This is the same bit mask as the BMCR so re-use the BMCR default */ 70 #define DP83869_FX_CTRL_DEFAULT MII_DP83869_BMCR_DEFAULT 71 72 /* CFG1 bits */ 73 #define DP83869_CFG1_DEFAULT (ADVERTISE_1000HALF | \ 74 ADVERTISE_1000FULL | \ 75 CTL1000_AS_MASTER) 76 77 /* RGMIICTL bits */ 78 #define DP83869_RGMII_TX_CLK_DELAY_EN BIT(1) 79 #define DP83869_RGMII_RX_CLK_DELAY_EN BIT(0) 80 81 /* RGMIIDCTL */ 82 #define DP83869_RGMII_CLK_DELAY_SHIFT 4 83 #define DP83869_CLK_DELAY_DEF 7 84 85 /* STRAP_STS1 bits */ 86 #define DP83869_STRAP_OP_MODE_MASK GENMASK(2, 0) 87 #define DP83869_STRAP_STS1_RESERVED BIT(11) 88 #define DP83869_STRAP_MIRROR_ENABLED BIT(12) 89 90 /* PHYCTRL bits */ 91 #define DP83869_RX_FIFO_SHIFT 12 92 #define DP83869_TX_FIFO_SHIFT 14 93 94 /* PHY_CTRL lower bytes 0x48 are declared as reserved */ 95 #define DP83869_PHY_CTRL_DEFAULT 0x48 96 #define DP83869_PHYCR_FIFO_DEPTH_MASK GENMASK(15, 12) 97 #define DP83869_PHYCR_RESERVED_MASK BIT(11) 98 99 /* IO_MUX_CFG bits */ 100 #define DP83869_IO_MUX_CFG_IO_IMPEDANCE_CTRL 0x1f 101 102 #define DP83869_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0 103 #define DP83869_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f 104 #define DP83869_IO_MUX_CFG_CLK_O_SEL_MASK (0x1f << 8) 105 #define DP83869_IO_MUX_CFG_CLK_O_SEL_SHIFT 8 106 107 /* CFG3 bits */ 108 #define DP83869_CFG3_PORT_MIRROR_EN BIT(0) 109 110 /* CFG4 bits */ 111 #define DP83869_INT_OE BIT(7) 112 113 /* OP MODE */ 114 #define DP83869_OP_MODE_MII BIT(5) 115 #define DP83869_SGMII_RGMII_BRIDGE BIT(6) 116 117 /* RXFCFG bits*/ 118 #define DP83869_WOL_MAGIC_EN BIT(0) 119 #define DP83869_WOL_PATTERN_EN BIT(1) 120 #define DP83869_WOL_BCAST_EN BIT(2) 121 #define DP83869_WOL_UCAST_EN BIT(4) 122 #define DP83869_WOL_SEC_EN BIT(5) 123 #define DP83869_WOL_ENH_MAC BIT(7) 124 125 /* CFG2 bits */ 126 #define DP83869_DOWNSHIFT_EN (BIT(8) | BIT(9)) 127 #define DP83869_DOWNSHIFT_ATTEMPT_MASK (BIT(10) | BIT(11)) 128 #define DP83869_DOWNSHIFT_1_COUNT_VAL 0 129 #define DP83869_DOWNSHIFT_2_COUNT_VAL 1 130 #define DP83869_DOWNSHIFT_4_COUNT_VAL 2 131 #define DP83869_DOWNSHIFT_8_COUNT_VAL 3 132 #define DP83869_DOWNSHIFT_1_COUNT 1 133 #define DP83869_DOWNSHIFT_2_COUNT 2 134 #define DP83869_DOWNSHIFT_4_COUNT 4 135 #define DP83869_DOWNSHIFT_8_COUNT 8 136 137 enum { 138 DP83869_PORT_MIRRORING_KEEP, 139 DP83869_PORT_MIRRORING_EN, 140 DP83869_PORT_MIRRORING_DIS, 141 }; 142 143 struct dp83869_private { 144 int tx_fifo_depth; 145 int rx_fifo_depth; 146 s32 rx_int_delay; 147 s32 tx_int_delay; 148 int io_impedance; 149 int port_mirroring; 150 bool rxctrl_strap_quirk; 151 int clk_output_sel; 152 int mode; 153 }; 154 155 static int dp83869_read_status(struct phy_device *phydev) 156 { 157 struct dp83869_private *dp83869 = phydev->priv; 158 int ret; 159 160 ret = genphy_read_status(phydev); 161 if (ret) 162 return ret; 163 164 if (linkmode_test_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, phydev->supported)) { 165 if (phydev->link) { 166 if (dp83869->mode == DP83869_RGMII_100_BASE) 167 phydev->speed = SPEED_100; 168 } else { 169 phydev->speed = SPEED_UNKNOWN; 170 phydev->duplex = DUPLEX_UNKNOWN; 171 } 172 } 173 174 return 0; 175 } 176 177 static int dp83869_ack_interrupt(struct phy_device *phydev) 178 { 179 int err = phy_read(phydev, MII_DP83869_ISR); 180 181 if (err < 0) 182 return err; 183 184 return 0; 185 } 186 187 static int dp83869_config_intr(struct phy_device *phydev) 188 { 189 int micr_status = 0; 190 191 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 192 micr_status = phy_read(phydev, MII_DP83869_MICR); 193 if (micr_status < 0) 194 return micr_status; 195 196 micr_status |= 197 (MII_DP83869_MICR_AN_ERR_INT_EN | 198 MII_DP83869_MICR_SPEED_CHNG_INT_EN | 199 MII_DP83869_MICR_AUTONEG_COMP_INT_EN | 200 MII_DP83869_MICR_LINK_STS_CHNG_INT_EN | 201 MII_DP83869_MICR_DUP_MODE_CHNG_INT_EN | 202 MII_DP83869_MICR_SLEEP_MODE_CHNG_INT_EN); 203 204 return phy_write(phydev, MII_DP83869_MICR, micr_status); 205 } 206 207 return phy_write(phydev, MII_DP83869_MICR, micr_status); 208 } 209 210 static int dp83869_set_wol(struct phy_device *phydev, 211 struct ethtool_wolinfo *wol) 212 { 213 struct net_device *ndev = phydev->attached_dev; 214 int val_rxcfg, val_micr; 215 u8 *mac; 216 int ret; 217 218 val_rxcfg = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_RXFCFG); 219 if (val_rxcfg < 0) 220 return val_rxcfg; 221 222 val_micr = phy_read(phydev, MII_DP83869_MICR); 223 if (val_micr < 0) 224 return val_micr; 225 226 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_UCAST | 227 WAKE_BCAST)) { 228 val_rxcfg |= DP83869_WOL_ENH_MAC; 229 val_micr |= MII_DP83869_MICR_WOL_INT_EN; 230 231 if (wol->wolopts & WAKE_MAGIC || 232 wol->wolopts & WAKE_MAGICSECURE) { 233 mac = (u8 *)ndev->dev_addr; 234 235 if (!is_valid_ether_addr(mac)) 236 return -EINVAL; 237 238 ret = phy_write_mmd(phydev, DP83869_DEVADDR, 239 DP83869_RXFPMD1, 240 mac[1] << 8 | mac[0]); 241 if (ret) 242 return ret; 243 244 ret = phy_write_mmd(phydev, DP83869_DEVADDR, 245 DP83869_RXFPMD2, 246 mac[3] << 8 | mac[2]); 247 if (ret) 248 return ret; 249 250 ret = phy_write_mmd(phydev, DP83869_DEVADDR, 251 DP83869_RXFPMD3, 252 mac[5] << 8 | mac[4]); 253 if (ret) 254 return ret; 255 256 val_rxcfg |= DP83869_WOL_MAGIC_EN; 257 } else { 258 val_rxcfg &= ~DP83869_WOL_MAGIC_EN; 259 } 260 261 if (wol->wolopts & WAKE_MAGICSECURE) { 262 ret = phy_write_mmd(phydev, DP83869_DEVADDR, 263 DP83869_RXFSOP1, 264 (wol->sopass[1] << 8) | wol->sopass[0]); 265 if (ret) 266 return ret; 267 268 ret = phy_write_mmd(phydev, DP83869_DEVADDR, 269 DP83869_RXFSOP2, 270 (wol->sopass[3] << 8) | wol->sopass[2]); 271 if (ret) 272 return ret; 273 ret = phy_write_mmd(phydev, DP83869_DEVADDR, 274 DP83869_RXFSOP3, 275 (wol->sopass[5] << 8) | wol->sopass[4]); 276 if (ret) 277 return ret; 278 279 val_rxcfg |= DP83869_WOL_SEC_EN; 280 } else { 281 val_rxcfg &= ~DP83869_WOL_SEC_EN; 282 } 283 284 if (wol->wolopts & WAKE_UCAST) 285 val_rxcfg |= DP83869_WOL_UCAST_EN; 286 else 287 val_rxcfg &= ~DP83869_WOL_UCAST_EN; 288 289 if (wol->wolopts & WAKE_BCAST) 290 val_rxcfg |= DP83869_WOL_BCAST_EN; 291 else 292 val_rxcfg &= ~DP83869_WOL_BCAST_EN; 293 } else { 294 val_rxcfg &= ~DP83869_WOL_ENH_MAC; 295 val_micr &= ~MII_DP83869_MICR_WOL_INT_EN; 296 } 297 298 ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RXFCFG, val_rxcfg); 299 if (ret) 300 return ret; 301 302 return phy_write(phydev, MII_DP83869_MICR, val_micr); 303 } 304 305 static void dp83869_get_wol(struct phy_device *phydev, 306 struct ethtool_wolinfo *wol) 307 { 308 int value, sopass_val; 309 310 wol->supported = (WAKE_UCAST | WAKE_BCAST | WAKE_MAGIC | 311 WAKE_MAGICSECURE); 312 wol->wolopts = 0; 313 314 value = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_RXFCFG); 315 if (value < 0) { 316 phydev_err(phydev, "Failed to read RX CFG\n"); 317 return; 318 } 319 320 if (value & DP83869_WOL_UCAST_EN) 321 wol->wolopts |= WAKE_UCAST; 322 323 if (value & DP83869_WOL_BCAST_EN) 324 wol->wolopts |= WAKE_BCAST; 325 326 if (value & DP83869_WOL_MAGIC_EN) 327 wol->wolopts |= WAKE_MAGIC; 328 329 if (value & DP83869_WOL_SEC_EN) { 330 sopass_val = phy_read_mmd(phydev, DP83869_DEVADDR, 331 DP83869_RXFSOP1); 332 if (sopass_val < 0) { 333 phydev_err(phydev, "Failed to read RX SOP 1\n"); 334 return; 335 } 336 337 wol->sopass[0] = (sopass_val & 0xff); 338 wol->sopass[1] = (sopass_val >> 8); 339 340 sopass_val = phy_read_mmd(phydev, DP83869_DEVADDR, 341 DP83869_RXFSOP2); 342 if (sopass_val < 0) { 343 phydev_err(phydev, "Failed to read RX SOP 2\n"); 344 return; 345 } 346 347 wol->sopass[2] = (sopass_val & 0xff); 348 wol->sopass[3] = (sopass_val >> 8); 349 350 sopass_val = phy_read_mmd(phydev, DP83869_DEVADDR, 351 DP83869_RXFSOP3); 352 if (sopass_val < 0) { 353 phydev_err(phydev, "Failed to read RX SOP 3\n"); 354 return; 355 } 356 357 wol->sopass[4] = (sopass_val & 0xff); 358 wol->sopass[5] = (sopass_val >> 8); 359 360 wol->wolopts |= WAKE_MAGICSECURE; 361 } 362 363 if (!(value & DP83869_WOL_ENH_MAC)) 364 wol->wolopts = 0; 365 } 366 367 static int dp83869_get_downshift(struct phy_device *phydev, u8 *data) 368 { 369 int val, cnt, enable, count; 370 371 val = phy_read(phydev, DP83869_CFG2); 372 if (val < 0) 373 return val; 374 375 enable = FIELD_GET(DP83869_DOWNSHIFT_EN, val); 376 cnt = FIELD_GET(DP83869_DOWNSHIFT_ATTEMPT_MASK, val); 377 378 switch (cnt) { 379 case DP83869_DOWNSHIFT_1_COUNT_VAL: 380 count = DP83869_DOWNSHIFT_1_COUNT; 381 break; 382 case DP83869_DOWNSHIFT_2_COUNT_VAL: 383 count = DP83869_DOWNSHIFT_2_COUNT; 384 break; 385 case DP83869_DOWNSHIFT_4_COUNT_VAL: 386 count = DP83869_DOWNSHIFT_4_COUNT; 387 break; 388 case DP83869_DOWNSHIFT_8_COUNT_VAL: 389 count = DP83869_DOWNSHIFT_8_COUNT; 390 break; 391 default: 392 return -EINVAL; 393 } 394 395 *data = enable ? count : DOWNSHIFT_DEV_DISABLE; 396 397 return 0; 398 } 399 400 static int dp83869_set_downshift(struct phy_device *phydev, u8 cnt) 401 { 402 int val, count; 403 404 if (cnt > DP83869_DOWNSHIFT_8_COUNT) 405 return -EINVAL; 406 407 if (!cnt) 408 return phy_clear_bits(phydev, DP83869_CFG2, 409 DP83869_DOWNSHIFT_EN); 410 411 switch (cnt) { 412 case DP83869_DOWNSHIFT_1_COUNT: 413 count = DP83869_DOWNSHIFT_1_COUNT_VAL; 414 break; 415 case DP83869_DOWNSHIFT_2_COUNT: 416 count = DP83869_DOWNSHIFT_2_COUNT_VAL; 417 break; 418 case DP83869_DOWNSHIFT_4_COUNT: 419 count = DP83869_DOWNSHIFT_4_COUNT_VAL; 420 break; 421 case DP83869_DOWNSHIFT_8_COUNT: 422 count = DP83869_DOWNSHIFT_8_COUNT_VAL; 423 break; 424 default: 425 phydev_err(phydev, 426 "Downshift count must be 1, 2, 4 or 8\n"); 427 return -EINVAL; 428 } 429 430 val = DP83869_DOWNSHIFT_EN; 431 val |= FIELD_PREP(DP83869_DOWNSHIFT_ATTEMPT_MASK, count); 432 433 return phy_modify(phydev, DP83869_CFG2, 434 DP83869_DOWNSHIFT_EN | DP83869_DOWNSHIFT_ATTEMPT_MASK, 435 val); 436 } 437 438 static int dp83869_get_tunable(struct phy_device *phydev, 439 struct ethtool_tunable *tuna, void *data) 440 { 441 switch (tuna->id) { 442 case ETHTOOL_PHY_DOWNSHIFT: 443 return dp83869_get_downshift(phydev, data); 444 default: 445 return -EOPNOTSUPP; 446 } 447 } 448 449 static int dp83869_set_tunable(struct phy_device *phydev, 450 struct ethtool_tunable *tuna, const void *data) 451 { 452 switch (tuna->id) { 453 case ETHTOOL_PHY_DOWNSHIFT: 454 return dp83869_set_downshift(phydev, *(const u8 *)data); 455 default: 456 return -EOPNOTSUPP; 457 } 458 } 459 460 static int dp83869_config_port_mirroring(struct phy_device *phydev) 461 { 462 struct dp83869_private *dp83869 = phydev->priv; 463 464 if (dp83869->port_mirroring == DP83869_PORT_MIRRORING_EN) 465 return phy_set_bits_mmd(phydev, DP83869_DEVADDR, 466 DP83869_GEN_CFG3, 467 DP83869_CFG3_PORT_MIRROR_EN); 468 else 469 return phy_clear_bits_mmd(phydev, DP83869_DEVADDR, 470 DP83869_GEN_CFG3, 471 DP83869_CFG3_PORT_MIRROR_EN); 472 } 473 474 static int dp83869_set_strapped_mode(struct phy_device *phydev) 475 { 476 struct dp83869_private *dp83869 = phydev->priv; 477 int val; 478 479 val = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_STRAP_STS1); 480 if (val < 0) 481 return val; 482 483 dp83869->mode = val & DP83869_STRAP_OP_MODE_MASK; 484 485 return 0; 486 } 487 488 #if IS_ENABLED(CONFIG_OF_MDIO) 489 static const int dp83869_internal_delay[] = {250, 500, 750, 1000, 1250, 1500, 490 1750, 2000, 2250, 2500, 2750, 3000, 491 3250, 3500, 3750, 4000}; 492 493 static int dp83869_of_init(struct phy_device *phydev) 494 { 495 struct dp83869_private *dp83869 = phydev->priv; 496 struct device *dev = &phydev->mdio.dev; 497 struct device_node *of_node = dev->of_node; 498 int delay_size = ARRAY_SIZE(dp83869_internal_delay); 499 int ret; 500 501 if (!of_node) 502 return -ENODEV; 503 504 dp83869->io_impedance = -EINVAL; 505 506 /* Optional configuration */ 507 ret = of_property_read_u32(of_node, "ti,clk-output-sel", 508 &dp83869->clk_output_sel); 509 if (ret || dp83869->clk_output_sel > DP83869_CLK_O_SEL_REF_CLK) 510 dp83869->clk_output_sel = DP83869_CLK_O_SEL_REF_CLK; 511 512 ret = of_property_read_u32(of_node, "ti,op-mode", &dp83869->mode); 513 if (ret == 0) { 514 if (dp83869->mode < DP83869_RGMII_COPPER_ETHERNET || 515 dp83869->mode > DP83869_SGMII_COPPER_ETHERNET) 516 return -EINVAL; 517 } else { 518 ret = dp83869_set_strapped_mode(phydev); 519 if (ret) 520 return ret; 521 } 522 523 if (of_property_read_bool(of_node, "ti,max-output-impedance")) 524 dp83869->io_impedance = DP83869_IO_MUX_CFG_IO_IMPEDANCE_MAX; 525 else if (of_property_read_bool(of_node, "ti,min-output-impedance")) 526 dp83869->io_impedance = DP83869_IO_MUX_CFG_IO_IMPEDANCE_MIN; 527 528 if (of_property_read_bool(of_node, "enet-phy-lane-swap")) { 529 dp83869->port_mirroring = DP83869_PORT_MIRRORING_EN; 530 } else { 531 /* If the lane swap is not in the DT then check the straps */ 532 ret = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_STRAP_STS1); 533 if (ret < 0) 534 return ret; 535 536 if (ret & DP83869_STRAP_MIRROR_ENABLED) 537 dp83869->port_mirroring = DP83869_PORT_MIRRORING_EN; 538 else 539 dp83869->port_mirroring = DP83869_PORT_MIRRORING_DIS; 540 541 ret = 0; 542 } 543 544 if (of_property_read_u32(of_node, "rx-fifo-depth", 545 &dp83869->rx_fifo_depth)) 546 dp83869->rx_fifo_depth = DP83869_PHYCR_FIFO_DEPTH_4_B_NIB; 547 548 if (of_property_read_u32(of_node, "tx-fifo-depth", 549 &dp83869->tx_fifo_depth)) 550 dp83869->tx_fifo_depth = DP83869_PHYCR_FIFO_DEPTH_4_B_NIB; 551 552 dp83869->rx_int_delay = phy_get_internal_delay(phydev, dev, 553 &dp83869_internal_delay[0], 554 delay_size, true); 555 if (dp83869->rx_int_delay < 0) 556 dp83869->rx_int_delay = 557 dp83869_internal_delay[DP83869_CLK_DELAY_DEF]; 558 559 dp83869->tx_int_delay = phy_get_internal_delay(phydev, dev, 560 &dp83869_internal_delay[0], 561 delay_size, false); 562 if (dp83869->tx_int_delay < 0) 563 dp83869->tx_int_delay = 564 dp83869_internal_delay[DP83869_CLK_DELAY_DEF]; 565 566 return ret; 567 } 568 #else 569 static int dp83869_of_init(struct phy_device *phydev) 570 { 571 return dp83869_set_strapped_mode(phydev); 572 } 573 #endif /* CONFIG_OF_MDIO */ 574 575 static int dp83869_configure_rgmii(struct phy_device *phydev, 576 struct dp83869_private *dp83869) 577 { 578 int ret = 0, val; 579 580 if (phy_interface_is_rgmii(phydev)) { 581 val = phy_read(phydev, MII_DP83869_PHYCTRL); 582 if (val < 0) 583 return val; 584 585 val &= ~DP83869_PHYCR_FIFO_DEPTH_MASK; 586 val |= (dp83869->tx_fifo_depth << DP83869_TX_FIFO_SHIFT); 587 val |= (dp83869->rx_fifo_depth << DP83869_RX_FIFO_SHIFT); 588 589 ret = phy_write(phydev, MII_DP83869_PHYCTRL, val); 590 if (ret) 591 return ret; 592 } 593 594 if (dp83869->io_impedance >= 0) 595 ret = phy_modify_mmd(phydev, DP83869_DEVADDR, 596 DP83869_IO_MUX_CFG, 597 DP83869_IO_MUX_CFG_IO_IMPEDANCE_CTRL, 598 dp83869->io_impedance & 599 DP83869_IO_MUX_CFG_IO_IMPEDANCE_CTRL); 600 601 return ret; 602 } 603 604 static int dp83869_configure_fiber(struct phy_device *phydev, 605 struct dp83869_private *dp83869) 606 { 607 int bmcr; 608 int ret; 609 610 /* Only allow advertising what this PHY supports */ 611 linkmode_and(phydev->advertising, phydev->advertising, 612 phydev->supported); 613 614 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, phydev->supported); 615 linkmode_set_bit(ADVERTISED_FIBRE, phydev->advertising); 616 617 if (dp83869->mode == DP83869_RGMII_1000_BASE) { 618 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 619 phydev->supported); 620 } else { 621 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Full_BIT, 622 phydev->supported); 623 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Half_BIT, 624 phydev->supported); 625 626 /* Auto neg is not supported in 100base FX mode */ 627 bmcr = phy_read(phydev, MII_BMCR); 628 if (bmcr < 0) 629 return bmcr; 630 631 phydev->autoneg = AUTONEG_DISABLE; 632 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported); 633 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->advertising); 634 635 if (bmcr & BMCR_ANENABLE) { 636 ret = phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0); 637 if (ret < 0) 638 return ret; 639 } 640 } 641 642 /* Update advertising from supported */ 643 linkmode_or(phydev->advertising, phydev->advertising, 644 phydev->supported); 645 646 return 0; 647 } 648 649 static int dp83869_configure_mode(struct phy_device *phydev, 650 struct dp83869_private *dp83869) 651 { 652 int phy_ctrl_val; 653 int ret; 654 655 if (dp83869->mode < DP83869_RGMII_COPPER_ETHERNET || 656 dp83869->mode > DP83869_SGMII_COPPER_ETHERNET) 657 return -EINVAL; 658 659 /* Below init sequence for each operational mode is defined in 660 * section 9.4.8 of the datasheet. 661 */ 662 ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_OP_MODE, 663 dp83869->mode); 664 if (ret) 665 return ret; 666 667 ret = phy_write(phydev, MII_BMCR, MII_DP83869_BMCR_DEFAULT); 668 if (ret) 669 return ret; 670 671 phy_ctrl_val = (dp83869->rx_fifo_depth << DP83869_RX_FIFO_SHIFT | 672 dp83869->tx_fifo_depth << DP83869_TX_FIFO_SHIFT | 673 DP83869_PHY_CTRL_DEFAULT); 674 675 switch (dp83869->mode) { 676 case DP83869_RGMII_COPPER_ETHERNET: 677 ret = phy_write(phydev, MII_DP83869_PHYCTRL, 678 phy_ctrl_val); 679 if (ret) 680 return ret; 681 682 ret = phy_write(phydev, MII_CTRL1000, DP83869_CFG1_DEFAULT); 683 if (ret) 684 return ret; 685 686 ret = dp83869_configure_rgmii(phydev, dp83869); 687 if (ret) 688 return ret; 689 break; 690 case DP83869_RGMII_SGMII_BRIDGE: 691 ret = phy_modify_mmd(phydev, DP83869_DEVADDR, DP83869_OP_MODE, 692 DP83869_SGMII_RGMII_BRIDGE, 693 DP83869_SGMII_RGMII_BRIDGE); 694 if (ret) 695 return ret; 696 697 ret = phy_write_mmd(phydev, DP83869_DEVADDR, 698 DP83869_FX_CTRL, DP83869_FX_CTRL_DEFAULT); 699 if (ret) 700 return ret; 701 702 break; 703 case DP83869_1000M_MEDIA_CONVERT: 704 ret = phy_write(phydev, MII_DP83869_PHYCTRL, 705 phy_ctrl_val); 706 if (ret) 707 return ret; 708 709 ret = phy_write_mmd(phydev, DP83869_DEVADDR, 710 DP83869_FX_CTRL, DP83869_FX_CTRL_DEFAULT); 711 if (ret) 712 return ret; 713 break; 714 case DP83869_100M_MEDIA_CONVERT: 715 ret = phy_write(phydev, MII_DP83869_PHYCTRL, 716 phy_ctrl_val); 717 if (ret) 718 return ret; 719 break; 720 case DP83869_SGMII_COPPER_ETHERNET: 721 ret = phy_write(phydev, MII_DP83869_PHYCTRL, 722 phy_ctrl_val); 723 if (ret) 724 return ret; 725 726 ret = phy_write(phydev, MII_CTRL1000, DP83869_CFG1_DEFAULT); 727 if (ret) 728 return ret; 729 730 ret = phy_write_mmd(phydev, DP83869_DEVADDR, 731 DP83869_FX_CTRL, DP83869_FX_CTRL_DEFAULT); 732 if (ret) 733 return ret; 734 735 break; 736 case DP83869_RGMII_1000_BASE: 737 case DP83869_RGMII_100_BASE: 738 ret = dp83869_configure_fiber(phydev, dp83869); 739 break; 740 default: 741 return -EINVAL; 742 } 743 744 return ret; 745 } 746 747 static int dp83869_config_init(struct phy_device *phydev) 748 { 749 struct dp83869_private *dp83869 = phydev->priv; 750 int ret, val; 751 752 /* Force speed optimization for the PHY even if it strapped */ 753 ret = phy_modify(phydev, DP83869_CFG2, DP83869_DOWNSHIFT_EN, 754 DP83869_DOWNSHIFT_EN); 755 if (ret) 756 return ret; 757 758 ret = dp83869_configure_mode(phydev, dp83869); 759 if (ret) 760 return ret; 761 762 /* Enable Interrupt output INT_OE in CFG4 register */ 763 if (phy_interrupt_is_valid(phydev)) { 764 val = phy_read(phydev, DP83869_CFG4); 765 val |= DP83869_INT_OE; 766 phy_write(phydev, DP83869_CFG4, val); 767 } 768 769 if (dp83869->port_mirroring != DP83869_PORT_MIRRORING_KEEP) 770 dp83869_config_port_mirroring(phydev); 771 772 /* Clock output selection if muxing property is set */ 773 if (dp83869->clk_output_sel != DP83869_CLK_O_SEL_REF_CLK) 774 ret = phy_modify_mmd(phydev, 775 DP83869_DEVADDR, DP83869_IO_MUX_CFG, 776 DP83869_IO_MUX_CFG_CLK_O_SEL_MASK, 777 dp83869->clk_output_sel << 778 DP83869_IO_MUX_CFG_CLK_O_SEL_SHIFT); 779 780 if (phy_interface_is_rgmii(phydev)) { 781 ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIIDCTL, 782 dp83869->rx_int_delay | 783 dp83869->tx_int_delay << DP83869_RGMII_CLK_DELAY_SHIFT); 784 if (ret) 785 return ret; 786 787 val = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIICTL); 788 val |= (DP83869_RGMII_TX_CLK_DELAY_EN | 789 DP83869_RGMII_RX_CLK_DELAY_EN); 790 791 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) 792 val &= ~(DP83869_RGMII_TX_CLK_DELAY_EN | 793 DP83869_RGMII_RX_CLK_DELAY_EN); 794 795 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) 796 val &= ~DP83869_RGMII_TX_CLK_DELAY_EN; 797 798 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) 799 val &= ~DP83869_RGMII_RX_CLK_DELAY_EN; 800 801 ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIICTL, 802 val); 803 } 804 805 return ret; 806 } 807 808 static int dp83869_probe(struct phy_device *phydev) 809 { 810 struct dp83869_private *dp83869; 811 int ret; 812 813 dp83869 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83869), 814 GFP_KERNEL); 815 if (!dp83869) 816 return -ENOMEM; 817 818 phydev->priv = dp83869; 819 820 ret = dp83869_of_init(phydev); 821 if (ret) 822 return ret; 823 824 return dp83869_config_init(phydev); 825 } 826 827 static int dp83869_phy_reset(struct phy_device *phydev) 828 { 829 int ret; 830 831 ret = phy_write(phydev, DP83869_CTRL, DP83869_SW_RESET); 832 if (ret < 0) 833 return ret; 834 835 usleep_range(10, 20); 836 837 /* Global sw reset sets all registers to default. 838 * Need to set the registers in the PHY to the right config. 839 */ 840 return dp83869_config_init(phydev); 841 } 842 843 static struct phy_driver dp83869_driver[] = { 844 { 845 PHY_ID_MATCH_MODEL(DP83869_PHY_ID), 846 .name = "TI DP83869", 847 848 .probe = dp83869_probe, 849 .config_init = dp83869_config_init, 850 .soft_reset = dp83869_phy_reset, 851 852 /* IRQ related */ 853 .ack_interrupt = dp83869_ack_interrupt, 854 .config_intr = dp83869_config_intr, 855 .read_status = dp83869_read_status, 856 857 .get_tunable = dp83869_get_tunable, 858 .set_tunable = dp83869_set_tunable, 859 860 .get_wol = dp83869_get_wol, 861 .set_wol = dp83869_set_wol, 862 863 .suspend = genphy_suspend, 864 .resume = genphy_resume, 865 }, 866 }; 867 module_phy_driver(dp83869_driver); 868 869 static struct mdio_device_id __maybe_unused dp83869_tbl[] = { 870 { PHY_ID_MATCH_MODEL(DP83869_PHY_ID) }, 871 { } 872 }; 873 MODULE_DEVICE_TABLE(mdio, dp83869_tbl); 874 875 MODULE_DESCRIPTION("Texas Instruments DP83869 PHY driver"); 876 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com"); 877 MODULE_LICENSE("GPL v2"); 878