1 // SPDX-License-Identifier: GPL-2.0 2 /* Driver for the Texas Instruments DP83869 PHY 3 * Copyright (C) 2019 Texas Instruments Inc. 4 */ 5 6 #include <linux/ethtool.h> 7 #include <linux/kernel.h> 8 #include <linux/mii.h> 9 #include <linux/module.h> 10 #include <linux/of.h> 11 #include <linux/phy.h> 12 #include <linux/delay.h> 13 14 #include <dt-bindings/net/ti-dp83869.h> 15 16 #define DP83869_PHY_ID 0x2000a0f1 17 #define DP83869_DEVADDR 0x1f 18 19 #define MII_DP83869_PHYCTRL 0x10 20 #define MII_DP83869_MICR 0x12 21 #define MII_DP83869_ISR 0x13 22 #define DP83869_CTRL 0x1f 23 #define DP83869_CFG4 0x1e 24 25 /* Extended Registers */ 26 #define DP83869_GEN_CFG3 0x0031 27 #define DP83869_RGMIICTL 0x0032 28 #define DP83869_STRAP_STS1 0x006e 29 #define DP83869_RGMIIDCTL 0x0086 30 #define DP83869_IO_MUX_CFG 0x0170 31 #define DP83869_OP_MODE 0x01df 32 #define DP83869_FX_CTRL 0x0c00 33 34 #define DP83869_SW_RESET BIT(15) 35 #define DP83869_SW_RESTART BIT(14) 36 37 /* MICR Interrupt bits */ 38 #define MII_DP83869_MICR_AN_ERR_INT_EN BIT(15) 39 #define MII_DP83869_MICR_SPEED_CHNG_INT_EN BIT(14) 40 #define MII_DP83869_MICR_DUP_MODE_CHNG_INT_EN BIT(13) 41 #define MII_DP83869_MICR_PAGE_RXD_INT_EN BIT(12) 42 #define MII_DP83869_MICR_AUTONEG_COMP_INT_EN BIT(11) 43 #define MII_DP83869_MICR_LINK_STS_CHNG_INT_EN BIT(10) 44 #define MII_DP83869_MICR_FALSE_CARRIER_INT_EN BIT(8) 45 #define MII_DP83869_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4) 46 #define MII_DP83869_MICR_WOL_INT_EN BIT(3) 47 #define MII_DP83869_MICR_XGMII_ERR_INT_EN BIT(2) 48 #define MII_DP83869_MICR_POL_CHNG_INT_EN BIT(1) 49 #define MII_DP83869_MICR_JABBER_INT_EN BIT(0) 50 51 #define MII_DP83869_BMCR_DEFAULT (BMCR_ANENABLE | \ 52 BMCR_FULLDPLX | \ 53 BMCR_SPEED1000) 54 55 /* This is the same bit mask as the BMCR so re-use the BMCR default */ 56 #define DP83869_FX_CTRL_DEFAULT MII_DP83869_BMCR_DEFAULT 57 58 /* CFG1 bits */ 59 #define DP83869_CFG1_DEFAULT (ADVERTISE_1000HALF | \ 60 ADVERTISE_1000FULL | \ 61 CTL1000_AS_MASTER) 62 63 /* RGMIICTL bits */ 64 #define DP83869_RGMII_TX_CLK_DELAY_EN BIT(1) 65 #define DP83869_RGMII_RX_CLK_DELAY_EN BIT(0) 66 67 /* STRAP_STS1 bits */ 68 #define DP83869_STRAP_OP_MODE_MASK GENMASK(2, 0) 69 #define DP83869_STRAP_STS1_RESERVED BIT(11) 70 #define DP83869_STRAP_MIRROR_ENABLED BIT(12) 71 72 /* PHYCTRL bits */ 73 #define DP83869_RX_FIFO_SHIFT 12 74 #define DP83869_TX_FIFO_SHIFT 14 75 76 /* PHY_CTRL lower bytes 0x48 are declared as reserved */ 77 #define DP83869_PHY_CTRL_DEFAULT 0x48 78 #define DP83869_PHYCR_FIFO_DEPTH_MASK GENMASK(15, 12) 79 #define DP83869_PHYCR_RESERVED_MASK BIT(11) 80 81 /* RGMIIDCTL bits */ 82 #define DP83869_RGMII_TX_CLK_DELAY_SHIFT 4 83 84 /* IO_MUX_CFG bits */ 85 #define DP83869_IO_MUX_CFG_IO_IMPEDANCE_CTRL 0x1f 86 87 #define DP83869_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0 88 #define DP83869_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f 89 #define DP83869_IO_MUX_CFG_CLK_O_SEL_MASK (0x1f << 8) 90 #define DP83869_IO_MUX_CFG_CLK_O_SEL_SHIFT 8 91 92 /* CFG3 bits */ 93 #define DP83869_CFG3_PORT_MIRROR_EN BIT(0) 94 95 /* CFG4 bits */ 96 #define DP83869_INT_OE BIT(7) 97 98 /* OP MODE */ 99 #define DP83869_OP_MODE_MII BIT(5) 100 #define DP83869_SGMII_RGMII_BRIDGE BIT(6) 101 102 enum { 103 DP83869_PORT_MIRRORING_KEEP, 104 DP83869_PORT_MIRRORING_EN, 105 DP83869_PORT_MIRRORING_DIS, 106 }; 107 108 struct dp83869_private { 109 int tx_fifo_depth; 110 int rx_fifo_depth; 111 int io_impedance; 112 int port_mirroring; 113 bool rxctrl_strap_quirk; 114 int clk_output_sel; 115 int mode; 116 }; 117 118 static int dp83869_ack_interrupt(struct phy_device *phydev) 119 { 120 int err = phy_read(phydev, MII_DP83869_ISR); 121 122 if (err < 0) 123 return err; 124 125 return 0; 126 } 127 128 static int dp83869_config_intr(struct phy_device *phydev) 129 { 130 int micr_status = 0; 131 132 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 133 micr_status = phy_read(phydev, MII_DP83869_MICR); 134 if (micr_status < 0) 135 return micr_status; 136 137 micr_status |= 138 (MII_DP83869_MICR_AN_ERR_INT_EN | 139 MII_DP83869_MICR_SPEED_CHNG_INT_EN | 140 MII_DP83869_MICR_AUTONEG_COMP_INT_EN | 141 MII_DP83869_MICR_LINK_STS_CHNG_INT_EN | 142 MII_DP83869_MICR_DUP_MODE_CHNG_INT_EN | 143 MII_DP83869_MICR_SLEEP_MODE_CHNG_INT_EN); 144 145 return phy_write(phydev, MII_DP83869_MICR, micr_status); 146 } 147 148 return phy_write(phydev, MII_DP83869_MICR, micr_status); 149 } 150 151 static int dp83869_config_port_mirroring(struct phy_device *phydev) 152 { 153 struct dp83869_private *dp83869 = phydev->priv; 154 155 if (dp83869->port_mirroring == DP83869_PORT_MIRRORING_EN) 156 return phy_set_bits_mmd(phydev, DP83869_DEVADDR, 157 DP83869_GEN_CFG3, 158 DP83869_CFG3_PORT_MIRROR_EN); 159 else 160 return phy_clear_bits_mmd(phydev, DP83869_DEVADDR, 161 DP83869_GEN_CFG3, 162 DP83869_CFG3_PORT_MIRROR_EN); 163 } 164 165 static int dp83869_set_strapped_mode(struct phy_device *phydev) 166 { 167 struct dp83869_private *dp83869 = phydev->priv; 168 int val; 169 170 val = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_STRAP_STS1); 171 if (val < 0) 172 return val; 173 174 dp83869->mode = val & DP83869_STRAP_OP_MODE_MASK; 175 176 return 0; 177 } 178 179 #ifdef CONFIG_OF_MDIO 180 static int dp83869_of_init(struct phy_device *phydev) 181 { 182 struct dp83869_private *dp83869 = phydev->priv; 183 struct device *dev = &phydev->mdio.dev; 184 struct device_node *of_node = dev->of_node; 185 int ret; 186 187 if (!of_node) 188 return -ENODEV; 189 190 dp83869->io_impedance = -EINVAL; 191 192 /* Optional configuration */ 193 ret = of_property_read_u32(of_node, "ti,clk-output-sel", 194 &dp83869->clk_output_sel); 195 if (ret || dp83869->clk_output_sel > DP83869_CLK_O_SEL_REF_CLK) 196 dp83869->clk_output_sel = DP83869_CLK_O_SEL_REF_CLK; 197 198 ret = of_property_read_u32(of_node, "ti,op-mode", &dp83869->mode); 199 if (ret == 0) { 200 if (dp83869->mode < DP83869_RGMII_COPPER_ETHERNET || 201 dp83869->mode > DP83869_SGMII_COPPER_ETHERNET) 202 return -EINVAL; 203 } else { 204 ret = dp83869_set_strapped_mode(phydev); 205 if (ret) 206 return ret; 207 } 208 209 if (of_property_read_bool(of_node, "ti,max-output-impedance")) 210 dp83869->io_impedance = DP83869_IO_MUX_CFG_IO_IMPEDANCE_MAX; 211 else if (of_property_read_bool(of_node, "ti,min-output-impedance")) 212 dp83869->io_impedance = DP83869_IO_MUX_CFG_IO_IMPEDANCE_MIN; 213 214 if (of_property_read_bool(of_node, "enet-phy-lane-swap")) { 215 dp83869->port_mirroring = DP83869_PORT_MIRRORING_EN; 216 } else { 217 /* If the lane swap is not in the DT then check the straps */ 218 ret = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_STRAP_STS1); 219 if (ret < 0) 220 return ret; 221 if (ret & DP83869_STRAP_MIRROR_ENABLED) 222 dp83869->port_mirroring = DP83869_PORT_MIRRORING_EN; 223 else 224 dp83869->port_mirroring = DP83869_PORT_MIRRORING_DIS; 225 } 226 227 if (of_property_read_u32(of_node, "rx-fifo-depth", 228 &dp83869->rx_fifo_depth)) 229 dp83869->rx_fifo_depth = DP83869_PHYCR_FIFO_DEPTH_4_B_NIB; 230 231 if (of_property_read_u32(of_node, "tx-fifo-depth", 232 &dp83869->tx_fifo_depth)) 233 dp83869->tx_fifo_depth = DP83869_PHYCR_FIFO_DEPTH_4_B_NIB; 234 235 return ret; 236 } 237 #else 238 static int dp83869_of_init(struct phy_device *phydev) 239 { 240 return dp83869_set_strapped_mode(phydev); 241 } 242 #endif /* CONFIG_OF_MDIO */ 243 244 static int dp83869_configure_rgmii(struct phy_device *phydev, 245 struct dp83869_private *dp83869) 246 { 247 int ret = 0, val; 248 249 if (phy_interface_is_rgmii(phydev)) { 250 val = phy_read(phydev, MII_DP83869_PHYCTRL); 251 if (val < 0) 252 return val; 253 254 val &= ~DP83869_PHYCR_FIFO_DEPTH_MASK; 255 val |= (dp83869->tx_fifo_depth << DP83869_TX_FIFO_SHIFT); 256 val |= (dp83869->rx_fifo_depth << DP83869_RX_FIFO_SHIFT); 257 258 ret = phy_write(phydev, MII_DP83869_PHYCTRL, val); 259 if (ret) 260 return ret; 261 } 262 263 if (dp83869->io_impedance >= 0) 264 ret = phy_modify_mmd(phydev, DP83869_DEVADDR, 265 DP83869_IO_MUX_CFG, 266 DP83869_IO_MUX_CFG_IO_IMPEDANCE_CTRL, 267 dp83869->io_impedance & 268 DP83869_IO_MUX_CFG_IO_IMPEDANCE_CTRL); 269 270 return ret; 271 } 272 273 static int dp83869_configure_mode(struct phy_device *phydev, 274 struct dp83869_private *dp83869) 275 { 276 int phy_ctrl_val; 277 int ret; 278 279 if (dp83869->mode < DP83869_RGMII_COPPER_ETHERNET || 280 dp83869->mode > DP83869_SGMII_COPPER_ETHERNET) 281 return -EINVAL; 282 283 /* Below init sequence for each operational mode is defined in 284 * section 9.4.8 of the datasheet. 285 */ 286 ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_OP_MODE, 287 dp83869->mode); 288 if (ret) 289 return ret; 290 291 ret = phy_write(phydev, MII_BMCR, MII_DP83869_BMCR_DEFAULT); 292 if (ret) 293 return ret; 294 295 phy_ctrl_val = (dp83869->rx_fifo_depth << DP83869_RX_FIFO_SHIFT | 296 dp83869->tx_fifo_depth << DP83869_TX_FIFO_SHIFT | 297 DP83869_PHY_CTRL_DEFAULT); 298 299 switch (dp83869->mode) { 300 case DP83869_RGMII_COPPER_ETHERNET: 301 ret = phy_write(phydev, MII_DP83869_PHYCTRL, 302 phy_ctrl_val); 303 if (ret) 304 return ret; 305 306 ret = phy_write(phydev, MII_CTRL1000, DP83869_CFG1_DEFAULT); 307 if (ret) 308 return ret; 309 310 ret = dp83869_configure_rgmii(phydev, dp83869); 311 if (ret) 312 return ret; 313 break; 314 case DP83869_RGMII_SGMII_BRIDGE: 315 ret = phy_modify_mmd(phydev, DP83869_DEVADDR, DP83869_OP_MODE, 316 DP83869_SGMII_RGMII_BRIDGE, 317 DP83869_SGMII_RGMII_BRIDGE); 318 if (ret) 319 return ret; 320 321 ret = phy_write_mmd(phydev, DP83869_DEVADDR, 322 DP83869_FX_CTRL, DP83869_FX_CTRL_DEFAULT); 323 if (ret) 324 return ret; 325 326 break; 327 case DP83869_1000M_MEDIA_CONVERT: 328 ret = phy_write(phydev, MII_DP83869_PHYCTRL, 329 phy_ctrl_val); 330 if (ret) 331 return ret; 332 333 ret = phy_write_mmd(phydev, DP83869_DEVADDR, 334 DP83869_FX_CTRL, DP83869_FX_CTRL_DEFAULT); 335 if (ret) 336 return ret; 337 break; 338 case DP83869_100M_MEDIA_CONVERT: 339 ret = phy_write(phydev, MII_DP83869_PHYCTRL, 340 phy_ctrl_val); 341 if (ret) 342 return ret; 343 break; 344 case DP83869_SGMII_COPPER_ETHERNET: 345 ret = phy_write(phydev, MII_DP83869_PHYCTRL, 346 phy_ctrl_val); 347 if (ret) 348 return ret; 349 350 ret = phy_write(phydev, MII_CTRL1000, DP83869_CFG1_DEFAULT); 351 if (ret) 352 return ret; 353 354 ret = phy_write_mmd(phydev, DP83869_DEVADDR, 355 DP83869_FX_CTRL, DP83869_FX_CTRL_DEFAULT); 356 if (ret) 357 return ret; 358 359 break; 360 case DP83869_RGMII_1000_BASE: 361 case DP83869_RGMII_100_BASE: 362 break; 363 default: 364 return -EINVAL; 365 } 366 367 return ret; 368 } 369 370 static int dp83869_config_init(struct phy_device *phydev) 371 { 372 struct dp83869_private *dp83869 = phydev->priv; 373 int ret, val; 374 375 ret = dp83869_configure_mode(phydev, dp83869); 376 if (ret) 377 return ret; 378 379 /* Enable Interrupt output INT_OE in CFG4 register */ 380 if (phy_interrupt_is_valid(phydev)) { 381 val = phy_read(phydev, DP83869_CFG4); 382 val |= DP83869_INT_OE; 383 phy_write(phydev, DP83869_CFG4, val); 384 } 385 386 if (dp83869->port_mirroring != DP83869_PORT_MIRRORING_KEEP) 387 dp83869_config_port_mirroring(phydev); 388 389 /* Clock output selection if muxing property is set */ 390 if (dp83869->clk_output_sel != DP83869_CLK_O_SEL_REF_CLK) 391 ret = phy_modify_mmd(phydev, 392 DP83869_DEVADDR, DP83869_IO_MUX_CFG, 393 DP83869_IO_MUX_CFG_CLK_O_SEL_MASK, 394 dp83869->clk_output_sel << 395 DP83869_IO_MUX_CFG_CLK_O_SEL_SHIFT); 396 397 return ret; 398 } 399 400 static int dp83869_probe(struct phy_device *phydev) 401 { 402 struct dp83869_private *dp83869; 403 int ret; 404 405 dp83869 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83869), 406 GFP_KERNEL); 407 if (!dp83869) 408 return -ENOMEM; 409 410 phydev->priv = dp83869; 411 412 ret = dp83869_of_init(phydev); 413 if (ret) 414 return ret; 415 416 return dp83869_config_init(phydev); 417 } 418 419 static int dp83869_phy_reset(struct phy_device *phydev) 420 { 421 int ret; 422 423 ret = phy_write(phydev, DP83869_CTRL, DP83869_SW_RESET); 424 if (ret < 0) 425 return ret; 426 427 usleep_range(10, 20); 428 429 /* Global sw reset sets all registers to default. 430 * Need to set the registers in the PHY to the right config. 431 */ 432 return dp83869_config_init(phydev); 433 } 434 435 static struct phy_driver dp83869_driver[] = { 436 { 437 PHY_ID_MATCH_MODEL(DP83869_PHY_ID), 438 .name = "TI DP83869", 439 440 .probe = dp83869_probe, 441 .config_init = dp83869_config_init, 442 .soft_reset = dp83869_phy_reset, 443 444 /* IRQ related */ 445 .ack_interrupt = dp83869_ack_interrupt, 446 .config_intr = dp83869_config_intr, 447 448 .suspend = genphy_suspend, 449 .resume = genphy_resume, 450 }, 451 }; 452 module_phy_driver(dp83869_driver); 453 454 static struct mdio_device_id __maybe_unused dp83869_tbl[] = { 455 { PHY_ID_MATCH_MODEL(DP83869_PHY_ID) }, 456 { } 457 }; 458 MODULE_DEVICE_TABLE(mdio, dp83869_tbl); 459 460 MODULE_DESCRIPTION("Texas Instruments DP83869 PHY driver"); 461 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com"); 462 MODULE_LICENSE("GPL v2"); 463