1 // SPDX-License-Identifier: GPL-2.0 2 /* Driver for the Texas Instruments DP83869 PHY 3 * Copyright (C) 2019 Texas Instruments Inc. 4 */ 5 6 #include <linux/ethtool.h> 7 #include <linux/kernel.h> 8 #include <linux/mii.h> 9 #include <linux/module.h> 10 #include <linux/of.h> 11 #include <linux/phy.h> 12 #include <linux/delay.h> 13 14 #include <dt-bindings/net/ti-dp83869.h> 15 16 #define DP83869_PHY_ID 0x2000a0f1 17 #define DP83869_DEVADDR 0x1f 18 19 #define MII_DP83869_PHYCTRL 0x10 20 #define MII_DP83869_MICR 0x12 21 #define MII_DP83869_ISR 0x13 22 #define DP83869_CTRL 0x1f 23 #define DP83869_CFG4 0x1e 24 25 /* Extended Registers */ 26 #define DP83869_GEN_CFG3 0x0031 27 #define DP83869_RGMIICTL 0x0032 28 #define DP83869_STRAP_STS1 0x006e 29 #define DP83869_RGMIIDCTL 0x0086 30 #define DP83869_IO_MUX_CFG 0x0170 31 #define DP83869_OP_MODE 0x01df 32 #define DP83869_FX_CTRL 0x0c00 33 34 #define DP83869_SW_RESET BIT(15) 35 #define DP83869_SW_RESTART BIT(14) 36 37 /* MICR Interrupt bits */ 38 #define MII_DP83869_MICR_AN_ERR_INT_EN BIT(15) 39 #define MII_DP83869_MICR_SPEED_CHNG_INT_EN BIT(14) 40 #define MII_DP83869_MICR_DUP_MODE_CHNG_INT_EN BIT(13) 41 #define MII_DP83869_MICR_PAGE_RXD_INT_EN BIT(12) 42 #define MII_DP83869_MICR_AUTONEG_COMP_INT_EN BIT(11) 43 #define MII_DP83869_MICR_LINK_STS_CHNG_INT_EN BIT(10) 44 #define MII_DP83869_MICR_FALSE_CARRIER_INT_EN BIT(8) 45 #define MII_DP83869_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4) 46 #define MII_DP83869_MICR_WOL_INT_EN BIT(3) 47 #define MII_DP83869_MICR_XGMII_ERR_INT_EN BIT(2) 48 #define MII_DP83869_MICR_POL_CHNG_INT_EN BIT(1) 49 #define MII_DP83869_MICR_JABBER_INT_EN BIT(0) 50 51 #define MII_DP83869_BMCR_DEFAULT (BMCR_ANENABLE | \ 52 BMCR_FULLDPLX | \ 53 BMCR_SPEED1000) 54 55 /* This is the same bit mask as the BMCR so re-use the BMCR default */ 56 #define DP83869_FX_CTRL_DEFAULT MII_DP83869_BMCR_DEFAULT 57 58 /* CFG1 bits */ 59 #define DP83869_CFG1_DEFAULT (ADVERTISE_1000HALF | \ 60 ADVERTISE_1000FULL | \ 61 CTL1000_AS_MASTER) 62 63 /* RGMIICTL bits */ 64 #define DP83869_RGMII_TX_CLK_DELAY_EN BIT(1) 65 #define DP83869_RGMII_RX_CLK_DELAY_EN BIT(0) 66 67 /* RGMIIDCTL */ 68 #define DP83869_RGMII_CLK_DELAY_SHIFT 4 69 #define DP83869_CLK_DELAY_DEF 7 70 71 /* STRAP_STS1 bits */ 72 #define DP83869_STRAP_OP_MODE_MASK GENMASK(2, 0) 73 #define DP83869_STRAP_STS1_RESERVED BIT(11) 74 #define DP83869_STRAP_MIRROR_ENABLED BIT(12) 75 76 /* PHYCTRL bits */ 77 #define DP83869_RX_FIFO_SHIFT 12 78 #define DP83869_TX_FIFO_SHIFT 14 79 80 /* PHY_CTRL lower bytes 0x48 are declared as reserved */ 81 #define DP83869_PHY_CTRL_DEFAULT 0x48 82 #define DP83869_PHYCR_FIFO_DEPTH_MASK GENMASK(15, 12) 83 #define DP83869_PHYCR_RESERVED_MASK BIT(11) 84 85 /* IO_MUX_CFG bits */ 86 #define DP83869_IO_MUX_CFG_IO_IMPEDANCE_CTRL 0x1f 87 88 #define DP83869_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0 89 #define DP83869_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f 90 #define DP83869_IO_MUX_CFG_CLK_O_SEL_MASK (0x1f << 8) 91 #define DP83869_IO_MUX_CFG_CLK_O_SEL_SHIFT 8 92 93 /* CFG3 bits */ 94 #define DP83869_CFG3_PORT_MIRROR_EN BIT(0) 95 96 /* CFG4 bits */ 97 #define DP83869_INT_OE BIT(7) 98 99 /* OP MODE */ 100 #define DP83869_OP_MODE_MII BIT(5) 101 #define DP83869_SGMII_RGMII_BRIDGE BIT(6) 102 103 enum { 104 DP83869_PORT_MIRRORING_KEEP, 105 DP83869_PORT_MIRRORING_EN, 106 DP83869_PORT_MIRRORING_DIS, 107 }; 108 109 struct dp83869_private { 110 int tx_fifo_depth; 111 int rx_fifo_depth; 112 s32 rx_int_delay; 113 s32 tx_int_delay; 114 int io_impedance; 115 int port_mirroring; 116 bool rxctrl_strap_quirk; 117 int clk_output_sel; 118 int mode; 119 }; 120 121 static int dp83869_ack_interrupt(struct phy_device *phydev) 122 { 123 int err = phy_read(phydev, MII_DP83869_ISR); 124 125 if (err < 0) 126 return err; 127 128 return 0; 129 } 130 131 static int dp83869_config_intr(struct phy_device *phydev) 132 { 133 int micr_status = 0; 134 135 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 136 micr_status = phy_read(phydev, MII_DP83869_MICR); 137 if (micr_status < 0) 138 return micr_status; 139 140 micr_status |= 141 (MII_DP83869_MICR_AN_ERR_INT_EN | 142 MII_DP83869_MICR_SPEED_CHNG_INT_EN | 143 MII_DP83869_MICR_AUTONEG_COMP_INT_EN | 144 MII_DP83869_MICR_LINK_STS_CHNG_INT_EN | 145 MII_DP83869_MICR_DUP_MODE_CHNG_INT_EN | 146 MII_DP83869_MICR_SLEEP_MODE_CHNG_INT_EN); 147 148 return phy_write(phydev, MII_DP83869_MICR, micr_status); 149 } 150 151 return phy_write(phydev, MII_DP83869_MICR, micr_status); 152 } 153 154 static int dp83869_config_port_mirroring(struct phy_device *phydev) 155 { 156 struct dp83869_private *dp83869 = phydev->priv; 157 158 if (dp83869->port_mirroring == DP83869_PORT_MIRRORING_EN) 159 return phy_set_bits_mmd(phydev, DP83869_DEVADDR, 160 DP83869_GEN_CFG3, 161 DP83869_CFG3_PORT_MIRROR_EN); 162 else 163 return phy_clear_bits_mmd(phydev, DP83869_DEVADDR, 164 DP83869_GEN_CFG3, 165 DP83869_CFG3_PORT_MIRROR_EN); 166 } 167 168 static int dp83869_set_strapped_mode(struct phy_device *phydev) 169 { 170 struct dp83869_private *dp83869 = phydev->priv; 171 int val; 172 173 val = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_STRAP_STS1); 174 if (val < 0) 175 return val; 176 177 dp83869->mode = val & DP83869_STRAP_OP_MODE_MASK; 178 179 return 0; 180 } 181 182 #if IS_ENABLED(CONFIG_OF_MDIO) 183 static const int dp83869_internal_delay[] = {250, 500, 750, 1000, 1250, 1500, 184 1750, 2000, 2250, 2500, 2750, 3000, 185 3250, 3500, 3750, 4000}; 186 187 static int dp83869_of_init(struct phy_device *phydev) 188 { 189 struct dp83869_private *dp83869 = phydev->priv; 190 struct device *dev = &phydev->mdio.dev; 191 struct device_node *of_node = dev->of_node; 192 int delay_size = ARRAY_SIZE(dp83869_internal_delay); 193 int ret; 194 195 if (!of_node) 196 return -ENODEV; 197 198 dp83869->io_impedance = -EINVAL; 199 200 /* Optional configuration */ 201 ret = of_property_read_u32(of_node, "ti,clk-output-sel", 202 &dp83869->clk_output_sel); 203 if (ret || dp83869->clk_output_sel > DP83869_CLK_O_SEL_REF_CLK) 204 dp83869->clk_output_sel = DP83869_CLK_O_SEL_REF_CLK; 205 206 ret = of_property_read_u32(of_node, "ti,op-mode", &dp83869->mode); 207 if (ret == 0) { 208 if (dp83869->mode < DP83869_RGMII_COPPER_ETHERNET || 209 dp83869->mode > DP83869_SGMII_COPPER_ETHERNET) 210 return -EINVAL; 211 } else { 212 ret = dp83869_set_strapped_mode(phydev); 213 if (ret) 214 return ret; 215 } 216 217 if (of_property_read_bool(of_node, "ti,max-output-impedance")) 218 dp83869->io_impedance = DP83869_IO_MUX_CFG_IO_IMPEDANCE_MAX; 219 else if (of_property_read_bool(of_node, "ti,min-output-impedance")) 220 dp83869->io_impedance = DP83869_IO_MUX_CFG_IO_IMPEDANCE_MIN; 221 222 if (of_property_read_bool(of_node, "enet-phy-lane-swap")) { 223 dp83869->port_mirroring = DP83869_PORT_MIRRORING_EN; 224 } else { 225 /* If the lane swap is not in the DT then check the straps */ 226 ret = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_STRAP_STS1); 227 if (ret < 0) 228 return ret; 229 230 if (ret & DP83869_STRAP_MIRROR_ENABLED) 231 dp83869->port_mirroring = DP83869_PORT_MIRRORING_EN; 232 else 233 dp83869->port_mirroring = DP83869_PORT_MIRRORING_DIS; 234 235 ret = 0; 236 } 237 238 if (of_property_read_u32(of_node, "rx-fifo-depth", 239 &dp83869->rx_fifo_depth)) 240 dp83869->rx_fifo_depth = DP83869_PHYCR_FIFO_DEPTH_4_B_NIB; 241 242 if (of_property_read_u32(of_node, "tx-fifo-depth", 243 &dp83869->tx_fifo_depth)) 244 dp83869->tx_fifo_depth = DP83869_PHYCR_FIFO_DEPTH_4_B_NIB; 245 246 dp83869->rx_int_delay = phy_get_internal_delay(phydev, dev, 247 &dp83869_internal_delay[0], 248 delay_size, true); 249 if (dp83869->rx_int_delay < 0) 250 dp83869->rx_int_delay = 251 dp83869_internal_delay[DP83869_CLK_DELAY_DEF]; 252 253 dp83869->tx_int_delay = phy_get_internal_delay(phydev, dev, 254 &dp83869_internal_delay[0], 255 delay_size, false); 256 if (dp83869->tx_int_delay < 0) 257 dp83869->tx_int_delay = 258 dp83869_internal_delay[DP83869_CLK_DELAY_DEF]; 259 260 return ret; 261 } 262 #else 263 static int dp83869_of_init(struct phy_device *phydev) 264 { 265 return dp83869_set_strapped_mode(phydev); 266 } 267 #endif /* CONFIG_OF_MDIO */ 268 269 static int dp83869_configure_rgmii(struct phy_device *phydev, 270 struct dp83869_private *dp83869) 271 { 272 int ret = 0, val; 273 274 if (phy_interface_is_rgmii(phydev)) { 275 val = phy_read(phydev, MII_DP83869_PHYCTRL); 276 if (val < 0) 277 return val; 278 279 val &= ~DP83869_PHYCR_FIFO_DEPTH_MASK; 280 val |= (dp83869->tx_fifo_depth << DP83869_TX_FIFO_SHIFT); 281 val |= (dp83869->rx_fifo_depth << DP83869_RX_FIFO_SHIFT); 282 283 ret = phy_write(phydev, MII_DP83869_PHYCTRL, val); 284 if (ret) 285 return ret; 286 } 287 288 if (dp83869->io_impedance >= 0) 289 ret = phy_modify_mmd(phydev, DP83869_DEVADDR, 290 DP83869_IO_MUX_CFG, 291 DP83869_IO_MUX_CFG_IO_IMPEDANCE_CTRL, 292 dp83869->io_impedance & 293 DP83869_IO_MUX_CFG_IO_IMPEDANCE_CTRL); 294 295 return ret; 296 } 297 298 static int dp83869_configure_mode(struct phy_device *phydev, 299 struct dp83869_private *dp83869) 300 { 301 int phy_ctrl_val; 302 int ret; 303 304 if (dp83869->mode < DP83869_RGMII_COPPER_ETHERNET || 305 dp83869->mode > DP83869_SGMII_COPPER_ETHERNET) 306 return -EINVAL; 307 308 /* Below init sequence for each operational mode is defined in 309 * section 9.4.8 of the datasheet. 310 */ 311 ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_OP_MODE, 312 dp83869->mode); 313 if (ret) 314 return ret; 315 316 ret = phy_write(phydev, MII_BMCR, MII_DP83869_BMCR_DEFAULT); 317 if (ret) 318 return ret; 319 320 phy_ctrl_val = (dp83869->rx_fifo_depth << DP83869_RX_FIFO_SHIFT | 321 dp83869->tx_fifo_depth << DP83869_TX_FIFO_SHIFT | 322 DP83869_PHY_CTRL_DEFAULT); 323 324 switch (dp83869->mode) { 325 case DP83869_RGMII_COPPER_ETHERNET: 326 ret = phy_write(phydev, MII_DP83869_PHYCTRL, 327 phy_ctrl_val); 328 if (ret) 329 return ret; 330 331 ret = phy_write(phydev, MII_CTRL1000, DP83869_CFG1_DEFAULT); 332 if (ret) 333 return ret; 334 335 ret = dp83869_configure_rgmii(phydev, dp83869); 336 if (ret) 337 return ret; 338 break; 339 case DP83869_RGMII_SGMII_BRIDGE: 340 ret = phy_modify_mmd(phydev, DP83869_DEVADDR, DP83869_OP_MODE, 341 DP83869_SGMII_RGMII_BRIDGE, 342 DP83869_SGMII_RGMII_BRIDGE); 343 if (ret) 344 return ret; 345 346 ret = phy_write_mmd(phydev, DP83869_DEVADDR, 347 DP83869_FX_CTRL, DP83869_FX_CTRL_DEFAULT); 348 if (ret) 349 return ret; 350 351 break; 352 case DP83869_1000M_MEDIA_CONVERT: 353 ret = phy_write(phydev, MII_DP83869_PHYCTRL, 354 phy_ctrl_val); 355 if (ret) 356 return ret; 357 358 ret = phy_write_mmd(phydev, DP83869_DEVADDR, 359 DP83869_FX_CTRL, DP83869_FX_CTRL_DEFAULT); 360 if (ret) 361 return ret; 362 break; 363 case DP83869_100M_MEDIA_CONVERT: 364 ret = phy_write(phydev, MII_DP83869_PHYCTRL, 365 phy_ctrl_val); 366 if (ret) 367 return ret; 368 break; 369 case DP83869_SGMII_COPPER_ETHERNET: 370 ret = phy_write(phydev, MII_DP83869_PHYCTRL, 371 phy_ctrl_val); 372 if (ret) 373 return ret; 374 375 ret = phy_write(phydev, MII_CTRL1000, DP83869_CFG1_DEFAULT); 376 if (ret) 377 return ret; 378 379 ret = phy_write_mmd(phydev, DP83869_DEVADDR, 380 DP83869_FX_CTRL, DP83869_FX_CTRL_DEFAULT); 381 if (ret) 382 return ret; 383 384 break; 385 case DP83869_RGMII_1000_BASE: 386 case DP83869_RGMII_100_BASE: 387 break; 388 default: 389 return -EINVAL; 390 } 391 392 return ret; 393 } 394 395 static int dp83869_config_init(struct phy_device *phydev) 396 { 397 struct dp83869_private *dp83869 = phydev->priv; 398 int ret, val; 399 400 ret = dp83869_configure_mode(phydev, dp83869); 401 if (ret) 402 return ret; 403 404 /* Enable Interrupt output INT_OE in CFG4 register */ 405 if (phy_interrupt_is_valid(phydev)) { 406 val = phy_read(phydev, DP83869_CFG4); 407 val |= DP83869_INT_OE; 408 phy_write(phydev, DP83869_CFG4, val); 409 } 410 411 if (dp83869->port_mirroring != DP83869_PORT_MIRRORING_KEEP) 412 dp83869_config_port_mirroring(phydev); 413 414 /* Clock output selection if muxing property is set */ 415 if (dp83869->clk_output_sel != DP83869_CLK_O_SEL_REF_CLK) 416 ret = phy_modify_mmd(phydev, 417 DP83869_DEVADDR, DP83869_IO_MUX_CFG, 418 DP83869_IO_MUX_CFG_CLK_O_SEL_MASK, 419 dp83869->clk_output_sel << 420 DP83869_IO_MUX_CFG_CLK_O_SEL_SHIFT); 421 422 if (phy_interface_is_rgmii(phydev)) { 423 ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIIDCTL, 424 dp83869->rx_int_delay | 425 dp83869->tx_int_delay << DP83869_RGMII_CLK_DELAY_SHIFT); 426 if (ret) 427 return ret; 428 429 val = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIICTL); 430 val &= ~(DP83869_RGMII_TX_CLK_DELAY_EN | 431 DP83869_RGMII_RX_CLK_DELAY_EN); 432 433 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) 434 val |= (DP83869_RGMII_TX_CLK_DELAY_EN | 435 DP83869_RGMII_RX_CLK_DELAY_EN); 436 437 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) 438 val |= DP83869_RGMII_TX_CLK_DELAY_EN; 439 440 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) 441 val |= DP83869_RGMII_RX_CLK_DELAY_EN; 442 443 ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIICTL, 444 val); 445 } 446 447 return ret; 448 } 449 450 static int dp83869_probe(struct phy_device *phydev) 451 { 452 struct dp83869_private *dp83869; 453 int ret; 454 455 dp83869 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83869), 456 GFP_KERNEL); 457 if (!dp83869) 458 return -ENOMEM; 459 460 phydev->priv = dp83869; 461 462 ret = dp83869_of_init(phydev); 463 if (ret) 464 return ret; 465 466 return dp83869_config_init(phydev); 467 } 468 469 static int dp83869_phy_reset(struct phy_device *phydev) 470 { 471 int ret; 472 473 ret = phy_write(phydev, DP83869_CTRL, DP83869_SW_RESET); 474 if (ret < 0) 475 return ret; 476 477 usleep_range(10, 20); 478 479 /* Global sw reset sets all registers to default. 480 * Need to set the registers in the PHY to the right config. 481 */ 482 return dp83869_config_init(phydev); 483 } 484 485 static struct phy_driver dp83869_driver[] = { 486 { 487 PHY_ID_MATCH_MODEL(DP83869_PHY_ID), 488 .name = "TI DP83869", 489 490 .probe = dp83869_probe, 491 .config_init = dp83869_config_init, 492 .soft_reset = dp83869_phy_reset, 493 494 /* IRQ related */ 495 .ack_interrupt = dp83869_ack_interrupt, 496 .config_intr = dp83869_config_intr, 497 498 .suspend = genphy_suspend, 499 .resume = genphy_resume, 500 }, 501 }; 502 module_phy_driver(dp83869_driver); 503 504 static struct mdio_device_id __maybe_unused dp83869_tbl[] = { 505 { PHY_ID_MATCH_MODEL(DP83869_PHY_ID) }, 506 { } 507 }; 508 MODULE_DEVICE_TABLE(mdio, dp83869_tbl); 509 510 MODULE_DESCRIPTION("Texas Instruments DP83869 PHY driver"); 511 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com"); 512 MODULE_LICENSE("GPL v2"); 513