1 // SPDX-License-Identifier: GPL-2.0 2 /* Driver for the Texas Instruments DP83822, DP83825 and DP83826 PHYs. 3 * 4 * Copyright (C) 2017 Texas Instruments Inc. 5 */ 6 7 #include <linux/ethtool.h> 8 #include <linux/etherdevice.h> 9 #include <linux/kernel.h> 10 #include <linux/mii.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/phy.h> 14 #include <linux/netdevice.h> 15 16 #define DP83822_PHY_ID 0x2000a240 17 #define DP83825S_PHY_ID 0x2000a140 18 #define DP83825I_PHY_ID 0x2000a150 19 #define DP83825CM_PHY_ID 0x2000a160 20 #define DP83825CS_PHY_ID 0x2000a170 21 #define DP83826C_PHY_ID 0x2000a130 22 #define DP83826NC_PHY_ID 0x2000a110 23 24 #define DP83822_DEVADDR 0x1f 25 26 #define MII_DP83822_CTRL_2 0x0a 27 #define MII_DP83822_PHYSTS 0x10 28 #define MII_DP83822_PHYSCR 0x11 29 #define MII_DP83822_MISR1 0x12 30 #define MII_DP83822_MISR2 0x13 31 #define MII_DP83822_FCSCR 0x14 32 #define MII_DP83822_RCSR 0x17 33 #define MII_DP83822_RESET_CTRL 0x1f 34 #define MII_DP83822_GENCFG 0x465 35 #define MII_DP83822_SOR1 0x467 36 37 /* GENCFG */ 38 #define DP83822_SIG_DET_LOW BIT(0) 39 40 /* Control Register 2 bits */ 41 #define DP83822_FX_ENABLE BIT(14) 42 43 #define DP83822_HW_RESET BIT(15) 44 #define DP83822_SW_RESET BIT(14) 45 46 /* PHY STS bits */ 47 #define DP83822_PHYSTS_DUPLEX BIT(2) 48 #define DP83822_PHYSTS_10 BIT(1) 49 #define DP83822_PHYSTS_LINK BIT(0) 50 51 /* PHYSCR Register Fields */ 52 #define DP83822_PHYSCR_INT_OE BIT(0) /* Interrupt Output Enable */ 53 #define DP83822_PHYSCR_INTEN BIT(1) /* Interrupt Enable */ 54 55 /* MISR1 bits */ 56 #define DP83822_RX_ERR_HF_INT_EN BIT(0) 57 #define DP83822_FALSE_CARRIER_HF_INT_EN BIT(1) 58 #define DP83822_ANEG_COMPLETE_INT_EN BIT(2) 59 #define DP83822_DUP_MODE_CHANGE_INT_EN BIT(3) 60 #define DP83822_SPEED_CHANGED_INT_EN BIT(4) 61 #define DP83822_LINK_STAT_INT_EN BIT(5) 62 #define DP83822_ENERGY_DET_INT_EN BIT(6) 63 #define DP83822_LINK_QUAL_INT_EN BIT(7) 64 65 /* MISR2 bits */ 66 #define DP83822_JABBER_DET_INT_EN BIT(0) 67 #define DP83822_WOL_PKT_INT_EN BIT(1) 68 #define DP83822_SLEEP_MODE_INT_EN BIT(2) 69 #define DP83822_MDI_XOVER_INT_EN BIT(3) 70 #define DP83822_LB_FIFO_INT_EN BIT(4) 71 #define DP83822_PAGE_RX_INT_EN BIT(5) 72 #define DP83822_ANEG_ERR_INT_EN BIT(6) 73 #define DP83822_EEE_ERROR_CHANGE_INT_EN BIT(7) 74 75 /* INT_STAT1 bits */ 76 #define DP83822_WOL_INT_EN BIT(4) 77 #define DP83822_WOL_INT_STAT BIT(12) 78 79 #define MII_DP83822_RXSOP1 0x04a5 80 #define MII_DP83822_RXSOP2 0x04a6 81 #define MII_DP83822_RXSOP3 0x04a7 82 83 /* WoL Registers */ 84 #define MII_DP83822_WOL_CFG 0x04a0 85 #define MII_DP83822_WOL_STAT 0x04a1 86 #define MII_DP83822_WOL_DA1 0x04a2 87 #define MII_DP83822_WOL_DA2 0x04a3 88 #define MII_DP83822_WOL_DA3 0x04a4 89 90 /* WoL bits */ 91 #define DP83822_WOL_MAGIC_EN BIT(0) 92 #define DP83822_WOL_SECURE_ON BIT(5) 93 #define DP83822_WOL_EN BIT(7) 94 #define DP83822_WOL_INDICATION_SEL BIT(8) 95 #define DP83822_WOL_CLR_INDICATION BIT(11) 96 97 /* RCSR bits */ 98 #define DP83822_RGMII_MODE_EN BIT(9) 99 #define DP83822_RX_CLK_SHIFT BIT(12) 100 #define DP83822_TX_CLK_SHIFT BIT(11) 101 102 /* SOR1 mode */ 103 #define DP83822_STRAP_MODE1 0 104 #define DP83822_STRAP_MODE2 BIT(0) 105 #define DP83822_STRAP_MODE3 BIT(1) 106 #define DP83822_STRAP_MODE4 GENMASK(1, 0) 107 108 #define DP83822_COL_STRAP_MASK GENMASK(11, 10) 109 #define DP83822_COL_SHIFT 10 110 #define DP83822_RX_ER_STR_MASK GENMASK(9, 8) 111 #define DP83822_RX_ER_SHIFT 8 112 113 #define MII_DP83822_FIBER_ADVERTISE (ADVERTISED_TP | ADVERTISED_MII | \ 114 ADVERTISED_FIBRE | \ 115 ADVERTISED_Pause | ADVERTISED_Asym_Pause) 116 117 struct dp83822_private { 118 bool fx_signal_det_low; 119 int fx_enabled; 120 u16 fx_sd_enable; 121 }; 122 123 static int dp83822_set_wol(struct phy_device *phydev, 124 struct ethtool_wolinfo *wol) 125 { 126 struct net_device *ndev = phydev->attached_dev; 127 u16 value; 128 const u8 *mac; 129 130 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE)) { 131 mac = (const u8 *)ndev->dev_addr; 132 133 if (!is_valid_ether_addr(mac)) 134 return -EINVAL; 135 136 /* MAC addresses start with byte 5, but stored in mac[0]. 137 * 822 PHYs store bytes 4|5, 2|3, 0|1 138 */ 139 phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA1, 140 (mac[1] << 8) | mac[0]); 141 phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA2, 142 (mac[3] << 8) | mac[2]); 143 phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA3, 144 (mac[5] << 8) | mac[4]); 145 146 value = phy_read_mmd(phydev, DP83822_DEVADDR, 147 MII_DP83822_WOL_CFG); 148 if (wol->wolopts & WAKE_MAGIC) 149 value |= DP83822_WOL_MAGIC_EN; 150 else 151 value &= ~DP83822_WOL_MAGIC_EN; 152 153 if (wol->wolopts & WAKE_MAGICSECURE) { 154 phy_write_mmd(phydev, DP83822_DEVADDR, 155 MII_DP83822_RXSOP1, 156 (wol->sopass[1] << 8) | wol->sopass[0]); 157 phy_write_mmd(phydev, DP83822_DEVADDR, 158 MII_DP83822_RXSOP2, 159 (wol->sopass[3] << 8) | wol->sopass[2]); 160 phy_write_mmd(phydev, DP83822_DEVADDR, 161 MII_DP83822_RXSOP3, 162 (wol->sopass[5] << 8) | wol->sopass[4]); 163 value |= DP83822_WOL_SECURE_ON; 164 } else { 165 value &= ~DP83822_WOL_SECURE_ON; 166 } 167 168 /* Clear any pending WoL interrupt */ 169 phy_read(phydev, MII_DP83822_MISR2); 170 171 value |= DP83822_WOL_EN | DP83822_WOL_INDICATION_SEL | 172 DP83822_WOL_CLR_INDICATION; 173 174 return phy_write_mmd(phydev, DP83822_DEVADDR, 175 MII_DP83822_WOL_CFG, value); 176 } else { 177 return phy_clear_bits_mmd(phydev, DP83822_DEVADDR, 178 MII_DP83822_WOL_CFG, DP83822_WOL_EN); 179 } 180 } 181 182 static void dp83822_get_wol(struct phy_device *phydev, 183 struct ethtool_wolinfo *wol) 184 { 185 int value; 186 u16 sopass_val; 187 188 wol->supported = (WAKE_MAGIC | WAKE_MAGICSECURE); 189 wol->wolopts = 0; 190 191 value = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG); 192 193 if (value & DP83822_WOL_MAGIC_EN) 194 wol->wolopts |= WAKE_MAGIC; 195 196 if (value & DP83822_WOL_SECURE_ON) { 197 sopass_val = phy_read_mmd(phydev, DP83822_DEVADDR, 198 MII_DP83822_RXSOP1); 199 wol->sopass[0] = (sopass_val & 0xff); 200 wol->sopass[1] = (sopass_val >> 8); 201 202 sopass_val = phy_read_mmd(phydev, DP83822_DEVADDR, 203 MII_DP83822_RXSOP2); 204 wol->sopass[2] = (sopass_val & 0xff); 205 wol->sopass[3] = (sopass_val >> 8); 206 207 sopass_val = phy_read_mmd(phydev, DP83822_DEVADDR, 208 MII_DP83822_RXSOP3); 209 wol->sopass[4] = (sopass_val & 0xff); 210 wol->sopass[5] = (sopass_val >> 8); 211 212 wol->wolopts |= WAKE_MAGICSECURE; 213 } 214 215 /* WoL is not enabled so set wolopts to 0 */ 216 if (!(value & DP83822_WOL_EN)) 217 wol->wolopts = 0; 218 } 219 220 static int dp83822_config_intr(struct phy_device *phydev) 221 { 222 struct dp83822_private *dp83822 = phydev->priv; 223 int misr_status; 224 int physcr_status; 225 int err; 226 227 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 228 misr_status = phy_read(phydev, MII_DP83822_MISR1); 229 if (misr_status < 0) 230 return misr_status; 231 232 misr_status |= (DP83822_LINK_STAT_INT_EN | 233 DP83822_ENERGY_DET_INT_EN | 234 DP83822_LINK_QUAL_INT_EN); 235 236 /* Private data pointer is NULL on DP83825/26 */ 237 if (!dp83822 || !dp83822->fx_enabled) 238 misr_status |= DP83822_ANEG_COMPLETE_INT_EN | 239 DP83822_DUP_MODE_CHANGE_INT_EN | 240 DP83822_SPEED_CHANGED_INT_EN; 241 242 243 err = phy_write(phydev, MII_DP83822_MISR1, misr_status); 244 if (err < 0) 245 return err; 246 247 misr_status = phy_read(phydev, MII_DP83822_MISR2); 248 if (misr_status < 0) 249 return misr_status; 250 251 misr_status |= (DP83822_JABBER_DET_INT_EN | 252 DP83822_SLEEP_MODE_INT_EN | 253 DP83822_LB_FIFO_INT_EN | 254 DP83822_PAGE_RX_INT_EN | 255 DP83822_EEE_ERROR_CHANGE_INT_EN); 256 257 /* Private data pointer is NULL on DP83825/26 */ 258 if (!dp83822 || !dp83822->fx_enabled) 259 misr_status |= DP83822_ANEG_ERR_INT_EN | 260 DP83822_WOL_PKT_INT_EN; 261 262 err = phy_write(phydev, MII_DP83822_MISR2, misr_status); 263 if (err < 0) 264 return err; 265 266 physcr_status = phy_read(phydev, MII_DP83822_PHYSCR); 267 if (physcr_status < 0) 268 return physcr_status; 269 270 physcr_status |= DP83822_PHYSCR_INT_OE | DP83822_PHYSCR_INTEN; 271 272 } else { 273 err = phy_write(phydev, MII_DP83822_MISR1, 0); 274 if (err < 0) 275 return err; 276 277 err = phy_write(phydev, MII_DP83822_MISR2, 0); 278 if (err < 0) 279 return err; 280 281 physcr_status = phy_read(phydev, MII_DP83822_PHYSCR); 282 if (physcr_status < 0) 283 return physcr_status; 284 285 physcr_status &= ~DP83822_PHYSCR_INTEN; 286 } 287 288 return phy_write(phydev, MII_DP83822_PHYSCR, physcr_status); 289 } 290 291 static irqreturn_t dp83822_handle_interrupt(struct phy_device *phydev) 292 { 293 bool trigger_machine = false; 294 int irq_status; 295 296 /* The MISR1 and MISR2 registers are holding the interrupt status in 297 * the upper half (15:8), while the lower half (7:0) is used for 298 * controlling the interrupt enable state of those individual interrupt 299 * sources. To determine the possible interrupt sources, just read the 300 * MISR* register and use it directly to know which interrupts have 301 * been enabled previously or not. 302 */ 303 irq_status = phy_read(phydev, MII_DP83822_MISR1); 304 if (irq_status < 0) { 305 phy_error(phydev); 306 return IRQ_NONE; 307 } 308 if (irq_status & ((irq_status & GENMASK(7, 0)) << 8)) 309 trigger_machine = true; 310 311 irq_status = phy_read(phydev, MII_DP83822_MISR2); 312 if (irq_status < 0) { 313 phy_error(phydev); 314 return IRQ_NONE; 315 } 316 if (irq_status & ((irq_status & GENMASK(7, 0)) << 8)) 317 trigger_machine = true; 318 319 if (!trigger_machine) 320 return IRQ_NONE; 321 322 phy_trigger_machine(phydev); 323 324 return IRQ_HANDLED; 325 } 326 327 static int dp8382x_disable_wol(struct phy_device *phydev) 328 { 329 return phy_clear_bits_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG, 330 DP83822_WOL_EN | DP83822_WOL_MAGIC_EN | 331 DP83822_WOL_SECURE_ON); 332 } 333 334 static int dp83822_read_status(struct phy_device *phydev) 335 { 336 struct dp83822_private *dp83822 = phydev->priv; 337 int status = phy_read(phydev, MII_DP83822_PHYSTS); 338 int ctrl2; 339 int ret; 340 341 if (dp83822->fx_enabled) { 342 if (status & DP83822_PHYSTS_LINK) { 343 phydev->speed = SPEED_UNKNOWN; 344 phydev->duplex = DUPLEX_UNKNOWN; 345 } else { 346 ctrl2 = phy_read(phydev, MII_DP83822_CTRL_2); 347 if (ctrl2 < 0) 348 return ctrl2; 349 350 if (!(ctrl2 & DP83822_FX_ENABLE)) { 351 ret = phy_write(phydev, MII_DP83822_CTRL_2, 352 DP83822_FX_ENABLE | ctrl2); 353 if (ret < 0) 354 return ret; 355 } 356 } 357 } 358 359 ret = genphy_read_status(phydev); 360 if (ret) 361 return ret; 362 363 if (status < 0) 364 return status; 365 366 if (status & DP83822_PHYSTS_DUPLEX) 367 phydev->duplex = DUPLEX_FULL; 368 else 369 phydev->duplex = DUPLEX_HALF; 370 371 if (status & DP83822_PHYSTS_10) 372 phydev->speed = SPEED_10; 373 else 374 phydev->speed = SPEED_100; 375 376 return 0; 377 } 378 379 static int dp83822_config_init(struct phy_device *phydev) 380 { 381 struct dp83822_private *dp83822 = phydev->priv; 382 struct device *dev = &phydev->mdio.dev; 383 int rgmii_delay = 0; 384 s32 rx_int_delay; 385 s32 tx_int_delay; 386 int err = 0; 387 int bmcr; 388 389 if (phy_interface_is_rgmii(phydev)) { 390 rx_int_delay = phy_get_internal_delay(phydev, dev, NULL, 0, 391 true); 392 393 /* Set DP83822_RX_CLK_SHIFT to enable rx clk internal delay */ 394 if (rx_int_delay > 0) 395 rgmii_delay |= DP83822_RX_CLK_SHIFT; 396 397 tx_int_delay = phy_get_internal_delay(phydev, dev, NULL, 0, 398 false); 399 400 /* Set DP83822_TX_CLK_SHIFT to disable tx clk internal delay */ 401 if (tx_int_delay <= 0) 402 rgmii_delay |= DP83822_TX_CLK_SHIFT; 403 404 err = phy_modify_mmd(phydev, DP83822_DEVADDR, MII_DP83822_RCSR, 405 DP83822_RX_CLK_SHIFT | DP83822_TX_CLK_SHIFT, rgmii_delay); 406 if (err) 407 return err; 408 409 err = phy_set_bits_mmd(phydev, DP83822_DEVADDR, 410 MII_DP83822_RCSR, DP83822_RGMII_MODE_EN); 411 412 if (err) 413 return err; 414 } else { 415 err = phy_clear_bits_mmd(phydev, DP83822_DEVADDR, 416 MII_DP83822_RCSR, DP83822_RGMII_MODE_EN); 417 418 if (err) 419 return err; 420 } 421 422 if (dp83822->fx_enabled) { 423 err = phy_modify(phydev, MII_DP83822_CTRL_2, 424 DP83822_FX_ENABLE, 1); 425 if (err < 0) 426 return err; 427 428 /* Only allow advertising what this PHY supports */ 429 linkmode_and(phydev->advertising, phydev->advertising, 430 phydev->supported); 431 432 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, 433 phydev->supported); 434 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, 435 phydev->advertising); 436 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Full_BIT, 437 phydev->supported); 438 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Half_BIT, 439 phydev->supported); 440 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Full_BIT, 441 phydev->advertising); 442 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Half_BIT, 443 phydev->advertising); 444 445 /* Auto neg is not supported in fiber mode */ 446 bmcr = phy_read(phydev, MII_BMCR); 447 if (bmcr < 0) 448 return bmcr; 449 450 if (bmcr & BMCR_ANENABLE) { 451 err = phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0); 452 if (err < 0) 453 return err; 454 } 455 phydev->autoneg = AUTONEG_DISABLE; 456 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 457 phydev->supported); 458 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 459 phydev->advertising); 460 461 /* Setup fiber advertisement */ 462 err = phy_modify_changed(phydev, MII_ADVERTISE, 463 MII_DP83822_FIBER_ADVERTISE, 464 MII_DP83822_FIBER_ADVERTISE); 465 466 if (err < 0) 467 return err; 468 469 if (dp83822->fx_signal_det_low) { 470 err = phy_set_bits_mmd(phydev, DP83822_DEVADDR, 471 MII_DP83822_GENCFG, 472 DP83822_SIG_DET_LOW); 473 if (err) 474 return err; 475 } 476 } 477 return dp8382x_disable_wol(phydev); 478 } 479 480 static int dp8382x_config_init(struct phy_device *phydev) 481 { 482 return dp8382x_disable_wol(phydev); 483 } 484 485 static int dp83822_phy_reset(struct phy_device *phydev) 486 { 487 int err; 488 489 err = phy_write(phydev, MII_DP83822_RESET_CTRL, DP83822_SW_RESET); 490 if (err < 0) 491 return err; 492 493 return phydev->drv->config_init(phydev); 494 } 495 496 #ifdef CONFIG_OF_MDIO 497 static int dp83822_of_init(struct phy_device *phydev) 498 { 499 struct dp83822_private *dp83822 = phydev->priv; 500 struct device *dev = &phydev->mdio.dev; 501 502 /* Signal detection for the PHY is only enabled if the FX_EN and the 503 * SD_EN pins are strapped. Signal detection can only enabled if FX_EN 504 * is strapped otherwise signal detection is disabled for the PHY. 505 */ 506 if (dp83822->fx_enabled && dp83822->fx_sd_enable) 507 dp83822->fx_signal_det_low = device_property_present(dev, 508 "ti,link-loss-low"); 509 if (!dp83822->fx_enabled) 510 dp83822->fx_enabled = device_property_present(dev, 511 "ti,fiber-mode"); 512 513 return 0; 514 } 515 #else 516 static int dp83822_of_init(struct phy_device *phydev) 517 { 518 return 0; 519 } 520 #endif /* CONFIG_OF_MDIO */ 521 522 static int dp83822_read_straps(struct phy_device *phydev) 523 { 524 struct dp83822_private *dp83822 = phydev->priv; 525 int fx_enabled, fx_sd_enable; 526 int val; 527 528 val = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_SOR1); 529 if (val < 0) 530 return val; 531 532 phydev_dbg(phydev, "SOR1 strap register: 0x%04x\n", val); 533 534 fx_enabled = (val & DP83822_COL_STRAP_MASK) >> DP83822_COL_SHIFT; 535 if (fx_enabled == DP83822_STRAP_MODE2 || 536 fx_enabled == DP83822_STRAP_MODE3) 537 dp83822->fx_enabled = 1; 538 539 if (dp83822->fx_enabled) { 540 fx_sd_enable = (val & DP83822_RX_ER_STR_MASK) >> DP83822_RX_ER_SHIFT; 541 if (fx_sd_enable == DP83822_STRAP_MODE3 || 542 fx_sd_enable == DP83822_STRAP_MODE4) 543 dp83822->fx_sd_enable = 1; 544 } 545 546 return 0; 547 } 548 549 static int dp83822_probe(struct phy_device *phydev) 550 { 551 struct dp83822_private *dp83822; 552 int ret; 553 554 dp83822 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83822), 555 GFP_KERNEL); 556 if (!dp83822) 557 return -ENOMEM; 558 559 phydev->priv = dp83822; 560 561 ret = dp83822_read_straps(phydev); 562 if (ret) 563 return ret; 564 565 dp83822_of_init(phydev); 566 567 if (dp83822->fx_enabled) 568 phydev->port = PORT_FIBRE; 569 570 return 0; 571 } 572 573 static int dp83822_suspend(struct phy_device *phydev) 574 { 575 int value; 576 577 value = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG); 578 579 if (!(value & DP83822_WOL_EN)) 580 genphy_suspend(phydev); 581 582 return 0; 583 } 584 585 static int dp83822_resume(struct phy_device *phydev) 586 { 587 int value; 588 589 genphy_resume(phydev); 590 591 value = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG); 592 593 phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG, value | 594 DP83822_WOL_CLR_INDICATION); 595 596 return 0; 597 } 598 599 #define DP83822_PHY_DRIVER(_id, _name) \ 600 { \ 601 PHY_ID_MATCH_MODEL(_id), \ 602 .name = (_name), \ 603 /* PHY_BASIC_FEATURES */ \ 604 .probe = dp83822_probe, \ 605 .soft_reset = dp83822_phy_reset, \ 606 .config_init = dp83822_config_init, \ 607 .read_status = dp83822_read_status, \ 608 .get_wol = dp83822_get_wol, \ 609 .set_wol = dp83822_set_wol, \ 610 .config_intr = dp83822_config_intr, \ 611 .handle_interrupt = dp83822_handle_interrupt, \ 612 .suspend = dp83822_suspend, \ 613 .resume = dp83822_resume, \ 614 } 615 616 #define DP8382X_PHY_DRIVER(_id, _name) \ 617 { \ 618 PHY_ID_MATCH_MODEL(_id), \ 619 .name = (_name), \ 620 /* PHY_BASIC_FEATURES */ \ 621 .soft_reset = dp83822_phy_reset, \ 622 .config_init = dp8382x_config_init, \ 623 .get_wol = dp83822_get_wol, \ 624 .set_wol = dp83822_set_wol, \ 625 .config_intr = dp83822_config_intr, \ 626 .handle_interrupt = dp83822_handle_interrupt, \ 627 .suspend = dp83822_suspend, \ 628 .resume = dp83822_resume, \ 629 } 630 631 static struct phy_driver dp83822_driver[] = { 632 DP83822_PHY_DRIVER(DP83822_PHY_ID, "TI DP83822"), 633 DP8382X_PHY_DRIVER(DP83825I_PHY_ID, "TI DP83825I"), 634 DP8382X_PHY_DRIVER(DP83826C_PHY_ID, "TI DP83826C"), 635 DP8382X_PHY_DRIVER(DP83826NC_PHY_ID, "TI DP83826NC"), 636 DP8382X_PHY_DRIVER(DP83825S_PHY_ID, "TI DP83825S"), 637 DP8382X_PHY_DRIVER(DP83825CM_PHY_ID, "TI DP83825M"), 638 DP8382X_PHY_DRIVER(DP83825CS_PHY_ID, "TI DP83825CS"), 639 }; 640 module_phy_driver(dp83822_driver); 641 642 static struct mdio_device_id __maybe_unused dp83822_tbl[] = { 643 { DP83822_PHY_ID, 0xfffffff0 }, 644 { DP83825I_PHY_ID, 0xfffffff0 }, 645 { DP83826C_PHY_ID, 0xfffffff0 }, 646 { DP83826NC_PHY_ID, 0xfffffff0 }, 647 { DP83825S_PHY_ID, 0xfffffff0 }, 648 { DP83825CM_PHY_ID, 0xfffffff0 }, 649 { DP83825CS_PHY_ID, 0xfffffff0 }, 650 { }, 651 }; 652 MODULE_DEVICE_TABLE(mdio, dp83822_tbl); 653 654 MODULE_DESCRIPTION("Texas Instruments DP83822 PHY driver"); 655 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com"); 656 MODULE_LICENSE("GPL v2"); 657