1 // SPDX-License-Identifier: GPL-2.0 2 /* Driver for the Texas Instruments DP83822, DP83825 and DP83826 PHYs. 3 * 4 * Copyright (C) 2017 Texas Instruments Inc. 5 */ 6 7 #include <linux/ethtool.h> 8 #include <linux/etherdevice.h> 9 #include <linux/kernel.h> 10 #include <linux/mii.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/phy.h> 14 #include <linux/netdevice.h> 15 16 #define DP83822_PHY_ID 0x2000a240 17 #define DP83825S_PHY_ID 0x2000a140 18 #define DP83825I_PHY_ID 0x2000a150 19 #define DP83825CM_PHY_ID 0x2000a160 20 #define DP83825CS_PHY_ID 0x2000a170 21 #define DP83826C_PHY_ID 0x2000a130 22 #define DP83826NC_PHY_ID 0x2000a110 23 24 #define DP83822_DEVADDR 0x1f 25 26 #define MII_DP83822_CTRL_2 0x0a 27 #define MII_DP83822_PHYSTS 0x10 28 #define MII_DP83822_PHYSCR 0x11 29 #define MII_DP83822_MISR1 0x12 30 #define MII_DP83822_MISR2 0x13 31 #define MII_DP83822_FCSCR 0x14 32 #define MII_DP83822_RCSR 0x17 33 #define MII_DP83822_RESET_CTRL 0x1f 34 #define MII_DP83822_GENCFG 0x465 35 #define MII_DP83822_SOR1 0x467 36 37 /* GENCFG */ 38 #define DP83822_SIG_DET_LOW BIT(0) 39 40 /* Control Register 2 bits */ 41 #define DP83822_FX_ENABLE BIT(14) 42 43 #define DP83822_HW_RESET BIT(15) 44 #define DP83822_SW_RESET BIT(14) 45 46 /* PHY STS bits */ 47 #define DP83822_PHYSTS_DUPLEX BIT(2) 48 #define DP83822_PHYSTS_10 BIT(1) 49 #define DP83822_PHYSTS_LINK BIT(0) 50 51 /* PHYSCR Register Fields */ 52 #define DP83822_PHYSCR_INT_OE BIT(0) /* Interrupt Output Enable */ 53 #define DP83822_PHYSCR_INTEN BIT(1) /* Interrupt Enable */ 54 55 /* MISR1 bits */ 56 #define DP83822_RX_ERR_HF_INT_EN BIT(0) 57 #define DP83822_FALSE_CARRIER_HF_INT_EN BIT(1) 58 #define DP83822_ANEG_COMPLETE_INT_EN BIT(2) 59 #define DP83822_DUP_MODE_CHANGE_INT_EN BIT(3) 60 #define DP83822_SPEED_CHANGED_INT_EN BIT(4) 61 #define DP83822_LINK_STAT_INT_EN BIT(5) 62 #define DP83822_ENERGY_DET_INT_EN BIT(6) 63 #define DP83822_LINK_QUAL_INT_EN BIT(7) 64 65 /* MISR2 bits */ 66 #define DP83822_JABBER_DET_INT_EN BIT(0) 67 #define DP83822_WOL_PKT_INT_EN BIT(1) 68 #define DP83822_SLEEP_MODE_INT_EN BIT(2) 69 #define DP83822_MDI_XOVER_INT_EN BIT(3) 70 #define DP83822_LB_FIFO_INT_EN BIT(4) 71 #define DP83822_PAGE_RX_INT_EN BIT(5) 72 #define DP83822_ANEG_ERR_INT_EN BIT(6) 73 #define DP83822_EEE_ERROR_CHANGE_INT_EN BIT(7) 74 75 /* INT_STAT1 bits */ 76 #define DP83822_WOL_INT_EN BIT(4) 77 #define DP83822_WOL_INT_STAT BIT(12) 78 79 #define MII_DP83822_RXSOP1 0x04a5 80 #define MII_DP83822_RXSOP2 0x04a6 81 #define MII_DP83822_RXSOP3 0x04a7 82 83 /* WoL Registers */ 84 #define MII_DP83822_WOL_CFG 0x04a0 85 #define MII_DP83822_WOL_STAT 0x04a1 86 #define MII_DP83822_WOL_DA1 0x04a2 87 #define MII_DP83822_WOL_DA2 0x04a3 88 #define MII_DP83822_WOL_DA3 0x04a4 89 90 /* WoL bits */ 91 #define DP83822_WOL_MAGIC_EN BIT(0) 92 #define DP83822_WOL_SECURE_ON BIT(5) 93 #define DP83822_WOL_EN BIT(7) 94 #define DP83822_WOL_INDICATION_SEL BIT(8) 95 #define DP83822_WOL_CLR_INDICATION BIT(11) 96 97 /* RSCR bits */ 98 #define DP83822_RX_CLK_SHIFT BIT(12) 99 #define DP83822_TX_CLK_SHIFT BIT(11) 100 101 /* SOR1 mode */ 102 #define DP83822_STRAP_MODE1 0 103 #define DP83822_STRAP_MODE2 BIT(0) 104 #define DP83822_STRAP_MODE3 BIT(1) 105 #define DP83822_STRAP_MODE4 GENMASK(1, 0) 106 107 #define DP83822_COL_STRAP_MASK GENMASK(11, 10) 108 #define DP83822_COL_SHIFT 10 109 #define DP83822_RX_ER_STR_MASK GENMASK(9, 8) 110 #define DP83822_RX_ER_SHIFT 8 111 112 #define MII_DP83822_FIBER_ADVERTISE (ADVERTISED_TP | ADVERTISED_MII | \ 113 ADVERTISED_FIBRE | \ 114 ADVERTISED_Pause | ADVERTISED_Asym_Pause) 115 116 struct dp83822_private { 117 bool fx_signal_det_low; 118 int fx_enabled; 119 u16 fx_sd_enable; 120 }; 121 122 static int dp83822_ack_interrupt(struct phy_device *phydev) 123 { 124 int err; 125 126 err = phy_read(phydev, MII_DP83822_MISR1); 127 if (err < 0) 128 return err; 129 130 err = phy_read(phydev, MII_DP83822_MISR2); 131 if (err < 0) 132 return err; 133 134 return 0; 135 } 136 137 static int dp83822_set_wol(struct phy_device *phydev, 138 struct ethtool_wolinfo *wol) 139 { 140 struct net_device *ndev = phydev->attached_dev; 141 u16 value; 142 const u8 *mac; 143 144 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE)) { 145 mac = (const u8 *)ndev->dev_addr; 146 147 if (!is_valid_ether_addr(mac)) 148 return -EINVAL; 149 150 /* MAC addresses start with byte 5, but stored in mac[0]. 151 * 822 PHYs store bytes 4|5, 2|3, 0|1 152 */ 153 phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA1, 154 (mac[1] << 8) | mac[0]); 155 phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA2, 156 (mac[3] << 8) | mac[2]); 157 phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA3, 158 (mac[5] << 8) | mac[4]); 159 160 value = phy_read_mmd(phydev, DP83822_DEVADDR, 161 MII_DP83822_WOL_CFG); 162 if (wol->wolopts & WAKE_MAGIC) 163 value |= DP83822_WOL_MAGIC_EN; 164 else 165 value &= ~DP83822_WOL_MAGIC_EN; 166 167 if (wol->wolopts & WAKE_MAGICSECURE) { 168 phy_write_mmd(phydev, DP83822_DEVADDR, 169 MII_DP83822_RXSOP1, 170 (wol->sopass[1] << 8) | wol->sopass[0]); 171 phy_write_mmd(phydev, DP83822_DEVADDR, 172 MII_DP83822_RXSOP2, 173 (wol->sopass[3] << 8) | wol->sopass[2]); 174 phy_write_mmd(phydev, DP83822_DEVADDR, 175 MII_DP83822_RXSOP3, 176 (wol->sopass[5] << 8) | wol->sopass[4]); 177 value |= DP83822_WOL_SECURE_ON; 178 } else { 179 value &= ~DP83822_WOL_SECURE_ON; 180 } 181 182 /* Clear any pending WoL interrupt */ 183 phy_read(phydev, MII_DP83822_MISR2); 184 185 value |= DP83822_WOL_EN | DP83822_WOL_INDICATION_SEL | 186 DP83822_WOL_CLR_INDICATION; 187 188 return phy_write_mmd(phydev, DP83822_DEVADDR, 189 MII_DP83822_WOL_CFG, value); 190 } else { 191 return phy_clear_bits_mmd(phydev, DP83822_DEVADDR, 192 MII_DP83822_WOL_CFG, DP83822_WOL_EN); 193 } 194 } 195 196 static void dp83822_get_wol(struct phy_device *phydev, 197 struct ethtool_wolinfo *wol) 198 { 199 int value; 200 u16 sopass_val; 201 202 wol->supported = (WAKE_MAGIC | WAKE_MAGICSECURE); 203 wol->wolopts = 0; 204 205 value = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG); 206 207 if (value & DP83822_WOL_MAGIC_EN) 208 wol->wolopts |= WAKE_MAGIC; 209 210 if (value & DP83822_WOL_SECURE_ON) { 211 sopass_val = phy_read_mmd(phydev, DP83822_DEVADDR, 212 MII_DP83822_RXSOP1); 213 wol->sopass[0] = (sopass_val & 0xff); 214 wol->sopass[1] = (sopass_val >> 8); 215 216 sopass_val = phy_read_mmd(phydev, DP83822_DEVADDR, 217 MII_DP83822_RXSOP2); 218 wol->sopass[2] = (sopass_val & 0xff); 219 wol->sopass[3] = (sopass_val >> 8); 220 221 sopass_val = phy_read_mmd(phydev, DP83822_DEVADDR, 222 MII_DP83822_RXSOP3); 223 wol->sopass[4] = (sopass_val & 0xff); 224 wol->sopass[5] = (sopass_val >> 8); 225 226 wol->wolopts |= WAKE_MAGICSECURE; 227 } 228 229 /* WoL is not enabled so set wolopts to 0 */ 230 if (!(value & DP83822_WOL_EN)) 231 wol->wolopts = 0; 232 } 233 234 static int dp83822_config_intr(struct phy_device *phydev) 235 { 236 struct dp83822_private *dp83822 = phydev->priv; 237 int misr_status; 238 int physcr_status; 239 int err; 240 241 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 242 misr_status = phy_read(phydev, MII_DP83822_MISR1); 243 if (misr_status < 0) 244 return misr_status; 245 246 misr_status |= (DP83822_RX_ERR_HF_INT_EN | 247 DP83822_FALSE_CARRIER_HF_INT_EN | 248 DP83822_LINK_STAT_INT_EN | 249 DP83822_ENERGY_DET_INT_EN | 250 DP83822_LINK_QUAL_INT_EN); 251 252 if (!dp83822->fx_enabled) 253 misr_status |= DP83822_ANEG_COMPLETE_INT_EN | 254 DP83822_DUP_MODE_CHANGE_INT_EN | 255 DP83822_SPEED_CHANGED_INT_EN; 256 257 258 err = phy_write(phydev, MII_DP83822_MISR1, misr_status); 259 if (err < 0) 260 return err; 261 262 misr_status = phy_read(phydev, MII_DP83822_MISR2); 263 if (misr_status < 0) 264 return misr_status; 265 266 misr_status |= (DP83822_JABBER_DET_INT_EN | 267 DP83822_SLEEP_MODE_INT_EN | 268 DP83822_LB_FIFO_INT_EN | 269 DP83822_PAGE_RX_INT_EN | 270 DP83822_EEE_ERROR_CHANGE_INT_EN); 271 272 if (!dp83822->fx_enabled) 273 misr_status |= DP83822_MDI_XOVER_INT_EN | 274 DP83822_ANEG_ERR_INT_EN | 275 DP83822_WOL_PKT_INT_EN; 276 277 err = phy_write(phydev, MII_DP83822_MISR2, misr_status); 278 if (err < 0) 279 return err; 280 281 physcr_status = phy_read(phydev, MII_DP83822_PHYSCR); 282 if (physcr_status < 0) 283 return physcr_status; 284 285 physcr_status |= DP83822_PHYSCR_INT_OE | DP83822_PHYSCR_INTEN; 286 287 } else { 288 err = phy_write(phydev, MII_DP83822_MISR1, 0); 289 if (err < 0) 290 return err; 291 292 err = phy_write(phydev, MII_DP83822_MISR1, 0); 293 if (err < 0) 294 return err; 295 296 physcr_status = phy_read(phydev, MII_DP83822_PHYSCR); 297 if (physcr_status < 0) 298 return physcr_status; 299 300 physcr_status &= ~DP83822_PHYSCR_INTEN; 301 } 302 303 return phy_write(phydev, MII_DP83822_PHYSCR, physcr_status); 304 } 305 306 static int dp8382x_disable_wol(struct phy_device *phydev) 307 { 308 int value = DP83822_WOL_EN | DP83822_WOL_MAGIC_EN | 309 DP83822_WOL_SECURE_ON; 310 311 return phy_clear_bits_mmd(phydev, DP83822_DEVADDR, 312 MII_DP83822_WOL_CFG, value); 313 } 314 315 static int dp83822_read_status(struct phy_device *phydev) 316 { 317 struct dp83822_private *dp83822 = phydev->priv; 318 int status = phy_read(phydev, MII_DP83822_PHYSTS); 319 int ctrl2; 320 int ret; 321 322 if (dp83822->fx_enabled) { 323 if (status & DP83822_PHYSTS_LINK) { 324 phydev->speed = SPEED_UNKNOWN; 325 phydev->duplex = DUPLEX_UNKNOWN; 326 } else { 327 ctrl2 = phy_read(phydev, MII_DP83822_CTRL_2); 328 if (ctrl2 < 0) 329 return ctrl2; 330 331 if (!(ctrl2 & DP83822_FX_ENABLE)) { 332 ret = phy_write(phydev, MII_DP83822_CTRL_2, 333 DP83822_FX_ENABLE | ctrl2); 334 if (ret < 0) 335 return ret; 336 } 337 } 338 } 339 340 ret = genphy_read_status(phydev); 341 if (ret) 342 return ret; 343 344 if (status < 0) 345 return status; 346 347 if (status & DP83822_PHYSTS_DUPLEX) 348 phydev->duplex = DUPLEX_FULL; 349 else 350 phydev->duplex = DUPLEX_HALF; 351 352 if (status & DP83822_PHYSTS_10) 353 phydev->speed = SPEED_10; 354 else 355 phydev->speed = SPEED_100; 356 357 return 0; 358 } 359 360 static int dp83822_config_init(struct phy_device *phydev) 361 { 362 struct dp83822_private *dp83822 = phydev->priv; 363 struct device *dev = &phydev->mdio.dev; 364 int rgmii_delay; 365 s32 rx_int_delay; 366 s32 tx_int_delay; 367 int err = 0; 368 int bmcr; 369 370 if (phy_interface_is_rgmii(phydev)) { 371 rx_int_delay = phy_get_internal_delay(phydev, dev, NULL, 0, 372 true); 373 374 if (rx_int_delay <= 0) 375 rgmii_delay = 0; 376 else 377 rgmii_delay = DP83822_RX_CLK_SHIFT; 378 379 tx_int_delay = phy_get_internal_delay(phydev, dev, NULL, 0, 380 false); 381 if (tx_int_delay <= 0) 382 rgmii_delay &= ~DP83822_TX_CLK_SHIFT; 383 else 384 rgmii_delay |= DP83822_TX_CLK_SHIFT; 385 386 if (rgmii_delay) { 387 err = phy_set_bits_mmd(phydev, DP83822_DEVADDR, 388 MII_DP83822_RCSR, rgmii_delay); 389 if (err) 390 return err; 391 } 392 } 393 394 if (dp83822->fx_enabled) { 395 err = phy_modify(phydev, MII_DP83822_CTRL_2, 396 DP83822_FX_ENABLE, 1); 397 if (err < 0) 398 return err; 399 400 /* Only allow advertising what this PHY supports */ 401 linkmode_and(phydev->advertising, phydev->advertising, 402 phydev->supported); 403 404 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, 405 phydev->supported); 406 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, 407 phydev->advertising); 408 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Full_BIT, 409 phydev->supported); 410 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Half_BIT, 411 phydev->supported); 412 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Full_BIT, 413 phydev->advertising); 414 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Half_BIT, 415 phydev->advertising); 416 417 /* Auto neg is not supported in fiber mode */ 418 bmcr = phy_read(phydev, MII_BMCR); 419 if (bmcr < 0) 420 return bmcr; 421 422 if (bmcr & BMCR_ANENABLE) { 423 err = phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0); 424 if (err < 0) 425 return err; 426 } 427 phydev->autoneg = AUTONEG_DISABLE; 428 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 429 phydev->supported); 430 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 431 phydev->advertising); 432 433 /* Setup fiber advertisement */ 434 err = phy_modify_changed(phydev, MII_ADVERTISE, 435 MII_DP83822_FIBER_ADVERTISE, 436 MII_DP83822_FIBER_ADVERTISE); 437 438 if (err < 0) 439 return err; 440 441 if (dp83822->fx_signal_det_low) { 442 err = phy_set_bits_mmd(phydev, DP83822_DEVADDR, 443 MII_DP83822_GENCFG, 444 DP83822_SIG_DET_LOW); 445 if (err) 446 return err; 447 } 448 } 449 return dp8382x_disable_wol(phydev); 450 } 451 452 static int dp8382x_config_init(struct phy_device *phydev) 453 { 454 return dp8382x_disable_wol(phydev); 455 } 456 457 static int dp83822_phy_reset(struct phy_device *phydev) 458 { 459 int err; 460 461 err = phy_write(phydev, MII_DP83822_RESET_CTRL, DP83822_SW_RESET); 462 if (err < 0) 463 return err; 464 465 return phydev->drv->config_init(phydev); 466 } 467 468 #ifdef CONFIG_OF_MDIO 469 static int dp83822_of_init(struct phy_device *phydev) 470 { 471 struct dp83822_private *dp83822 = phydev->priv; 472 struct device *dev = &phydev->mdio.dev; 473 474 /* Signal detection for the PHY is only enabled if the FX_EN and the 475 * SD_EN pins are strapped. Signal detection can only enabled if FX_EN 476 * is strapped otherwise signal detection is disabled for the PHY. 477 */ 478 if (dp83822->fx_enabled && dp83822->fx_sd_enable) 479 dp83822->fx_signal_det_low = device_property_present(dev, 480 "ti,link-loss-low"); 481 if (!dp83822->fx_enabled) 482 dp83822->fx_enabled = device_property_present(dev, 483 "ti,fiber-mode"); 484 485 return 0; 486 } 487 #else 488 static int dp83822_of_init(struct phy_device *phydev) 489 { 490 return 0; 491 } 492 #endif /* CONFIG_OF_MDIO */ 493 494 static int dp83822_read_straps(struct phy_device *phydev) 495 { 496 struct dp83822_private *dp83822 = phydev->priv; 497 int fx_enabled, fx_sd_enable; 498 int val; 499 500 val = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_SOR1); 501 if (val < 0) 502 return val; 503 504 fx_enabled = (val & DP83822_COL_STRAP_MASK) >> DP83822_COL_SHIFT; 505 if (fx_enabled == DP83822_STRAP_MODE2 || 506 fx_enabled == DP83822_STRAP_MODE3) 507 dp83822->fx_enabled = 1; 508 509 if (dp83822->fx_enabled) { 510 fx_sd_enable = (val & DP83822_RX_ER_STR_MASK) >> DP83822_RX_ER_SHIFT; 511 if (fx_sd_enable == DP83822_STRAP_MODE3 || 512 fx_sd_enable == DP83822_STRAP_MODE4) 513 dp83822->fx_sd_enable = 1; 514 } 515 516 return 0; 517 } 518 519 static int dp83822_probe(struct phy_device *phydev) 520 { 521 struct dp83822_private *dp83822; 522 int ret; 523 524 dp83822 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83822), 525 GFP_KERNEL); 526 if (!dp83822) 527 return -ENOMEM; 528 529 phydev->priv = dp83822; 530 531 ret = dp83822_read_straps(phydev); 532 if (ret) 533 return ret; 534 535 dp83822_of_init(phydev); 536 537 return 0; 538 } 539 540 static int dp83822_suspend(struct phy_device *phydev) 541 { 542 int value; 543 544 value = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG); 545 546 if (!(value & DP83822_WOL_EN)) 547 genphy_suspend(phydev); 548 549 return 0; 550 } 551 552 static int dp83822_resume(struct phy_device *phydev) 553 { 554 int value; 555 556 genphy_resume(phydev); 557 558 value = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG); 559 560 phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG, value | 561 DP83822_WOL_CLR_INDICATION); 562 563 return 0; 564 } 565 566 #define DP83822_PHY_DRIVER(_id, _name) \ 567 { \ 568 PHY_ID_MATCH_MODEL(_id), \ 569 .name = (_name), \ 570 /* PHY_BASIC_FEATURES */ \ 571 .probe = dp83822_probe, \ 572 .soft_reset = dp83822_phy_reset, \ 573 .config_init = dp83822_config_init, \ 574 .read_status = dp83822_read_status, \ 575 .get_wol = dp83822_get_wol, \ 576 .set_wol = dp83822_set_wol, \ 577 .ack_interrupt = dp83822_ack_interrupt, \ 578 .config_intr = dp83822_config_intr, \ 579 .suspend = dp83822_suspend, \ 580 .resume = dp83822_resume, \ 581 } 582 583 #define DP8382X_PHY_DRIVER(_id, _name) \ 584 { \ 585 PHY_ID_MATCH_MODEL(_id), \ 586 .name = (_name), \ 587 /* PHY_BASIC_FEATURES */ \ 588 .soft_reset = dp83822_phy_reset, \ 589 .config_init = dp8382x_config_init, \ 590 .get_wol = dp83822_get_wol, \ 591 .set_wol = dp83822_set_wol, \ 592 .ack_interrupt = dp83822_ack_interrupt, \ 593 .config_intr = dp83822_config_intr, \ 594 .suspend = dp83822_suspend, \ 595 .resume = dp83822_resume, \ 596 } 597 598 static struct phy_driver dp83822_driver[] = { 599 DP83822_PHY_DRIVER(DP83822_PHY_ID, "TI DP83822"), 600 DP8382X_PHY_DRIVER(DP83825I_PHY_ID, "TI DP83825I"), 601 DP8382X_PHY_DRIVER(DP83826C_PHY_ID, "TI DP83826C"), 602 DP8382X_PHY_DRIVER(DP83826NC_PHY_ID, "TI DP83826NC"), 603 DP8382X_PHY_DRIVER(DP83825S_PHY_ID, "TI DP83825S"), 604 DP8382X_PHY_DRIVER(DP83825CM_PHY_ID, "TI DP83825M"), 605 DP8382X_PHY_DRIVER(DP83825CS_PHY_ID, "TI DP83825CS"), 606 }; 607 module_phy_driver(dp83822_driver); 608 609 static struct mdio_device_id __maybe_unused dp83822_tbl[] = { 610 { DP83822_PHY_ID, 0xfffffff0 }, 611 { DP83825I_PHY_ID, 0xfffffff0 }, 612 { DP83826C_PHY_ID, 0xfffffff0 }, 613 { DP83826NC_PHY_ID, 0xfffffff0 }, 614 { DP83825S_PHY_ID, 0xfffffff0 }, 615 { DP83825CM_PHY_ID, 0xfffffff0 }, 616 { DP83825CS_PHY_ID, 0xfffffff0 }, 617 { }, 618 }; 619 MODULE_DEVICE_TABLE(mdio, dp83822_tbl); 620 621 MODULE_DESCRIPTION("Texas Instruments DP83822 PHY driver"); 622 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com"); 623 MODULE_LICENSE("GPL v2"); 624