1 /* 2 * Driver for the National Semiconductor DP83640 PHYTER 3 * 4 * Copyright (C) 2010 OMICRON electronics GmbH 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 19 */ 20 21 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 22 23 #include <linux/ethtool.h> 24 #include <linux/kernel.h> 25 #include <linux/list.h> 26 #include <linux/mii.h> 27 #include <linux/module.h> 28 #include <linux/net_tstamp.h> 29 #include <linux/netdevice.h> 30 #include <linux/phy.h> 31 #include <linux/ptp_classify.h> 32 #include <linux/ptp_clock_kernel.h> 33 34 #include "dp83640_reg.h" 35 36 #define DP83640_PHY_ID 0x20005ce1 37 #define PAGESEL 0x13 38 #define LAYER4 0x02 39 #define LAYER2 0x01 40 #define MAX_RXTS 64 41 #define N_EXT_TS 6 42 #define PSF_PTPVER 2 43 #define PSF_EVNT 0x4000 44 #define PSF_RX 0x2000 45 #define PSF_TX 0x1000 46 #define EXT_EVENT 1 47 #define CAL_EVENT 7 48 #define CAL_TRIGGER 7 49 #define PER_TRIGGER 6 50 51 #define MII_DP83640_MICR 0x11 52 #define MII_DP83640_MISR 0x12 53 54 #define MII_DP83640_MICR_OE 0x1 55 #define MII_DP83640_MICR_IE 0x2 56 57 #define MII_DP83640_MISR_RHF_INT_EN 0x01 58 #define MII_DP83640_MISR_FHF_INT_EN 0x02 59 #define MII_DP83640_MISR_ANC_INT_EN 0x04 60 #define MII_DP83640_MISR_DUP_INT_EN 0x08 61 #define MII_DP83640_MISR_SPD_INT_EN 0x10 62 #define MII_DP83640_MISR_LINK_INT_EN 0x20 63 #define MII_DP83640_MISR_ED_INT_EN 0x40 64 #define MII_DP83640_MISR_LQ_INT_EN 0x80 65 66 /* phyter seems to miss the mark by 16 ns */ 67 #define ADJTIME_FIX 16 68 69 #if defined(__BIG_ENDIAN) 70 #define ENDIAN_FLAG 0 71 #elif defined(__LITTLE_ENDIAN) 72 #define ENDIAN_FLAG PSF_ENDIAN 73 #endif 74 75 #define SKB_PTP_TYPE(__skb) (*(unsigned int *)((__skb)->cb)) 76 77 struct phy_rxts { 78 u16 ns_lo; /* ns[15:0] */ 79 u16 ns_hi; /* overflow[1:0], ns[29:16] */ 80 u16 sec_lo; /* sec[15:0] */ 81 u16 sec_hi; /* sec[31:16] */ 82 u16 seqid; /* sequenceId[15:0] */ 83 u16 msgtype; /* messageType[3:0], hash[11:0] */ 84 }; 85 86 struct phy_txts { 87 u16 ns_lo; /* ns[15:0] */ 88 u16 ns_hi; /* overflow[1:0], ns[29:16] */ 89 u16 sec_lo; /* sec[15:0] */ 90 u16 sec_hi; /* sec[31:16] */ 91 }; 92 93 struct rxts { 94 struct list_head list; 95 unsigned long tmo; 96 u64 ns; 97 u16 seqid; 98 u8 msgtype; 99 u16 hash; 100 }; 101 102 struct dp83640_clock; 103 104 struct dp83640_private { 105 struct list_head list; 106 struct dp83640_clock *clock; 107 struct phy_device *phydev; 108 struct work_struct ts_work; 109 int hwts_tx_en; 110 int hwts_rx_en; 111 int layer; 112 int version; 113 /* remember state of cfg0 during calibration */ 114 int cfg0; 115 /* remember the last event time stamp */ 116 struct phy_txts edata; 117 /* list of rx timestamps */ 118 struct list_head rxts; 119 struct list_head rxpool; 120 struct rxts rx_pool_data[MAX_RXTS]; 121 /* protects above three fields from concurrent access */ 122 spinlock_t rx_lock; 123 /* queues of incoming and outgoing packets */ 124 struct sk_buff_head rx_queue; 125 struct sk_buff_head tx_queue; 126 }; 127 128 struct dp83640_clock { 129 /* keeps the instance in the 'phyter_clocks' list */ 130 struct list_head list; 131 /* we create one clock instance per MII bus */ 132 struct mii_bus *bus; 133 /* protects extended registers from concurrent access */ 134 struct mutex extreg_lock; 135 /* remembers which page was last selected */ 136 int page; 137 /* our advertised capabilities */ 138 struct ptp_clock_info caps; 139 /* protects the three fields below from concurrent access */ 140 struct mutex clock_lock; 141 /* the one phyter from which we shall read */ 142 struct dp83640_private *chosen; 143 /* list of the other attached phyters, not chosen */ 144 struct list_head phylist; 145 /* reference to our PTP hardware clock */ 146 struct ptp_clock *ptp_clock; 147 }; 148 149 /* globals */ 150 151 enum { 152 CALIBRATE_GPIO, 153 PEROUT_GPIO, 154 EXTTS0_GPIO, 155 EXTTS1_GPIO, 156 EXTTS2_GPIO, 157 EXTTS3_GPIO, 158 EXTTS4_GPIO, 159 EXTTS5_GPIO, 160 GPIO_TABLE_SIZE 161 }; 162 163 static int chosen_phy = -1; 164 static ushort gpio_tab[GPIO_TABLE_SIZE] = { 165 1, 2, 3, 4, 8, 9, 10, 11 166 }; 167 168 module_param(chosen_phy, int, 0444); 169 module_param_array(gpio_tab, ushort, NULL, 0444); 170 171 MODULE_PARM_DESC(chosen_phy, \ 172 "The address of the PHY to use for the ancillary clock features"); 173 MODULE_PARM_DESC(gpio_tab, \ 174 "Which GPIO line to use for which purpose: cal,perout,extts1,...,extts6"); 175 176 /* a list of clocks and a mutex to protect it */ 177 static LIST_HEAD(phyter_clocks); 178 static DEFINE_MUTEX(phyter_clocks_lock); 179 180 static void rx_timestamp_work(struct work_struct *work); 181 182 /* extended register access functions */ 183 184 #define BROADCAST_ADDR 31 185 186 static inline int broadcast_write(struct mii_bus *bus, u32 regnum, u16 val) 187 { 188 return mdiobus_write(bus, BROADCAST_ADDR, regnum, val); 189 } 190 191 /* Caller must hold extreg_lock. */ 192 static int ext_read(struct phy_device *phydev, int page, u32 regnum) 193 { 194 struct dp83640_private *dp83640 = phydev->priv; 195 int val; 196 197 if (dp83640->clock->page != page) { 198 broadcast_write(phydev->bus, PAGESEL, page); 199 dp83640->clock->page = page; 200 } 201 val = phy_read(phydev, regnum); 202 203 return val; 204 } 205 206 /* Caller must hold extreg_lock. */ 207 static void ext_write(int broadcast, struct phy_device *phydev, 208 int page, u32 regnum, u16 val) 209 { 210 struct dp83640_private *dp83640 = phydev->priv; 211 212 if (dp83640->clock->page != page) { 213 broadcast_write(phydev->bus, PAGESEL, page); 214 dp83640->clock->page = page; 215 } 216 if (broadcast) 217 broadcast_write(phydev->bus, regnum, val); 218 else 219 phy_write(phydev, regnum, val); 220 } 221 222 /* Caller must hold extreg_lock. */ 223 static int tdr_write(int bc, struct phy_device *dev, 224 const struct timespec *ts, u16 cmd) 225 { 226 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec & 0xffff);/* ns[15:0] */ 227 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec >> 16); /* ns[31:16] */ 228 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec & 0xffff); /* sec[15:0] */ 229 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec >> 16); /* sec[31:16]*/ 230 231 ext_write(bc, dev, PAGE4, PTP_CTL, cmd); 232 233 return 0; 234 } 235 236 /* convert phy timestamps into driver timestamps */ 237 238 static void phy2rxts(struct phy_rxts *p, struct rxts *rxts) 239 { 240 u32 sec; 241 242 sec = p->sec_lo; 243 sec |= p->sec_hi << 16; 244 245 rxts->ns = p->ns_lo; 246 rxts->ns |= (p->ns_hi & 0x3fff) << 16; 247 rxts->ns += ((u64)sec) * 1000000000ULL; 248 rxts->seqid = p->seqid; 249 rxts->msgtype = (p->msgtype >> 12) & 0xf; 250 rxts->hash = p->msgtype & 0x0fff; 251 rxts->tmo = jiffies + 2; 252 } 253 254 static u64 phy2txts(struct phy_txts *p) 255 { 256 u64 ns; 257 u32 sec; 258 259 sec = p->sec_lo; 260 sec |= p->sec_hi << 16; 261 262 ns = p->ns_lo; 263 ns |= (p->ns_hi & 0x3fff) << 16; 264 ns += ((u64)sec) * 1000000000ULL; 265 266 return ns; 267 } 268 269 static void periodic_output(struct dp83640_clock *clock, 270 struct ptp_clock_request *clkreq, bool on) 271 { 272 struct dp83640_private *dp83640 = clock->chosen; 273 struct phy_device *phydev = dp83640->phydev; 274 u32 sec, nsec, period; 275 u16 gpio, ptp_trig, trigger, val; 276 277 gpio = on ? gpio_tab[PEROUT_GPIO] : 0; 278 trigger = PER_TRIGGER; 279 280 ptp_trig = TRIG_WR | 281 (trigger & TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT | 282 (gpio & TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT | 283 TRIG_PER | 284 TRIG_PULSE; 285 286 val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT; 287 288 if (!on) { 289 val |= TRIG_DIS; 290 mutex_lock(&clock->extreg_lock); 291 ext_write(0, phydev, PAGE5, PTP_TRIG, ptp_trig); 292 ext_write(0, phydev, PAGE4, PTP_CTL, val); 293 mutex_unlock(&clock->extreg_lock); 294 return; 295 } 296 297 sec = clkreq->perout.start.sec; 298 nsec = clkreq->perout.start.nsec; 299 period = clkreq->perout.period.sec * 1000000000UL; 300 period += clkreq->perout.period.nsec; 301 302 mutex_lock(&clock->extreg_lock); 303 304 ext_write(0, phydev, PAGE5, PTP_TRIG, ptp_trig); 305 306 /*load trigger*/ 307 val |= TRIG_LOAD; 308 ext_write(0, phydev, PAGE4, PTP_CTL, val); 309 ext_write(0, phydev, PAGE4, PTP_TDR, nsec & 0xffff); /* ns[15:0] */ 310 ext_write(0, phydev, PAGE4, PTP_TDR, nsec >> 16); /* ns[31:16] */ 311 ext_write(0, phydev, PAGE4, PTP_TDR, sec & 0xffff); /* sec[15:0] */ 312 ext_write(0, phydev, PAGE4, PTP_TDR, sec >> 16); /* sec[31:16] */ 313 ext_write(0, phydev, PAGE4, PTP_TDR, period & 0xffff); /* ns[15:0] */ 314 ext_write(0, phydev, PAGE4, PTP_TDR, period >> 16); /* ns[31:16] */ 315 316 /*enable trigger*/ 317 val &= ~TRIG_LOAD; 318 val |= TRIG_EN; 319 ext_write(0, phydev, PAGE4, PTP_CTL, val); 320 321 mutex_unlock(&clock->extreg_lock); 322 } 323 324 /* ptp clock methods */ 325 326 static int ptp_dp83640_adjfreq(struct ptp_clock_info *ptp, s32 ppb) 327 { 328 struct dp83640_clock *clock = 329 container_of(ptp, struct dp83640_clock, caps); 330 struct phy_device *phydev = clock->chosen->phydev; 331 u64 rate; 332 int neg_adj = 0; 333 u16 hi, lo; 334 335 if (ppb < 0) { 336 neg_adj = 1; 337 ppb = -ppb; 338 } 339 rate = ppb; 340 rate <<= 26; 341 rate = div_u64(rate, 1953125); 342 343 hi = (rate >> 16) & PTP_RATE_HI_MASK; 344 if (neg_adj) 345 hi |= PTP_RATE_DIR; 346 347 lo = rate & 0xffff; 348 349 mutex_lock(&clock->extreg_lock); 350 351 ext_write(1, phydev, PAGE4, PTP_RATEH, hi); 352 ext_write(1, phydev, PAGE4, PTP_RATEL, lo); 353 354 mutex_unlock(&clock->extreg_lock); 355 356 return 0; 357 } 358 359 static int ptp_dp83640_adjtime(struct ptp_clock_info *ptp, s64 delta) 360 { 361 struct dp83640_clock *clock = 362 container_of(ptp, struct dp83640_clock, caps); 363 struct phy_device *phydev = clock->chosen->phydev; 364 struct timespec ts; 365 int err; 366 367 delta += ADJTIME_FIX; 368 369 ts = ns_to_timespec(delta); 370 371 mutex_lock(&clock->extreg_lock); 372 373 err = tdr_write(1, phydev, &ts, PTP_STEP_CLK); 374 375 mutex_unlock(&clock->extreg_lock); 376 377 return err; 378 } 379 380 static int ptp_dp83640_gettime(struct ptp_clock_info *ptp, struct timespec *ts) 381 { 382 struct dp83640_clock *clock = 383 container_of(ptp, struct dp83640_clock, caps); 384 struct phy_device *phydev = clock->chosen->phydev; 385 unsigned int val[4]; 386 387 mutex_lock(&clock->extreg_lock); 388 389 ext_write(0, phydev, PAGE4, PTP_CTL, PTP_RD_CLK); 390 391 val[0] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[15:0] */ 392 val[1] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[31:16] */ 393 val[2] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[15:0] */ 394 val[3] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[31:16] */ 395 396 mutex_unlock(&clock->extreg_lock); 397 398 ts->tv_nsec = val[0] | (val[1] << 16); 399 ts->tv_sec = val[2] | (val[3] << 16); 400 401 return 0; 402 } 403 404 static int ptp_dp83640_settime(struct ptp_clock_info *ptp, 405 const struct timespec *ts) 406 { 407 struct dp83640_clock *clock = 408 container_of(ptp, struct dp83640_clock, caps); 409 struct phy_device *phydev = clock->chosen->phydev; 410 int err; 411 412 mutex_lock(&clock->extreg_lock); 413 414 err = tdr_write(1, phydev, ts, PTP_LOAD_CLK); 415 416 mutex_unlock(&clock->extreg_lock); 417 418 return err; 419 } 420 421 static int ptp_dp83640_enable(struct ptp_clock_info *ptp, 422 struct ptp_clock_request *rq, int on) 423 { 424 struct dp83640_clock *clock = 425 container_of(ptp, struct dp83640_clock, caps); 426 struct phy_device *phydev = clock->chosen->phydev; 427 int index; 428 u16 evnt, event_num, gpio_num; 429 430 switch (rq->type) { 431 case PTP_CLK_REQ_EXTTS: 432 index = rq->extts.index; 433 if (index < 0 || index >= N_EXT_TS) 434 return -EINVAL; 435 event_num = EXT_EVENT + index; 436 evnt = EVNT_WR | (event_num & EVNT_SEL_MASK) << EVNT_SEL_SHIFT; 437 if (on) { 438 gpio_num = gpio_tab[EXTTS0_GPIO + index]; 439 evnt |= (gpio_num & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT; 440 evnt |= EVNT_RISE; 441 } 442 ext_write(0, phydev, PAGE5, PTP_EVNT, evnt); 443 return 0; 444 445 case PTP_CLK_REQ_PEROUT: 446 if (rq->perout.index != 0) 447 return -EINVAL; 448 periodic_output(clock, rq, on); 449 return 0; 450 451 default: 452 break; 453 } 454 455 return -EOPNOTSUPP; 456 } 457 458 static u8 status_frame_dst[6] = { 0x01, 0x1B, 0x19, 0x00, 0x00, 0x00 }; 459 static u8 status_frame_src[6] = { 0x08, 0x00, 0x17, 0x0B, 0x6B, 0x0F }; 460 461 static void enable_status_frames(struct phy_device *phydev, bool on) 462 { 463 u16 cfg0 = 0, ver; 464 465 if (on) 466 cfg0 = PSF_EVNT_EN | PSF_RXTS_EN | PSF_TXTS_EN | ENDIAN_FLAG; 467 468 ver = (PSF_PTPVER & VERSIONPTP_MASK) << VERSIONPTP_SHIFT; 469 470 ext_write(0, phydev, PAGE5, PSF_CFG0, cfg0); 471 ext_write(0, phydev, PAGE6, PSF_CFG1, ver); 472 473 if (!phydev->attached_dev) { 474 pr_warn("expected to find an attached netdevice\n"); 475 return; 476 } 477 478 if (on) { 479 if (dev_mc_add(phydev->attached_dev, status_frame_dst)) 480 pr_warn("failed to add mc address\n"); 481 } else { 482 if (dev_mc_del(phydev->attached_dev, status_frame_dst)) 483 pr_warn("failed to delete mc address\n"); 484 } 485 } 486 487 static bool is_status_frame(struct sk_buff *skb, int type) 488 { 489 struct ethhdr *h = eth_hdr(skb); 490 491 if (PTP_CLASS_V2_L2 == type && 492 !memcmp(h->h_source, status_frame_src, sizeof(status_frame_src))) 493 return true; 494 else 495 return false; 496 } 497 498 static int expired(struct rxts *rxts) 499 { 500 return time_after(jiffies, rxts->tmo); 501 } 502 503 /* Caller must hold rx_lock. */ 504 static void prune_rx_ts(struct dp83640_private *dp83640) 505 { 506 struct list_head *this, *next; 507 struct rxts *rxts; 508 509 list_for_each_safe(this, next, &dp83640->rxts) { 510 rxts = list_entry(this, struct rxts, list); 511 if (expired(rxts)) { 512 list_del_init(&rxts->list); 513 list_add(&rxts->list, &dp83640->rxpool); 514 } 515 } 516 } 517 518 /* synchronize the phyters so they act as one clock */ 519 520 static void enable_broadcast(struct phy_device *phydev, int init_page, int on) 521 { 522 int val; 523 phy_write(phydev, PAGESEL, 0); 524 val = phy_read(phydev, PHYCR2); 525 if (on) 526 val |= BC_WRITE; 527 else 528 val &= ~BC_WRITE; 529 phy_write(phydev, PHYCR2, val); 530 phy_write(phydev, PAGESEL, init_page); 531 } 532 533 static void recalibrate(struct dp83640_clock *clock) 534 { 535 s64 now, diff; 536 struct phy_txts event_ts; 537 struct timespec ts; 538 struct list_head *this; 539 struct dp83640_private *tmp; 540 struct phy_device *master = clock->chosen->phydev; 541 u16 cal_gpio, cfg0, evnt, ptp_trig, trigger, val; 542 543 trigger = CAL_TRIGGER; 544 cal_gpio = gpio_tab[CALIBRATE_GPIO]; 545 546 mutex_lock(&clock->extreg_lock); 547 548 /* 549 * enable broadcast, disable status frames, enable ptp clock 550 */ 551 list_for_each(this, &clock->phylist) { 552 tmp = list_entry(this, struct dp83640_private, list); 553 enable_broadcast(tmp->phydev, clock->page, 1); 554 tmp->cfg0 = ext_read(tmp->phydev, PAGE5, PSF_CFG0); 555 ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, 0); 556 ext_write(0, tmp->phydev, PAGE4, PTP_CTL, PTP_ENABLE); 557 } 558 enable_broadcast(master, clock->page, 1); 559 cfg0 = ext_read(master, PAGE5, PSF_CFG0); 560 ext_write(0, master, PAGE5, PSF_CFG0, 0); 561 ext_write(0, master, PAGE4, PTP_CTL, PTP_ENABLE); 562 563 /* 564 * enable an event timestamp 565 */ 566 evnt = EVNT_WR | EVNT_RISE | EVNT_SINGLE; 567 evnt |= (CAL_EVENT & EVNT_SEL_MASK) << EVNT_SEL_SHIFT; 568 evnt |= (cal_gpio & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT; 569 570 list_for_each(this, &clock->phylist) { 571 tmp = list_entry(this, struct dp83640_private, list); 572 ext_write(0, tmp->phydev, PAGE5, PTP_EVNT, evnt); 573 } 574 ext_write(0, master, PAGE5, PTP_EVNT, evnt); 575 576 /* 577 * configure a trigger 578 */ 579 ptp_trig = TRIG_WR | TRIG_IF_LATE | TRIG_PULSE; 580 ptp_trig |= (trigger & TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT; 581 ptp_trig |= (cal_gpio & TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT; 582 ext_write(0, master, PAGE5, PTP_TRIG, ptp_trig); 583 584 /* load trigger */ 585 val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT; 586 val |= TRIG_LOAD; 587 ext_write(0, master, PAGE4, PTP_CTL, val); 588 589 /* enable trigger */ 590 val &= ~TRIG_LOAD; 591 val |= TRIG_EN; 592 ext_write(0, master, PAGE4, PTP_CTL, val); 593 594 /* disable trigger */ 595 val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT; 596 val |= TRIG_DIS; 597 ext_write(0, master, PAGE4, PTP_CTL, val); 598 599 /* 600 * read out and correct offsets 601 */ 602 val = ext_read(master, PAGE4, PTP_STS); 603 pr_info("master PTP_STS 0x%04hx\n", val); 604 val = ext_read(master, PAGE4, PTP_ESTS); 605 pr_info("master PTP_ESTS 0x%04hx\n", val); 606 event_ts.ns_lo = ext_read(master, PAGE4, PTP_EDATA); 607 event_ts.ns_hi = ext_read(master, PAGE4, PTP_EDATA); 608 event_ts.sec_lo = ext_read(master, PAGE4, PTP_EDATA); 609 event_ts.sec_hi = ext_read(master, PAGE4, PTP_EDATA); 610 now = phy2txts(&event_ts); 611 612 list_for_each(this, &clock->phylist) { 613 tmp = list_entry(this, struct dp83640_private, list); 614 val = ext_read(tmp->phydev, PAGE4, PTP_STS); 615 pr_info("slave PTP_STS 0x%04hx\n", val); 616 val = ext_read(tmp->phydev, PAGE4, PTP_ESTS); 617 pr_info("slave PTP_ESTS 0x%04hx\n", val); 618 event_ts.ns_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA); 619 event_ts.ns_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA); 620 event_ts.sec_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA); 621 event_ts.sec_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA); 622 diff = now - (s64) phy2txts(&event_ts); 623 pr_info("slave offset %lld nanoseconds\n", diff); 624 diff += ADJTIME_FIX; 625 ts = ns_to_timespec(diff); 626 tdr_write(0, tmp->phydev, &ts, PTP_STEP_CLK); 627 } 628 629 /* 630 * restore status frames 631 */ 632 list_for_each(this, &clock->phylist) { 633 tmp = list_entry(this, struct dp83640_private, list); 634 ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, tmp->cfg0); 635 } 636 ext_write(0, master, PAGE5, PSF_CFG0, cfg0); 637 638 mutex_unlock(&clock->extreg_lock); 639 } 640 641 /* time stamping methods */ 642 643 static inline u16 exts_chan_to_edata(int ch) 644 { 645 return 1 << ((ch + EXT_EVENT) * 2); 646 } 647 648 static int decode_evnt(struct dp83640_private *dp83640, 649 void *data, u16 ests) 650 { 651 struct phy_txts *phy_txts; 652 struct ptp_clock_event event; 653 int i, parsed; 654 int words = (ests >> EVNT_TS_LEN_SHIFT) & EVNT_TS_LEN_MASK; 655 u16 ext_status = 0; 656 657 if (ests & MULT_EVNT) { 658 ext_status = *(u16 *) data; 659 data += sizeof(ext_status); 660 } 661 662 phy_txts = data; 663 664 switch (words) { /* fall through in every case */ 665 case 3: 666 dp83640->edata.sec_hi = phy_txts->sec_hi; 667 case 2: 668 dp83640->edata.sec_lo = phy_txts->sec_lo; 669 case 1: 670 dp83640->edata.ns_hi = phy_txts->ns_hi; 671 case 0: 672 dp83640->edata.ns_lo = phy_txts->ns_lo; 673 } 674 675 if (ext_status) { 676 parsed = words + 2; 677 } else { 678 parsed = words + 1; 679 i = ((ests >> EVNT_NUM_SHIFT) & EVNT_NUM_MASK) - EXT_EVENT; 680 ext_status = exts_chan_to_edata(i); 681 } 682 683 event.type = PTP_CLOCK_EXTTS; 684 event.timestamp = phy2txts(&dp83640->edata); 685 686 for (i = 0; i < N_EXT_TS; i++) { 687 if (ext_status & exts_chan_to_edata(i)) { 688 event.index = i; 689 ptp_clock_event(dp83640->clock->ptp_clock, &event); 690 } 691 } 692 693 return parsed * sizeof(u16); 694 } 695 696 static void decode_rxts(struct dp83640_private *dp83640, 697 struct phy_rxts *phy_rxts) 698 { 699 struct rxts *rxts; 700 unsigned long flags; 701 702 spin_lock_irqsave(&dp83640->rx_lock, flags); 703 704 prune_rx_ts(dp83640); 705 706 if (list_empty(&dp83640->rxpool)) { 707 pr_debug("rx timestamp pool is empty\n"); 708 goto out; 709 } 710 rxts = list_first_entry(&dp83640->rxpool, struct rxts, list); 711 list_del_init(&rxts->list); 712 phy2rxts(phy_rxts, rxts); 713 list_add_tail(&rxts->list, &dp83640->rxts); 714 out: 715 spin_unlock_irqrestore(&dp83640->rx_lock, flags); 716 } 717 718 static void decode_txts(struct dp83640_private *dp83640, 719 struct phy_txts *phy_txts) 720 { 721 struct skb_shared_hwtstamps shhwtstamps; 722 struct sk_buff *skb; 723 u64 ns; 724 725 /* We must already have the skb that triggered this. */ 726 727 skb = skb_dequeue(&dp83640->tx_queue); 728 729 if (!skb) { 730 pr_debug("have timestamp but tx_queue empty\n"); 731 return; 732 } 733 ns = phy2txts(phy_txts); 734 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 735 shhwtstamps.hwtstamp = ns_to_ktime(ns); 736 skb_complete_tx_timestamp(skb, &shhwtstamps); 737 } 738 739 static void decode_status_frame(struct dp83640_private *dp83640, 740 struct sk_buff *skb) 741 { 742 struct phy_rxts *phy_rxts; 743 struct phy_txts *phy_txts; 744 u8 *ptr; 745 int len, size; 746 u16 ests, type; 747 748 ptr = skb->data + 2; 749 750 for (len = skb_headlen(skb) - 2; len > sizeof(type); len -= size) { 751 752 type = *(u16 *)ptr; 753 ests = type & 0x0fff; 754 type = type & 0xf000; 755 len -= sizeof(type); 756 ptr += sizeof(type); 757 758 if (PSF_RX == type && len >= sizeof(*phy_rxts)) { 759 760 phy_rxts = (struct phy_rxts *) ptr; 761 decode_rxts(dp83640, phy_rxts); 762 size = sizeof(*phy_rxts); 763 764 } else if (PSF_TX == type && len >= sizeof(*phy_txts)) { 765 766 phy_txts = (struct phy_txts *) ptr; 767 decode_txts(dp83640, phy_txts); 768 size = sizeof(*phy_txts); 769 770 } else if (PSF_EVNT == type && len >= sizeof(*phy_txts)) { 771 772 size = decode_evnt(dp83640, ptr, ests); 773 774 } else { 775 size = 0; 776 break; 777 } 778 ptr += size; 779 } 780 } 781 782 static int is_sync(struct sk_buff *skb, int type) 783 { 784 u8 *data = skb->data, *msgtype; 785 unsigned int offset = 0; 786 787 switch (type) { 788 case PTP_CLASS_V1_IPV4: 789 case PTP_CLASS_V2_IPV4: 790 offset = ETH_HLEN + IPV4_HLEN(data) + UDP_HLEN; 791 break; 792 case PTP_CLASS_V1_IPV6: 793 case PTP_CLASS_V2_IPV6: 794 offset = OFF_PTP6; 795 break; 796 case PTP_CLASS_V2_L2: 797 offset = ETH_HLEN; 798 break; 799 case PTP_CLASS_V2_VLAN: 800 offset = ETH_HLEN + VLAN_HLEN; 801 break; 802 default: 803 return 0; 804 } 805 806 if (type & PTP_CLASS_V1) 807 offset += OFF_PTP_CONTROL; 808 809 if (skb->len < offset + 1) 810 return 0; 811 812 msgtype = data + offset; 813 814 return (*msgtype & 0xf) == 0; 815 } 816 817 static int match(struct sk_buff *skb, unsigned int type, struct rxts *rxts) 818 { 819 u16 *seqid; 820 unsigned int offset; 821 u8 *msgtype, *data = skb_mac_header(skb); 822 823 /* check sequenceID, messageType, 12 bit hash of offset 20-29 */ 824 825 switch (type) { 826 case PTP_CLASS_V1_IPV4: 827 case PTP_CLASS_V2_IPV4: 828 offset = ETH_HLEN + IPV4_HLEN(data) + UDP_HLEN; 829 break; 830 case PTP_CLASS_V1_IPV6: 831 case PTP_CLASS_V2_IPV6: 832 offset = OFF_PTP6; 833 break; 834 case PTP_CLASS_V2_L2: 835 offset = ETH_HLEN; 836 break; 837 case PTP_CLASS_V2_VLAN: 838 offset = ETH_HLEN + VLAN_HLEN; 839 break; 840 default: 841 return 0; 842 } 843 844 if (skb->len + ETH_HLEN < offset + OFF_PTP_SEQUENCE_ID + sizeof(*seqid)) 845 return 0; 846 847 if (unlikely(type & PTP_CLASS_V1)) 848 msgtype = data + offset + OFF_PTP_CONTROL; 849 else 850 msgtype = data + offset; 851 852 seqid = (u16 *)(data + offset + OFF_PTP_SEQUENCE_ID); 853 854 return (rxts->msgtype == (*msgtype & 0xf) && 855 rxts->seqid == ntohs(*seqid)); 856 } 857 858 static void dp83640_free_clocks(void) 859 { 860 struct dp83640_clock *clock; 861 struct list_head *this, *next; 862 863 mutex_lock(&phyter_clocks_lock); 864 865 list_for_each_safe(this, next, &phyter_clocks) { 866 clock = list_entry(this, struct dp83640_clock, list); 867 if (!list_empty(&clock->phylist)) { 868 pr_warn("phy list non-empty while unloading\n"); 869 BUG(); 870 } 871 list_del(&clock->list); 872 mutex_destroy(&clock->extreg_lock); 873 mutex_destroy(&clock->clock_lock); 874 put_device(&clock->bus->dev); 875 kfree(clock); 876 } 877 878 mutex_unlock(&phyter_clocks_lock); 879 } 880 881 static void dp83640_clock_init(struct dp83640_clock *clock, struct mii_bus *bus) 882 { 883 INIT_LIST_HEAD(&clock->list); 884 clock->bus = bus; 885 mutex_init(&clock->extreg_lock); 886 mutex_init(&clock->clock_lock); 887 INIT_LIST_HEAD(&clock->phylist); 888 clock->caps.owner = THIS_MODULE; 889 sprintf(clock->caps.name, "dp83640 timer"); 890 clock->caps.max_adj = 1953124; 891 clock->caps.n_alarm = 0; 892 clock->caps.n_ext_ts = N_EXT_TS; 893 clock->caps.n_per_out = 1; 894 clock->caps.pps = 0; 895 clock->caps.adjfreq = ptp_dp83640_adjfreq; 896 clock->caps.adjtime = ptp_dp83640_adjtime; 897 clock->caps.gettime = ptp_dp83640_gettime; 898 clock->caps.settime = ptp_dp83640_settime; 899 clock->caps.enable = ptp_dp83640_enable; 900 /* 901 * Get a reference to this bus instance. 902 */ 903 get_device(&bus->dev); 904 } 905 906 static int choose_this_phy(struct dp83640_clock *clock, 907 struct phy_device *phydev) 908 { 909 if (chosen_phy == -1 && !clock->chosen) 910 return 1; 911 912 if (chosen_phy == phydev->addr) 913 return 1; 914 915 return 0; 916 } 917 918 static struct dp83640_clock *dp83640_clock_get(struct dp83640_clock *clock) 919 { 920 if (clock) 921 mutex_lock(&clock->clock_lock); 922 return clock; 923 } 924 925 /* 926 * Look up and lock a clock by bus instance. 927 * If there is no clock for this bus, then create it first. 928 */ 929 static struct dp83640_clock *dp83640_clock_get_bus(struct mii_bus *bus) 930 { 931 struct dp83640_clock *clock = NULL, *tmp; 932 struct list_head *this; 933 934 mutex_lock(&phyter_clocks_lock); 935 936 list_for_each(this, &phyter_clocks) { 937 tmp = list_entry(this, struct dp83640_clock, list); 938 if (tmp->bus == bus) { 939 clock = tmp; 940 break; 941 } 942 } 943 if (clock) 944 goto out; 945 946 clock = kzalloc(sizeof(struct dp83640_clock), GFP_KERNEL); 947 if (!clock) 948 goto out; 949 950 dp83640_clock_init(clock, bus); 951 list_add_tail(&phyter_clocks, &clock->list); 952 out: 953 mutex_unlock(&phyter_clocks_lock); 954 955 return dp83640_clock_get(clock); 956 } 957 958 static void dp83640_clock_put(struct dp83640_clock *clock) 959 { 960 mutex_unlock(&clock->clock_lock); 961 } 962 963 static int dp83640_probe(struct phy_device *phydev) 964 { 965 struct dp83640_clock *clock; 966 struct dp83640_private *dp83640; 967 int err = -ENOMEM, i; 968 969 if (phydev->addr == BROADCAST_ADDR) 970 return 0; 971 972 clock = dp83640_clock_get_bus(phydev->bus); 973 if (!clock) 974 goto no_clock; 975 976 dp83640 = kzalloc(sizeof(struct dp83640_private), GFP_KERNEL); 977 if (!dp83640) 978 goto no_memory; 979 980 dp83640->phydev = phydev; 981 INIT_WORK(&dp83640->ts_work, rx_timestamp_work); 982 983 INIT_LIST_HEAD(&dp83640->rxts); 984 INIT_LIST_HEAD(&dp83640->rxpool); 985 for (i = 0; i < MAX_RXTS; i++) 986 list_add(&dp83640->rx_pool_data[i].list, &dp83640->rxpool); 987 988 phydev->priv = dp83640; 989 990 spin_lock_init(&dp83640->rx_lock); 991 skb_queue_head_init(&dp83640->rx_queue); 992 skb_queue_head_init(&dp83640->tx_queue); 993 994 dp83640->clock = clock; 995 996 if (choose_this_phy(clock, phydev)) { 997 clock->chosen = dp83640; 998 clock->ptp_clock = ptp_clock_register(&clock->caps, &phydev->dev); 999 if (IS_ERR(clock->ptp_clock)) { 1000 err = PTR_ERR(clock->ptp_clock); 1001 goto no_register; 1002 } 1003 } else 1004 list_add_tail(&dp83640->list, &clock->phylist); 1005 1006 if (clock->chosen && !list_empty(&clock->phylist)) 1007 recalibrate(clock); 1008 else 1009 enable_broadcast(dp83640->phydev, clock->page, 1); 1010 1011 dp83640_clock_put(clock); 1012 return 0; 1013 1014 no_register: 1015 clock->chosen = NULL; 1016 kfree(dp83640); 1017 no_memory: 1018 dp83640_clock_put(clock); 1019 no_clock: 1020 return err; 1021 } 1022 1023 static void dp83640_remove(struct phy_device *phydev) 1024 { 1025 struct dp83640_clock *clock; 1026 struct list_head *this, *next; 1027 struct dp83640_private *tmp, *dp83640 = phydev->priv; 1028 struct sk_buff *skb; 1029 1030 if (phydev->addr == BROADCAST_ADDR) 1031 return; 1032 1033 enable_status_frames(phydev, false); 1034 cancel_work_sync(&dp83640->ts_work); 1035 1036 while ((skb = skb_dequeue(&dp83640->rx_queue)) != NULL) 1037 kfree_skb(skb); 1038 1039 while ((skb = skb_dequeue(&dp83640->tx_queue)) != NULL) 1040 skb_complete_tx_timestamp(skb, NULL); 1041 1042 clock = dp83640_clock_get(dp83640->clock); 1043 1044 if (dp83640 == clock->chosen) { 1045 ptp_clock_unregister(clock->ptp_clock); 1046 clock->chosen = NULL; 1047 } else { 1048 list_for_each_safe(this, next, &clock->phylist) { 1049 tmp = list_entry(this, struct dp83640_private, list); 1050 if (tmp == dp83640) { 1051 list_del_init(&tmp->list); 1052 break; 1053 } 1054 } 1055 } 1056 1057 dp83640_clock_put(clock); 1058 kfree(dp83640); 1059 } 1060 1061 static int dp83640_ack_interrupt(struct phy_device *phydev) 1062 { 1063 int err = phy_read(phydev, MII_DP83640_MISR); 1064 1065 if (err < 0) 1066 return err; 1067 1068 return 0; 1069 } 1070 1071 static int dp83640_config_intr(struct phy_device *phydev) 1072 { 1073 int micr; 1074 int misr; 1075 int err; 1076 1077 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 1078 misr = phy_read(phydev, MII_DP83640_MISR); 1079 if (misr < 0) 1080 return misr; 1081 misr |= 1082 (MII_DP83640_MISR_ANC_INT_EN | 1083 MII_DP83640_MISR_DUP_INT_EN | 1084 MII_DP83640_MISR_SPD_INT_EN | 1085 MII_DP83640_MISR_LINK_INT_EN); 1086 err = phy_write(phydev, MII_DP83640_MISR, misr); 1087 if (err < 0) 1088 return err; 1089 1090 micr = phy_read(phydev, MII_DP83640_MICR); 1091 if (micr < 0) 1092 return micr; 1093 micr |= 1094 (MII_DP83640_MICR_OE | 1095 MII_DP83640_MICR_IE); 1096 return phy_write(phydev, MII_DP83640_MICR, micr); 1097 } else { 1098 micr = phy_read(phydev, MII_DP83640_MICR); 1099 if (micr < 0) 1100 return micr; 1101 micr &= 1102 ~(MII_DP83640_MICR_OE | 1103 MII_DP83640_MICR_IE); 1104 err = phy_write(phydev, MII_DP83640_MICR, micr); 1105 if (err < 0) 1106 return err; 1107 1108 misr = phy_read(phydev, MII_DP83640_MISR); 1109 if (misr < 0) 1110 return misr; 1111 misr &= 1112 ~(MII_DP83640_MISR_ANC_INT_EN | 1113 MII_DP83640_MISR_DUP_INT_EN | 1114 MII_DP83640_MISR_SPD_INT_EN | 1115 MII_DP83640_MISR_LINK_INT_EN); 1116 return phy_write(phydev, MII_DP83640_MISR, misr); 1117 } 1118 } 1119 1120 static int dp83640_hwtstamp(struct phy_device *phydev, struct ifreq *ifr) 1121 { 1122 struct dp83640_private *dp83640 = phydev->priv; 1123 struct hwtstamp_config cfg; 1124 u16 txcfg0, rxcfg0; 1125 1126 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 1127 return -EFAULT; 1128 1129 if (cfg.flags) /* reserved for future extensions */ 1130 return -EINVAL; 1131 1132 if (cfg.tx_type < 0 || cfg.tx_type > HWTSTAMP_TX_ONESTEP_SYNC) 1133 return -ERANGE; 1134 1135 dp83640->hwts_tx_en = cfg.tx_type; 1136 1137 switch (cfg.rx_filter) { 1138 case HWTSTAMP_FILTER_NONE: 1139 dp83640->hwts_rx_en = 0; 1140 dp83640->layer = 0; 1141 dp83640->version = 0; 1142 break; 1143 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 1144 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 1145 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 1146 dp83640->hwts_rx_en = 1; 1147 dp83640->layer = LAYER4; 1148 dp83640->version = 1; 1149 break; 1150 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1151 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1152 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1153 dp83640->hwts_rx_en = 1; 1154 dp83640->layer = LAYER4; 1155 dp83640->version = 2; 1156 break; 1157 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1158 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1159 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1160 dp83640->hwts_rx_en = 1; 1161 dp83640->layer = LAYER2; 1162 dp83640->version = 2; 1163 break; 1164 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1165 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1166 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1167 dp83640->hwts_rx_en = 1; 1168 dp83640->layer = LAYER4|LAYER2; 1169 dp83640->version = 2; 1170 break; 1171 default: 1172 return -ERANGE; 1173 } 1174 1175 txcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT; 1176 rxcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT; 1177 1178 if (dp83640->layer & LAYER2) { 1179 txcfg0 |= TX_L2_EN; 1180 rxcfg0 |= RX_L2_EN; 1181 } 1182 if (dp83640->layer & LAYER4) { 1183 txcfg0 |= TX_IPV6_EN | TX_IPV4_EN; 1184 rxcfg0 |= RX_IPV6_EN | RX_IPV4_EN; 1185 } 1186 1187 if (dp83640->hwts_tx_en) 1188 txcfg0 |= TX_TS_EN; 1189 1190 if (dp83640->hwts_tx_en == HWTSTAMP_TX_ONESTEP_SYNC) 1191 txcfg0 |= SYNC_1STEP | CHK_1STEP; 1192 1193 if (dp83640->hwts_rx_en) 1194 rxcfg0 |= RX_TS_EN; 1195 1196 mutex_lock(&dp83640->clock->extreg_lock); 1197 1198 if (dp83640->hwts_tx_en || dp83640->hwts_rx_en) { 1199 enable_status_frames(phydev, true); 1200 ext_write(0, phydev, PAGE4, PTP_CTL, PTP_ENABLE); 1201 } 1202 1203 ext_write(0, phydev, PAGE5, PTP_TXCFG0, txcfg0); 1204 ext_write(0, phydev, PAGE5, PTP_RXCFG0, rxcfg0); 1205 1206 mutex_unlock(&dp83640->clock->extreg_lock); 1207 1208 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1209 } 1210 1211 static void rx_timestamp_work(struct work_struct *work) 1212 { 1213 struct dp83640_private *dp83640 = 1214 container_of(work, struct dp83640_private, ts_work); 1215 struct list_head *this, *next; 1216 struct rxts *rxts; 1217 struct skb_shared_hwtstamps *shhwtstamps; 1218 struct sk_buff *skb; 1219 unsigned int type; 1220 unsigned long flags; 1221 1222 /* Deliver each deferred packet, with or without a time stamp. */ 1223 1224 while ((skb = skb_dequeue(&dp83640->rx_queue)) != NULL) { 1225 type = SKB_PTP_TYPE(skb); 1226 spin_lock_irqsave(&dp83640->rx_lock, flags); 1227 list_for_each_safe(this, next, &dp83640->rxts) { 1228 rxts = list_entry(this, struct rxts, list); 1229 if (match(skb, type, rxts)) { 1230 shhwtstamps = skb_hwtstamps(skb); 1231 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 1232 shhwtstamps->hwtstamp = ns_to_ktime(rxts->ns); 1233 list_del_init(&rxts->list); 1234 list_add(&rxts->list, &dp83640->rxpool); 1235 break; 1236 } 1237 } 1238 spin_unlock_irqrestore(&dp83640->rx_lock, flags); 1239 netif_rx_ni(skb); 1240 } 1241 1242 /* Clear out expired time stamps. */ 1243 1244 spin_lock_irqsave(&dp83640->rx_lock, flags); 1245 prune_rx_ts(dp83640); 1246 spin_unlock_irqrestore(&dp83640->rx_lock, flags); 1247 } 1248 1249 static bool dp83640_rxtstamp(struct phy_device *phydev, 1250 struct sk_buff *skb, int type) 1251 { 1252 struct dp83640_private *dp83640 = phydev->priv; 1253 1254 if (!dp83640->hwts_rx_en) 1255 return false; 1256 1257 if (is_status_frame(skb, type)) { 1258 decode_status_frame(dp83640, skb); 1259 kfree_skb(skb); 1260 return true; 1261 } 1262 1263 SKB_PTP_TYPE(skb) = type; 1264 skb_queue_tail(&dp83640->rx_queue, skb); 1265 schedule_work(&dp83640->ts_work); 1266 1267 return true; 1268 } 1269 1270 static void dp83640_txtstamp(struct phy_device *phydev, 1271 struct sk_buff *skb, int type) 1272 { 1273 struct dp83640_private *dp83640 = phydev->priv; 1274 1275 switch (dp83640->hwts_tx_en) { 1276 1277 case HWTSTAMP_TX_ONESTEP_SYNC: 1278 if (is_sync(skb, type)) { 1279 skb_complete_tx_timestamp(skb, NULL); 1280 return; 1281 } 1282 /* fall through */ 1283 case HWTSTAMP_TX_ON: 1284 skb_queue_tail(&dp83640->tx_queue, skb); 1285 schedule_work(&dp83640->ts_work); 1286 break; 1287 1288 case HWTSTAMP_TX_OFF: 1289 default: 1290 skb_complete_tx_timestamp(skb, NULL); 1291 break; 1292 } 1293 } 1294 1295 static int dp83640_ts_info(struct phy_device *dev, struct ethtool_ts_info *info) 1296 { 1297 struct dp83640_private *dp83640 = dev->priv; 1298 1299 info->so_timestamping = 1300 SOF_TIMESTAMPING_TX_HARDWARE | 1301 SOF_TIMESTAMPING_RX_HARDWARE | 1302 SOF_TIMESTAMPING_RAW_HARDWARE; 1303 info->phc_index = ptp_clock_index(dp83640->clock->ptp_clock); 1304 info->tx_types = 1305 (1 << HWTSTAMP_TX_OFF) | 1306 (1 << HWTSTAMP_TX_ON) | 1307 (1 << HWTSTAMP_TX_ONESTEP_SYNC); 1308 info->rx_filters = 1309 (1 << HWTSTAMP_FILTER_NONE) | 1310 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) | 1311 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) | 1312 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) | 1313 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) | 1314 (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) | 1315 (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) | 1316 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 1317 (1 << HWTSTAMP_FILTER_PTP_V2_L2_SYNC) | 1318 (1 << HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ) | 1319 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT) | 1320 (1 << HWTSTAMP_FILTER_PTP_V2_SYNC) | 1321 (1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ); 1322 return 0; 1323 } 1324 1325 static struct phy_driver dp83640_driver = { 1326 .phy_id = DP83640_PHY_ID, 1327 .phy_id_mask = 0xfffffff0, 1328 .name = "NatSemi DP83640", 1329 .features = PHY_BASIC_FEATURES, 1330 .flags = PHY_HAS_INTERRUPT, 1331 .probe = dp83640_probe, 1332 .remove = dp83640_remove, 1333 .config_aneg = genphy_config_aneg, 1334 .read_status = genphy_read_status, 1335 .ack_interrupt = dp83640_ack_interrupt, 1336 .config_intr = dp83640_config_intr, 1337 .ts_info = dp83640_ts_info, 1338 .hwtstamp = dp83640_hwtstamp, 1339 .rxtstamp = dp83640_rxtstamp, 1340 .txtstamp = dp83640_txtstamp, 1341 .driver = {.owner = THIS_MODULE,} 1342 }; 1343 1344 static int __init dp83640_init(void) 1345 { 1346 return phy_driver_register(&dp83640_driver); 1347 } 1348 1349 static void __exit dp83640_exit(void) 1350 { 1351 dp83640_free_clocks(); 1352 phy_driver_unregister(&dp83640_driver); 1353 } 1354 1355 MODULE_DESCRIPTION("National Semiconductor DP83640 PHY driver"); 1356 MODULE_AUTHOR("Richard Cochran <richardcochran@gmail.at>"); 1357 MODULE_LICENSE("GPL"); 1358 1359 module_init(dp83640_init); 1360 module_exit(dp83640_exit); 1361 1362 static struct mdio_device_id __maybe_unused dp83640_tbl[] = { 1363 { DP83640_PHY_ID, 0xfffffff0 }, 1364 { } 1365 }; 1366 1367 MODULE_DEVICE_TABLE(mdio, dp83640_tbl); 1368