1 /* 2 * Driver for the National Semiconductor DP83640 PHYTER 3 * 4 * Copyright (C) 2010 OMICRON electronics GmbH 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 19 */ 20 21 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 22 23 #include <linux/ethtool.h> 24 #include <linux/kernel.h> 25 #include <linux/list.h> 26 #include <linux/mii.h> 27 #include <linux/module.h> 28 #include <linux/net_tstamp.h> 29 #include <linux/netdevice.h> 30 #include <linux/phy.h> 31 #include <linux/ptp_classify.h> 32 #include <linux/ptp_clock_kernel.h> 33 34 #include "dp83640_reg.h" 35 36 #define DP83640_PHY_ID 0x20005ce1 37 #define PAGESEL 0x13 38 #define LAYER4 0x02 39 #define LAYER2 0x01 40 #define MAX_RXTS 64 41 #define N_EXT_TS 6 42 #define PSF_PTPVER 2 43 #define PSF_EVNT 0x4000 44 #define PSF_RX 0x2000 45 #define PSF_TX 0x1000 46 #define EXT_EVENT 1 47 #define CAL_EVENT 7 48 #define CAL_TRIGGER 7 49 #define PER_TRIGGER 6 50 51 #define MII_DP83640_MICR 0x11 52 #define MII_DP83640_MISR 0x12 53 54 #define MII_DP83640_MICR_OE 0x1 55 #define MII_DP83640_MICR_IE 0x2 56 57 #define MII_DP83640_MISR_RHF_INT_EN 0x01 58 #define MII_DP83640_MISR_FHF_INT_EN 0x02 59 #define MII_DP83640_MISR_ANC_INT_EN 0x04 60 #define MII_DP83640_MISR_DUP_INT_EN 0x08 61 #define MII_DP83640_MISR_SPD_INT_EN 0x10 62 #define MII_DP83640_MISR_LINK_INT_EN 0x20 63 #define MII_DP83640_MISR_ED_INT_EN 0x40 64 #define MII_DP83640_MISR_LQ_INT_EN 0x80 65 66 /* phyter seems to miss the mark by 16 ns */ 67 #define ADJTIME_FIX 16 68 69 #if defined(__BIG_ENDIAN) 70 #define ENDIAN_FLAG 0 71 #elif defined(__LITTLE_ENDIAN) 72 #define ENDIAN_FLAG PSF_ENDIAN 73 #endif 74 75 #define SKB_PTP_TYPE(__skb) (*(unsigned int *)((__skb)->cb)) 76 77 struct phy_rxts { 78 u16 ns_lo; /* ns[15:0] */ 79 u16 ns_hi; /* overflow[1:0], ns[29:16] */ 80 u16 sec_lo; /* sec[15:0] */ 81 u16 sec_hi; /* sec[31:16] */ 82 u16 seqid; /* sequenceId[15:0] */ 83 u16 msgtype; /* messageType[3:0], hash[11:0] */ 84 }; 85 86 struct phy_txts { 87 u16 ns_lo; /* ns[15:0] */ 88 u16 ns_hi; /* overflow[1:0], ns[29:16] */ 89 u16 sec_lo; /* sec[15:0] */ 90 u16 sec_hi; /* sec[31:16] */ 91 }; 92 93 struct rxts { 94 struct list_head list; 95 unsigned long tmo; 96 u64 ns; 97 u16 seqid; 98 u8 msgtype; 99 u16 hash; 100 }; 101 102 struct dp83640_clock; 103 104 struct dp83640_private { 105 struct list_head list; 106 struct dp83640_clock *clock; 107 struct phy_device *phydev; 108 struct work_struct ts_work; 109 int hwts_tx_en; 110 int hwts_rx_en; 111 int layer; 112 int version; 113 /* remember state of cfg0 during calibration */ 114 int cfg0; 115 /* remember the last event time stamp */ 116 struct phy_txts edata; 117 /* list of rx timestamps */ 118 struct list_head rxts; 119 struct list_head rxpool; 120 struct rxts rx_pool_data[MAX_RXTS]; 121 /* protects above three fields from concurrent access */ 122 spinlock_t rx_lock; 123 /* queues of incoming and outgoing packets */ 124 struct sk_buff_head rx_queue; 125 struct sk_buff_head tx_queue; 126 }; 127 128 struct dp83640_clock { 129 /* keeps the instance in the 'phyter_clocks' list */ 130 struct list_head list; 131 /* we create one clock instance per MII bus */ 132 struct mii_bus *bus; 133 /* protects extended registers from concurrent access */ 134 struct mutex extreg_lock; 135 /* remembers which page was last selected */ 136 int page; 137 /* our advertised capabilities */ 138 struct ptp_clock_info caps; 139 /* protects the three fields below from concurrent access */ 140 struct mutex clock_lock; 141 /* the one phyter from which we shall read */ 142 struct dp83640_private *chosen; 143 /* list of the other attached phyters, not chosen */ 144 struct list_head phylist; 145 /* reference to our PTP hardware clock */ 146 struct ptp_clock *ptp_clock; 147 }; 148 149 /* globals */ 150 151 enum { 152 CALIBRATE_GPIO, 153 PEROUT_GPIO, 154 EXTTS0_GPIO, 155 EXTTS1_GPIO, 156 EXTTS2_GPIO, 157 EXTTS3_GPIO, 158 EXTTS4_GPIO, 159 EXTTS5_GPIO, 160 GPIO_TABLE_SIZE 161 }; 162 163 static int chosen_phy = -1; 164 static ushort gpio_tab[GPIO_TABLE_SIZE] = { 165 1, 2, 3, 4, 8, 9, 10, 11 166 }; 167 168 module_param(chosen_phy, int, 0444); 169 module_param_array(gpio_tab, ushort, NULL, 0444); 170 171 MODULE_PARM_DESC(chosen_phy, \ 172 "The address of the PHY to use for the ancillary clock features"); 173 MODULE_PARM_DESC(gpio_tab, \ 174 "Which GPIO line to use for which purpose: cal,perout,extts1,...,extts6"); 175 176 /* a list of clocks and a mutex to protect it */ 177 static LIST_HEAD(phyter_clocks); 178 static DEFINE_MUTEX(phyter_clocks_lock); 179 180 static void rx_timestamp_work(struct work_struct *work); 181 182 /* extended register access functions */ 183 184 #define BROADCAST_ADDR 31 185 186 static inline int broadcast_write(struct mii_bus *bus, u32 regnum, u16 val) 187 { 188 return mdiobus_write(bus, BROADCAST_ADDR, regnum, val); 189 } 190 191 /* Caller must hold extreg_lock. */ 192 static int ext_read(struct phy_device *phydev, int page, u32 regnum) 193 { 194 struct dp83640_private *dp83640 = phydev->priv; 195 int val; 196 197 if (dp83640->clock->page != page) { 198 broadcast_write(phydev->bus, PAGESEL, page); 199 dp83640->clock->page = page; 200 } 201 val = phy_read(phydev, regnum); 202 203 return val; 204 } 205 206 /* Caller must hold extreg_lock. */ 207 static void ext_write(int broadcast, struct phy_device *phydev, 208 int page, u32 regnum, u16 val) 209 { 210 struct dp83640_private *dp83640 = phydev->priv; 211 212 if (dp83640->clock->page != page) { 213 broadcast_write(phydev->bus, PAGESEL, page); 214 dp83640->clock->page = page; 215 } 216 if (broadcast) 217 broadcast_write(phydev->bus, regnum, val); 218 else 219 phy_write(phydev, regnum, val); 220 } 221 222 /* Caller must hold extreg_lock. */ 223 static int tdr_write(int bc, struct phy_device *dev, 224 const struct timespec *ts, u16 cmd) 225 { 226 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec & 0xffff);/* ns[15:0] */ 227 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec >> 16); /* ns[31:16] */ 228 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec & 0xffff); /* sec[15:0] */ 229 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec >> 16); /* sec[31:16]*/ 230 231 ext_write(bc, dev, PAGE4, PTP_CTL, cmd); 232 233 return 0; 234 } 235 236 /* convert phy timestamps into driver timestamps */ 237 238 static void phy2rxts(struct phy_rxts *p, struct rxts *rxts) 239 { 240 u32 sec; 241 242 sec = p->sec_lo; 243 sec |= p->sec_hi << 16; 244 245 rxts->ns = p->ns_lo; 246 rxts->ns |= (p->ns_hi & 0x3fff) << 16; 247 rxts->ns += ((u64)sec) * 1000000000ULL; 248 rxts->seqid = p->seqid; 249 rxts->msgtype = (p->msgtype >> 12) & 0xf; 250 rxts->hash = p->msgtype & 0x0fff; 251 rxts->tmo = jiffies + 2; 252 } 253 254 static u64 phy2txts(struct phy_txts *p) 255 { 256 u64 ns; 257 u32 sec; 258 259 sec = p->sec_lo; 260 sec |= p->sec_hi << 16; 261 262 ns = p->ns_lo; 263 ns |= (p->ns_hi & 0x3fff) << 16; 264 ns += ((u64)sec) * 1000000000ULL; 265 266 return ns; 267 } 268 269 static void periodic_output(struct dp83640_clock *clock, 270 struct ptp_clock_request *clkreq, bool on) 271 { 272 struct dp83640_private *dp83640 = clock->chosen; 273 struct phy_device *phydev = dp83640->phydev; 274 u32 sec, nsec, period; 275 u16 gpio, ptp_trig, trigger, val; 276 277 gpio = on ? gpio_tab[PEROUT_GPIO] : 0; 278 trigger = PER_TRIGGER; 279 280 ptp_trig = TRIG_WR | 281 (trigger & TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT | 282 (gpio & TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT | 283 TRIG_PER | 284 TRIG_PULSE; 285 286 val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT; 287 288 if (!on) { 289 val |= TRIG_DIS; 290 mutex_lock(&clock->extreg_lock); 291 ext_write(0, phydev, PAGE5, PTP_TRIG, ptp_trig); 292 ext_write(0, phydev, PAGE4, PTP_CTL, val); 293 mutex_unlock(&clock->extreg_lock); 294 return; 295 } 296 297 sec = clkreq->perout.start.sec; 298 nsec = clkreq->perout.start.nsec; 299 period = clkreq->perout.period.sec * 1000000000UL; 300 period += clkreq->perout.period.nsec; 301 302 mutex_lock(&clock->extreg_lock); 303 304 ext_write(0, phydev, PAGE5, PTP_TRIG, ptp_trig); 305 306 /*load trigger*/ 307 val |= TRIG_LOAD; 308 ext_write(0, phydev, PAGE4, PTP_CTL, val); 309 ext_write(0, phydev, PAGE4, PTP_TDR, nsec & 0xffff); /* ns[15:0] */ 310 ext_write(0, phydev, PAGE4, PTP_TDR, nsec >> 16); /* ns[31:16] */ 311 ext_write(0, phydev, PAGE4, PTP_TDR, sec & 0xffff); /* sec[15:0] */ 312 ext_write(0, phydev, PAGE4, PTP_TDR, sec >> 16); /* sec[31:16] */ 313 ext_write(0, phydev, PAGE4, PTP_TDR, period & 0xffff); /* ns[15:0] */ 314 ext_write(0, phydev, PAGE4, PTP_TDR, period >> 16); /* ns[31:16] */ 315 316 /*enable trigger*/ 317 val &= ~TRIG_LOAD; 318 val |= TRIG_EN; 319 ext_write(0, phydev, PAGE4, PTP_CTL, val); 320 321 mutex_unlock(&clock->extreg_lock); 322 } 323 324 /* ptp clock methods */ 325 326 static int ptp_dp83640_adjfreq(struct ptp_clock_info *ptp, s32 ppb) 327 { 328 struct dp83640_clock *clock = 329 container_of(ptp, struct dp83640_clock, caps); 330 struct phy_device *phydev = clock->chosen->phydev; 331 u64 rate; 332 int neg_adj = 0; 333 u16 hi, lo; 334 335 if (ppb < 0) { 336 neg_adj = 1; 337 ppb = -ppb; 338 } 339 rate = ppb; 340 rate <<= 26; 341 rate = div_u64(rate, 1953125); 342 343 hi = (rate >> 16) & PTP_RATE_HI_MASK; 344 if (neg_adj) 345 hi |= PTP_RATE_DIR; 346 347 lo = rate & 0xffff; 348 349 mutex_lock(&clock->extreg_lock); 350 351 ext_write(1, phydev, PAGE4, PTP_RATEH, hi); 352 ext_write(1, phydev, PAGE4, PTP_RATEL, lo); 353 354 mutex_unlock(&clock->extreg_lock); 355 356 return 0; 357 } 358 359 static int ptp_dp83640_adjtime(struct ptp_clock_info *ptp, s64 delta) 360 { 361 struct dp83640_clock *clock = 362 container_of(ptp, struct dp83640_clock, caps); 363 struct phy_device *phydev = clock->chosen->phydev; 364 struct timespec ts; 365 int err; 366 367 delta += ADJTIME_FIX; 368 369 ts = ns_to_timespec(delta); 370 371 mutex_lock(&clock->extreg_lock); 372 373 err = tdr_write(1, phydev, &ts, PTP_STEP_CLK); 374 375 mutex_unlock(&clock->extreg_lock); 376 377 return err; 378 } 379 380 static int ptp_dp83640_gettime(struct ptp_clock_info *ptp, struct timespec *ts) 381 { 382 struct dp83640_clock *clock = 383 container_of(ptp, struct dp83640_clock, caps); 384 struct phy_device *phydev = clock->chosen->phydev; 385 unsigned int val[4]; 386 387 mutex_lock(&clock->extreg_lock); 388 389 ext_write(0, phydev, PAGE4, PTP_CTL, PTP_RD_CLK); 390 391 val[0] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[15:0] */ 392 val[1] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[31:16] */ 393 val[2] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[15:0] */ 394 val[3] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[31:16] */ 395 396 mutex_unlock(&clock->extreg_lock); 397 398 ts->tv_nsec = val[0] | (val[1] << 16); 399 ts->tv_sec = val[2] | (val[3] << 16); 400 401 return 0; 402 } 403 404 static int ptp_dp83640_settime(struct ptp_clock_info *ptp, 405 const struct timespec *ts) 406 { 407 struct dp83640_clock *clock = 408 container_of(ptp, struct dp83640_clock, caps); 409 struct phy_device *phydev = clock->chosen->phydev; 410 int err; 411 412 mutex_lock(&clock->extreg_lock); 413 414 err = tdr_write(1, phydev, ts, PTP_LOAD_CLK); 415 416 mutex_unlock(&clock->extreg_lock); 417 418 return err; 419 } 420 421 static int ptp_dp83640_enable(struct ptp_clock_info *ptp, 422 struct ptp_clock_request *rq, int on) 423 { 424 struct dp83640_clock *clock = 425 container_of(ptp, struct dp83640_clock, caps); 426 struct phy_device *phydev = clock->chosen->phydev; 427 int index; 428 u16 evnt, event_num, gpio_num; 429 430 switch (rq->type) { 431 case PTP_CLK_REQ_EXTTS: 432 index = rq->extts.index; 433 if (index < 0 || index >= N_EXT_TS) 434 return -EINVAL; 435 event_num = EXT_EVENT + index; 436 evnt = EVNT_WR | (event_num & EVNT_SEL_MASK) << EVNT_SEL_SHIFT; 437 if (on) { 438 gpio_num = gpio_tab[EXTTS0_GPIO + index]; 439 evnt |= (gpio_num & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT; 440 if (rq->extts.flags & PTP_FALLING_EDGE) 441 evnt |= EVNT_FALL; 442 else 443 evnt |= EVNT_RISE; 444 } 445 ext_write(0, phydev, PAGE5, PTP_EVNT, evnt); 446 return 0; 447 448 case PTP_CLK_REQ_PEROUT: 449 if (rq->perout.index != 0) 450 return -EINVAL; 451 periodic_output(clock, rq, on); 452 return 0; 453 454 default: 455 break; 456 } 457 458 return -EOPNOTSUPP; 459 } 460 461 static u8 status_frame_dst[6] = { 0x01, 0x1B, 0x19, 0x00, 0x00, 0x00 }; 462 static u8 status_frame_src[6] = { 0x08, 0x00, 0x17, 0x0B, 0x6B, 0x0F }; 463 464 static void enable_status_frames(struct phy_device *phydev, bool on) 465 { 466 u16 cfg0 = 0, ver; 467 468 if (on) 469 cfg0 = PSF_EVNT_EN | PSF_RXTS_EN | PSF_TXTS_EN | ENDIAN_FLAG; 470 471 ver = (PSF_PTPVER & VERSIONPTP_MASK) << VERSIONPTP_SHIFT; 472 473 ext_write(0, phydev, PAGE5, PSF_CFG0, cfg0); 474 ext_write(0, phydev, PAGE6, PSF_CFG1, ver); 475 476 if (!phydev->attached_dev) { 477 pr_warn("expected to find an attached netdevice\n"); 478 return; 479 } 480 481 if (on) { 482 if (dev_mc_add(phydev->attached_dev, status_frame_dst)) 483 pr_warn("failed to add mc address\n"); 484 } else { 485 if (dev_mc_del(phydev->attached_dev, status_frame_dst)) 486 pr_warn("failed to delete mc address\n"); 487 } 488 } 489 490 static bool is_status_frame(struct sk_buff *skb, int type) 491 { 492 struct ethhdr *h = eth_hdr(skb); 493 494 if (PTP_CLASS_V2_L2 == type && 495 !memcmp(h->h_source, status_frame_src, sizeof(status_frame_src))) 496 return true; 497 else 498 return false; 499 } 500 501 static int expired(struct rxts *rxts) 502 { 503 return time_after(jiffies, rxts->tmo); 504 } 505 506 /* Caller must hold rx_lock. */ 507 static void prune_rx_ts(struct dp83640_private *dp83640) 508 { 509 struct list_head *this, *next; 510 struct rxts *rxts; 511 512 list_for_each_safe(this, next, &dp83640->rxts) { 513 rxts = list_entry(this, struct rxts, list); 514 if (expired(rxts)) { 515 list_del_init(&rxts->list); 516 list_add(&rxts->list, &dp83640->rxpool); 517 } 518 } 519 } 520 521 /* synchronize the phyters so they act as one clock */ 522 523 static void enable_broadcast(struct phy_device *phydev, int init_page, int on) 524 { 525 int val; 526 phy_write(phydev, PAGESEL, 0); 527 val = phy_read(phydev, PHYCR2); 528 if (on) 529 val |= BC_WRITE; 530 else 531 val &= ~BC_WRITE; 532 phy_write(phydev, PHYCR2, val); 533 phy_write(phydev, PAGESEL, init_page); 534 } 535 536 static void recalibrate(struct dp83640_clock *clock) 537 { 538 s64 now, diff; 539 struct phy_txts event_ts; 540 struct timespec ts; 541 struct list_head *this; 542 struct dp83640_private *tmp; 543 struct phy_device *master = clock->chosen->phydev; 544 u16 cal_gpio, cfg0, evnt, ptp_trig, trigger, val; 545 546 trigger = CAL_TRIGGER; 547 cal_gpio = gpio_tab[CALIBRATE_GPIO]; 548 549 mutex_lock(&clock->extreg_lock); 550 551 /* 552 * enable broadcast, disable status frames, enable ptp clock 553 */ 554 list_for_each(this, &clock->phylist) { 555 tmp = list_entry(this, struct dp83640_private, list); 556 enable_broadcast(tmp->phydev, clock->page, 1); 557 tmp->cfg0 = ext_read(tmp->phydev, PAGE5, PSF_CFG0); 558 ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, 0); 559 ext_write(0, tmp->phydev, PAGE4, PTP_CTL, PTP_ENABLE); 560 } 561 enable_broadcast(master, clock->page, 1); 562 cfg0 = ext_read(master, PAGE5, PSF_CFG0); 563 ext_write(0, master, PAGE5, PSF_CFG0, 0); 564 ext_write(0, master, PAGE4, PTP_CTL, PTP_ENABLE); 565 566 /* 567 * enable an event timestamp 568 */ 569 evnt = EVNT_WR | EVNT_RISE | EVNT_SINGLE; 570 evnt |= (CAL_EVENT & EVNT_SEL_MASK) << EVNT_SEL_SHIFT; 571 evnt |= (cal_gpio & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT; 572 573 list_for_each(this, &clock->phylist) { 574 tmp = list_entry(this, struct dp83640_private, list); 575 ext_write(0, tmp->phydev, PAGE5, PTP_EVNT, evnt); 576 } 577 ext_write(0, master, PAGE5, PTP_EVNT, evnt); 578 579 /* 580 * configure a trigger 581 */ 582 ptp_trig = TRIG_WR | TRIG_IF_LATE | TRIG_PULSE; 583 ptp_trig |= (trigger & TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT; 584 ptp_trig |= (cal_gpio & TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT; 585 ext_write(0, master, PAGE5, PTP_TRIG, ptp_trig); 586 587 /* load trigger */ 588 val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT; 589 val |= TRIG_LOAD; 590 ext_write(0, master, PAGE4, PTP_CTL, val); 591 592 /* enable trigger */ 593 val &= ~TRIG_LOAD; 594 val |= TRIG_EN; 595 ext_write(0, master, PAGE4, PTP_CTL, val); 596 597 /* disable trigger */ 598 val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT; 599 val |= TRIG_DIS; 600 ext_write(0, master, PAGE4, PTP_CTL, val); 601 602 /* 603 * read out and correct offsets 604 */ 605 val = ext_read(master, PAGE4, PTP_STS); 606 pr_info("master PTP_STS 0x%04hx\n", val); 607 val = ext_read(master, PAGE4, PTP_ESTS); 608 pr_info("master PTP_ESTS 0x%04hx\n", val); 609 event_ts.ns_lo = ext_read(master, PAGE4, PTP_EDATA); 610 event_ts.ns_hi = ext_read(master, PAGE4, PTP_EDATA); 611 event_ts.sec_lo = ext_read(master, PAGE4, PTP_EDATA); 612 event_ts.sec_hi = ext_read(master, PAGE4, PTP_EDATA); 613 now = phy2txts(&event_ts); 614 615 list_for_each(this, &clock->phylist) { 616 tmp = list_entry(this, struct dp83640_private, list); 617 val = ext_read(tmp->phydev, PAGE4, PTP_STS); 618 pr_info("slave PTP_STS 0x%04hx\n", val); 619 val = ext_read(tmp->phydev, PAGE4, PTP_ESTS); 620 pr_info("slave PTP_ESTS 0x%04hx\n", val); 621 event_ts.ns_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA); 622 event_ts.ns_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA); 623 event_ts.sec_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA); 624 event_ts.sec_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA); 625 diff = now - (s64) phy2txts(&event_ts); 626 pr_info("slave offset %lld nanoseconds\n", diff); 627 diff += ADJTIME_FIX; 628 ts = ns_to_timespec(diff); 629 tdr_write(0, tmp->phydev, &ts, PTP_STEP_CLK); 630 } 631 632 /* 633 * restore status frames 634 */ 635 list_for_each(this, &clock->phylist) { 636 tmp = list_entry(this, struct dp83640_private, list); 637 ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, tmp->cfg0); 638 } 639 ext_write(0, master, PAGE5, PSF_CFG0, cfg0); 640 641 mutex_unlock(&clock->extreg_lock); 642 } 643 644 /* time stamping methods */ 645 646 static inline u16 exts_chan_to_edata(int ch) 647 { 648 return 1 << ((ch + EXT_EVENT) * 2); 649 } 650 651 static int decode_evnt(struct dp83640_private *dp83640, 652 void *data, u16 ests) 653 { 654 struct phy_txts *phy_txts; 655 struct ptp_clock_event event; 656 int i, parsed; 657 int words = (ests >> EVNT_TS_LEN_SHIFT) & EVNT_TS_LEN_MASK; 658 u16 ext_status = 0; 659 660 if (ests & MULT_EVNT) { 661 ext_status = *(u16 *) data; 662 data += sizeof(ext_status); 663 } 664 665 phy_txts = data; 666 667 switch (words) { /* fall through in every case */ 668 case 3: 669 dp83640->edata.sec_hi = phy_txts->sec_hi; 670 case 2: 671 dp83640->edata.sec_lo = phy_txts->sec_lo; 672 case 1: 673 dp83640->edata.ns_hi = phy_txts->ns_hi; 674 case 0: 675 dp83640->edata.ns_lo = phy_txts->ns_lo; 676 } 677 678 if (ext_status) { 679 parsed = words + 2; 680 } else { 681 parsed = words + 1; 682 i = ((ests >> EVNT_NUM_SHIFT) & EVNT_NUM_MASK) - EXT_EVENT; 683 ext_status = exts_chan_to_edata(i); 684 } 685 686 event.type = PTP_CLOCK_EXTTS; 687 event.timestamp = phy2txts(&dp83640->edata); 688 689 for (i = 0; i < N_EXT_TS; i++) { 690 if (ext_status & exts_chan_to_edata(i)) { 691 event.index = i; 692 ptp_clock_event(dp83640->clock->ptp_clock, &event); 693 } 694 } 695 696 return parsed * sizeof(u16); 697 } 698 699 static void decode_rxts(struct dp83640_private *dp83640, 700 struct phy_rxts *phy_rxts) 701 { 702 struct rxts *rxts; 703 unsigned long flags; 704 705 spin_lock_irqsave(&dp83640->rx_lock, flags); 706 707 prune_rx_ts(dp83640); 708 709 if (list_empty(&dp83640->rxpool)) { 710 pr_debug("rx timestamp pool is empty\n"); 711 goto out; 712 } 713 rxts = list_first_entry(&dp83640->rxpool, struct rxts, list); 714 list_del_init(&rxts->list); 715 phy2rxts(phy_rxts, rxts); 716 list_add_tail(&rxts->list, &dp83640->rxts); 717 out: 718 spin_unlock_irqrestore(&dp83640->rx_lock, flags); 719 } 720 721 static void decode_txts(struct dp83640_private *dp83640, 722 struct phy_txts *phy_txts) 723 { 724 struct skb_shared_hwtstamps shhwtstamps; 725 struct sk_buff *skb; 726 u64 ns; 727 728 /* We must already have the skb that triggered this. */ 729 730 skb = skb_dequeue(&dp83640->tx_queue); 731 732 if (!skb) { 733 pr_debug("have timestamp but tx_queue empty\n"); 734 return; 735 } 736 ns = phy2txts(phy_txts); 737 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 738 shhwtstamps.hwtstamp = ns_to_ktime(ns); 739 skb_complete_tx_timestamp(skb, &shhwtstamps); 740 } 741 742 static void decode_status_frame(struct dp83640_private *dp83640, 743 struct sk_buff *skb) 744 { 745 struct phy_rxts *phy_rxts; 746 struct phy_txts *phy_txts; 747 u8 *ptr; 748 int len, size; 749 u16 ests, type; 750 751 ptr = skb->data + 2; 752 753 for (len = skb_headlen(skb) - 2; len > sizeof(type); len -= size) { 754 755 type = *(u16 *)ptr; 756 ests = type & 0x0fff; 757 type = type & 0xf000; 758 len -= sizeof(type); 759 ptr += sizeof(type); 760 761 if (PSF_RX == type && len >= sizeof(*phy_rxts)) { 762 763 phy_rxts = (struct phy_rxts *) ptr; 764 decode_rxts(dp83640, phy_rxts); 765 size = sizeof(*phy_rxts); 766 767 } else if (PSF_TX == type && len >= sizeof(*phy_txts)) { 768 769 phy_txts = (struct phy_txts *) ptr; 770 decode_txts(dp83640, phy_txts); 771 size = sizeof(*phy_txts); 772 773 } else if (PSF_EVNT == type && len >= sizeof(*phy_txts)) { 774 775 size = decode_evnt(dp83640, ptr, ests); 776 777 } else { 778 size = 0; 779 break; 780 } 781 ptr += size; 782 } 783 } 784 785 static int is_sync(struct sk_buff *skb, int type) 786 { 787 u8 *data = skb->data, *msgtype; 788 unsigned int offset = 0; 789 790 switch (type) { 791 case PTP_CLASS_V1_IPV4: 792 case PTP_CLASS_V2_IPV4: 793 offset = ETH_HLEN + IPV4_HLEN(data) + UDP_HLEN; 794 break; 795 case PTP_CLASS_V1_IPV6: 796 case PTP_CLASS_V2_IPV6: 797 offset = OFF_PTP6; 798 break; 799 case PTP_CLASS_V2_L2: 800 offset = ETH_HLEN; 801 break; 802 case PTP_CLASS_V2_VLAN: 803 offset = ETH_HLEN + VLAN_HLEN; 804 break; 805 default: 806 return 0; 807 } 808 809 if (type & PTP_CLASS_V1) 810 offset += OFF_PTP_CONTROL; 811 812 if (skb->len < offset + 1) 813 return 0; 814 815 msgtype = data + offset; 816 817 return (*msgtype & 0xf) == 0; 818 } 819 820 static int match(struct sk_buff *skb, unsigned int type, struct rxts *rxts) 821 { 822 u16 *seqid; 823 unsigned int offset; 824 u8 *msgtype, *data = skb_mac_header(skb); 825 826 /* check sequenceID, messageType, 12 bit hash of offset 20-29 */ 827 828 switch (type) { 829 case PTP_CLASS_V1_IPV4: 830 case PTP_CLASS_V2_IPV4: 831 offset = ETH_HLEN + IPV4_HLEN(data) + UDP_HLEN; 832 break; 833 case PTP_CLASS_V1_IPV6: 834 case PTP_CLASS_V2_IPV6: 835 offset = OFF_PTP6; 836 break; 837 case PTP_CLASS_V2_L2: 838 offset = ETH_HLEN; 839 break; 840 case PTP_CLASS_V2_VLAN: 841 offset = ETH_HLEN + VLAN_HLEN; 842 break; 843 default: 844 return 0; 845 } 846 847 if (skb->len + ETH_HLEN < offset + OFF_PTP_SEQUENCE_ID + sizeof(*seqid)) 848 return 0; 849 850 if (unlikely(type & PTP_CLASS_V1)) 851 msgtype = data + offset + OFF_PTP_CONTROL; 852 else 853 msgtype = data + offset; 854 855 seqid = (u16 *)(data + offset + OFF_PTP_SEQUENCE_ID); 856 857 return rxts->msgtype == (*msgtype & 0xf) && 858 rxts->seqid == ntohs(*seqid); 859 } 860 861 static void dp83640_free_clocks(void) 862 { 863 struct dp83640_clock *clock; 864 struct list_head *this, *next; 865 866 mutex_lock(&phyter_clocks_lock); 867 868 list_for_each_safe(this, next, &phyter_clocks) { 869 clock = list_entry(this, struct dp83640_clock, list); 870 if (!list_empty(&clock->phylist)) { 871 pr_warn("phy list non-empty while unloading\n"); 872 BUG(); 873 } 874 list_del(&clock->list); 875 mutex_destroy(&clock->extreg_lock); 876 mutex_destroy(&clock->clock_lock); 877 put_device(&clock->bus->dev); 878 kfree(clock); 879 } 880 881 mutex_unlock(&phyter_clocks_lock); 882 } 883 884 static void dp83640_clock_init(struct dp83640_clock *clock, struct mii_bus *bus) 885 { 886 INIT_LIST_HEAD(&clock->list); 887 clock->bus = bus; 888 mutex_init(&clock->extreg_lock); 889 mutex_init(&clock->clock_lock); 890 INIT_LIST_HEAD(&clock->phylist); 891 clock->caps.owner = THIS_MODULE; 892 sprintf(clock->caps.name, "dp83640 timer"); 893 clock->caps.max_adj = 1953124; 894 clock->caps.n_alarm = 0; 895 clock->caps.n_ext_ts = N_EXT_TS; 896 clock->caps.n_per_out = 1; 897 clock->caps.pps = 0; 898 clock->caps.adjfreq = ptp_dp83640_adjfreq; 899 clock->caps.adjtime = ptp_dp83640_adjtime; 900 clock->caps.gettime = ptp_dp83640_gettime; 901 clock->caps.settime = ptp_dp83640_settime; 902 clock->caps.enable = ptp_dp83640_enable; 903 /* 904 * Get a reference to this bus instance. 905 */ 906 get_device(&bus->dev); 907 } 908 909 static int choose_this_phy(struct dp83640_clock *clock, 910 struct phy_device *phydev) 911 { 912 if (chosen_phy == -1 && !clock->chosen) 913 return 1; 914 915 if (chosen_phy == phydev->addr) 916 return 1; 917 918 return 0; 919 } 920 921 static struct dp83640_clock *dp83640_clock_get(struct dp83640_clock *clock) 922 { 923 if (clock) 924 mutex_lock(&clock->clock_lock); 925 return clock; 926 } 927 928 /* 929 * Look up and lock a clock by bus instance. 930 * If there is no clock for this bus, then create it first. 931 */ 932 static struct dp83640_clock *dp83640_clock_get_bus(struct mii_bus *bus) 933 { 934 struct dp83640_clock *clock = NULL, *tmp; 935 struct list_head *this; 936 937 mutex_lock(&phyter_clocks_lock); 938 939 list_for_each(this, &phyter_clocks) { 940 tmp = list_entry(this, struct dp83640_clock, list); 941 if (tmp->bus == bus) { 942 clock = tmp; 943 break; 944 } 945 } 946 if (clock) 947 goto out; 948 949 clock = kzalloc(sizeof(struct dp83640_clock), GFP_KERNEL); 950 if (!clock) 951 goto out; 952 953 dp83640_clock_init(clock, bus); 954 list_add_tail(&phyter_clocks, &clock->list); 955 out: 956 mutex_unlock(&phyter_clocks_lock); 957 958 return dp83640_clock_get(clock); 959 } 960 961 static void dp83640_clock_put(struct dp83640_clock *clock) 962 { 963 mutex_unlock(&clock->clock_lock); 964 } 965 966 static int dp83640_probe(struct phy_device *phydev) 967 { 968 struct dp83640_clock *clock; 969 struct dp83640_private *dp83640; 970 int err = -ENOMEM, i; 971 972 if (phydev->addr == BROADCAST_ADDR) 973 return 0; 974 975 clock = dp83640_clock_get_bus(phydev->bus); 976 if (!clock) 977 goto no_clock; 978 979 dp83640 = kzalloc(sizeof(struct dp83640_private), GFP_KERNEL); 980 if (!dp83640) 981 goto no_memory; 982 983 dp83640->phydev = phydev; 984 INIT_WORK(&dp83640->ts_work, rx_timestamp_work); 985 986 INIT_LIST_HEAD(&dp83640->rxts); 987 INIT_LIST_HEAD(&dp83640->rxpool); 988 for (i = 0; i < MAX_RXTS; i++) 989 list_add(&dp83640->rx_pool_data[i].list, &dp83640->rxpool); 990 991 phydev->priv = dp83640; 992 993 spin_lock_init(&dp83640->rx_lock); 994 skb_queue_head_init(&dp83640->rx_queue); 995 skb_queue_head_init(&dp83640->tx_queue); 996 997 dp83640->clock = clock; 998 999 if (choose_this_phy(clock, phydev)) { 1000 clock->chosen = dp83640; 1001 clock->ptp_clock = ptp_clock_register(&clock->caps, &phydev->dev); 1002 if (IS_ERR(clock->ptp_clock)) { 1003 err = PTR_ERR(clock->ptp_clock); 1004 goto no_register; 1005 } 1006 } else 1007 list_add_tail(&dp83640->list, &clock->phylist); 1008 1009 dp83640_clock_put(clock); 1010 return 0; 1011 1012 no_register: 1013 clock->chosen = NULL; 1014 kfree(dp83640); 1015 no_memory: 1016 dp83640_clock_put(clock); 1017 no_clock: 1018 return err; 1019 } 1020 1021 static void dp83640_remove(struct phy_device *phydev) 1022 { 1023 struct dp83640_clock *clock; 1024 struct list_head *this, *next; 1025 struct dp83640_private *tmp, *dp83640 = phydev->priv; 1026 struct sk_buff *skb; 1027 1028 if (phydev->addr == BROADCAST_ADDR) 1029 return; 1030 1031 enable_status_frames(phydev, false); 1032 cancel_work_sync(&dp83640->ts_work); 1033 1034 while ((skb = skb_dequeue(&dp83640->rx_queue)) != NULL) 1035 kfree_skb(skb); 1036 1037 while ((skb = skb_dequeue(&dp83640->tx_queue)) != NULL) 1038 skb_complete_tx_timestamp(skb, NULL); 1039 1040 clock = dp83640_clock_get(dp83640->clock); 1041 1042 if (dp83640 == clock->chosen) { 1043 ptp_clock_unregister(clock->ptp_clock); 1044 clock->chosen = NULL; 1045 } else { 1046 list_for_each_safe(this, next, &clock->phylist) { 1047 tmp = list_entry(this, struct dp83640_private, list); 1048 if (tmp == dp83640) { 1049 list_del_init(&tmp->list); 1050 break; 1051 } 1052 } 1053 } 1054 1055 dp83640_clock_put(clock); 1056 kfree(dp83640); 1057 } 1058 1059 static int dp83640_config_init(struct phy_device *phydev) 1060 { 1061 struct dp83640_private *dp83640 = phydev->priv; 1062 struct dp83640_clock *clock = dp83640->clock; 1063 1064 if (clock->chosen && !list_empty(&clock->phylist)) 1065 recalibrate(clock); 1066 else 1067 enable_broadcast(phydev, clock->page, 1); 1068 1069 enable_status_frames(phydev, true); 1070 ext_write(0, phydev, PAGE4, PTP_CTL, PTP_ENABLE); 1071 return 0; 1072 } 1073 1074 static int dp83640_ack_interrupt(struct phy_device *phydev) 1075 { 1076 int err = phy_read(phydev, MII_DP83640_MISR); 1077 1078 if (err < 0) 1079 return err; 1080 1081 return 0; 1082 } 1083 1084 static int dp83640_config_intr(struct phy_device *phydev) 1085 { 1086 int micr; 1087 int misr; 1088 int err; 1089 1090 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 1091 misr = phy_read(phydev, MII_DP83640_MISR); 1092 if (misr < 0) 1093 return misr; 1094 misr |= 1095 (MII_DP83640_MISR_ANC_INT_EN | 1096 MII_DP83640_MISR_DUP_INT_EN | 1097 MII_DP83640_MISR_SPD_INT_EN | 1098 MII_DP83640_MISR_LINK_INT_EN); 1099 err = phy_write(phydev, MII_DP83640_MISR, misr); 1100 if (err < 0) 1101 return err; 1102 1103 micr = phy_read(phydev, MII_DP83640_MICR); 1104 if (micr < 0) 1105 return micr; 1106 micr |= 1107 (MII_DP83640_MICR_OE | 1108 MII_DP83640_MICR_IE); 1109 return phy_write(phydev, MII_DP83640_MICR, micr); 1110 } else { 1111 micr = phy_read(phydev, MII_DP83640_MICR); 1112 if (micr < 0) 1113 return micr; 1114 micr &= 1115 ~(MII_DP83640_MICR_OE | 1116 MII_DP83640_MICR_IE); 1117 err = phy_write(phydev, MII_DP83640_MICR, micr); 1118 if (err < 0) 1119 return err; 1120 1121 misr = phy_read(phydev, MII_DP83640_MISR); 1122 if (misr < 0) 1123 return misr; 1124 misr &= 1125 ~(MII_DP83640_MISR_ANC_INT_EN | 1126 MII_DP83640_MISR_DUP_INT_EN | 1127 MII_DP83640_MISR_SPD_INT_EN | 1128 MII_DP83640_MISR_LINK_INT_EN); 1129 return phy_write(phydev, MII_DP83640_MISR, misr); 1130 } 1131 } 1132 1133 static int dp83640_hwtstamp(struct phy_device *phydev, struct ifreq *ifr) 1134 { 1135 struct dp83640_private *dp83640 = phydev->priv; 1136 struct hwtstamp_config cfg; 1137 u16 txcfg0, rxcfg0; 1138 1139 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 1140 return -EFAULT; 1141 1142 if (cfg.flags) /* reserved for future extensions */ 1143 return -EINVAL; 1144 1145 if (cfg.tx_type < 0 || cfg.tx_type > HWTSTAMP_TX_ONESTEP_SYNC) 1146 return -ERANGE; 1147 1148 dp83640->hwts_tx_en = cfg.tx_type; 1149 1150 switch (cfg.rx_filter) { 1151 case HWTSTAMP_FILTER_NONE: 1152 dp83640->hwts_rx_en = 0; 1153 dp83640->layer = 0; 1154 dp83640->version = 0; 1155 break; 1156 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 1157 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 1158 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 1159 dp83640->hwts_rx_en = 1; 1160 dp83640->layer = LAYER4; 1161 dp83640->version = 1; 1162 break; 1163 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1164 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1165 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1166 dp83640->hwts_rx_en = 1; 1167 dp83640->layer = LAYER4; 1168 dp83640->version = 2; 1169 break; 1170 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1171 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1172 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1173 dp83640->hwts_rx_en = 1; 1174 dp83640->layer = LAYER2; 1175 dp83640->version = 2; 1176 break; 1177 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1178 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1179 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1180 dp83640->hwts_rx_en = 1; 1181 dp83640->layer = LAYER4|LAYER2; 1182 dp83640->version = 2; 1183 break; 1184 default: 1185 return -ERANGE; 1186 } 1187 1188 txcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT; 1189 rxcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT; 1190 1191 if (dp83640->layer & LAYER2) { 1192 txcfg0 |= TX_L2_EN; 1193 rxcfg0 |= RX_L2_EN; 1194 } 1195 if (dp83640->layer & LAYER4) { 1196 txcfg0 |= TX_IPV6_EN | TX_IPV4_EN; 1197 rxcfg0 |= RX_IPV6_EN | RX_IPV4_EN; 1198 } 1199 1200 if (dp83640->hwts_tx_en) 1201 txcfg0 |= TX_TS_EN; 1202 1203 if (dp83640->hwts_tx_en == HWTSTAMP_TX_ONESTEP_SYNC) 1204 txcfg0 |= SYNC_1STEP | CHK_1STEP; 1205 1206 if (dp83640->hwts_rx_en) 1207 rxcfg0 |= RX_TS_EN; 1208 1209 mutex_lock(&dp83640->clock->extreg_lock); 1210 1211 ext_write(0, phydev, PAGE5, PTP_TXCFG0, txcfg0); 1212 ext_write(0, phydev, PAGE5, PTP_RXCFG0, rxcfg0); 1213 1214 mutex_unlock(&dp83640->clock->extreg_lock); 1215 1216 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1217 } 1218 1219 static void rx_timestamp_work(struct work_struct *work) 1220 { 1221 struct dp83640_private *dp83640 = 1222 container_of(work, struct dp83640_private, ts_work); 1223 struct list_head *this, *next; 1224 struct rxts *rxts; 1225 struct skb_shared_hwtstamps *shhwtstamps; 1226 struct sk_buff *skb; 1227 unsigned int type; 1228 unsigned long flags; 1229 1230 /* Deliver each deferred packet, with or without a time stamp. */ 1231 1232 while ((skb = skb_dequeue(&dp83640->rx_queue)) != NULL) { 1233 type = SKB_PTP_TYPE(skb); 1234 spin_lock_irqsave(&dp83640->rx_lock, flags); 1235 list_for_each_safe(this, next, &dp83640->rxts) { 1236 rxts = list_entry(this, struct rxts, list); 1237 if (match(skb, type, rxts)) { 1238 shhwtstamps = skb_hwtstamps(skb); 1239 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 1240 shhwtstamps->hwtstamp = ns_to_ktime(rxts->ns); 1241 list_del_init(&rxts->list); 1242 list_add(&rxts->list, &dp83640->rxpool); 1243 break; 1244 } 1245 } 1246 spin_unlock_irqrestore(&dp83640->rx_lock, flags); 1247 netif_rx_ni(skb); 1248 } 1249 1250 /* Clear out expired time stamps. */ 1251 1252 spin_lock_irqsave(&dp83640->rx_lock, flags); 1253 prune_rx_ts(dp83640); 1254 spin_unlock_irqrestore(&dp83640->rx_lock, flags); 1255 } 1256 1257 static bool dp83640_rxtstamp(struct phy_device *phydev, 1258 struct sk_buff *skb, int type) 1259 { 1260 struct dp83640_private *dp83640 = phydev->priv; 1261 1262 if (!dp83640->hwts_rx_en) 1263 return false; 1264 1265 if (is_status_frame(skb, type)) { 1266 decode_status_frame(dp83640, skb); 1267 kfree_skb(skb); 1268 return true; 1269 } 1270 1271 SKB_PTP_TYPE(skb) = type; 1272 skb_queue_tail(&dp83640->rx_queue, skb); 1273 schedule_work(&dp83640->ts_work); 1274 1275 return true; 1276 } 1277 1278 static void dp83640_txtstamp(struct phy_device *phydev, 1279 struct sk_buff *skb, int type) 1280 { 1281 struct dp83640_private *dp83640 = phydev->priv; 1282 1283 switch (dp83640->hwts_tx_en) { 1284 1285 case HWTSTAMP_TX_ONESTEP_SYNC: 1286 if (is_sync(skb, type)) { 1287 skb_complete_tx_timestamp(skb, NULL); 1288 return; 1289 } 1290 /* fall through */ 1291 case HWTSTAMP_TX_ON: 1292 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1293 skb_queue_tail(&dp83640->tx_queue, skb); 1294 schedule_work(&dp83640->ts_work); 1295 break; 1296 1297 case HWTSTAMP_TX_OFF: 1298 default: 1299 skb_complete_tx_timestamp(skb, NULL); 1300 break; 1301 } 1302 } 1303 1304 static int dp83640_ts_info(struct phy_device *dev, struct ethtool_ts_info *info) 1305 { 1306 struct dp83640_private *dp83640 = dev->priv; 1307 1308 info->so_timestamping = 1309 SOF_TIMESTAMPING_TX_HARDWARE | 1310 SOF_TIMESTAMPING_RX_HARDWARE | 1311 SOF_TIMESTAMPING_RAW_HARDWARE; 1312 info->phc_index = ptp_clock_index(dp83640->clock->ptp_clock); 1313 info->tx_types = 1314 (1 << HWTSTAMP_TX_OFF) | 1315 (1 << HWTSTAMP_TX_ON) | 1316 (1 << HWTSTAMP_TX_ONESTEP_SYNC); 1317 info->rx_filters = 1318 (1 << HWTSTAMP_FILTER_NONE) | 1319 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) | 1320 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) | 1321 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) | 1322 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) | 1323 (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) | 1324 (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) | 1325 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 1326 (1 << HWTSTAMP_FILTER_PTP_V2_L2_SYNC) | 1327 (1 << HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ) | 1328 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT) | 1329 (1 << HWTSTAMP_FILTER_PTP_V2_SYNC) | 1330 (1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ); 1331 return 0; 1332 } 1333 1334 static struct phy_driver dp83640_driver = { 1335 .phy_id = DP83640_PHY_ID, 1336 .phy_id_mask = 0xfffffff0, 1337 .name = "NatSemi DP83640", 1338 .features = PHY_BASIC_FEATURES, 1339 .flags = PHY_HAS_INTERRUPT, 1340 .probe = dp83640_probe, 1341 .remove = dp83640_remove, 1342 .config_init = dp83640_config_init, 1343 .config_aneg = genphy_config_aneg, 1344 .read_status = genphy_read_status, 1345 .ack_interrupt = dp83640_ack_interrupt, 1346 .config_intr = dp83640_config_intr, 1347 .ts_info = dp83640_ts_info, 1348 .hwtstamp = dp83640_hwtstamp, 1349 .rxtstamp = dp83640_rxtstamp, 1350 .txtstamp = dp83640_txtstamp, 1351 .driver = {.owner = THIS_MODULE,} 1352 }; 1353 1354 static int __init dp83640_init(void) 1355 { 1356 return phy_driver_register(&dp83640_driver); 1357 } 1358 1359 static void __exit dp83640_exit(void) 1360 { 1361 dp83640_free_clocks(); 1362 phy_driver_unregister(&dp83640_driver); 1363 } 1364 1365 MODULE_DESCRIPTION("National Semiconductor DP83640 PHY driver"); 1366 MODULE_AUTHOR("Richard Cochran <richardcochran@gmail.at>"); 1367 MODULE_LICENSE("GPL"); 1368 1369 module_init(dp83640_init); 1370 module_exit(dp83640_exit); 1371 1372 static struct mdio_device_id __maybe_unused dp83640_tbl[] = { 1373 { DP83640_PHY_ID, 0xfffffff0 }, 1374 { } 1375 }; 1376 1377 MODULE_DEVICE_TABLE(mdio, dp83640_tbl); 1378