1 /* 2 * Driver for the National Semiconductor DP83640 PHYTER 3 * 4 * Copyright (C) 2010 OMICRON electronics GmbH 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 19 */ 20 21 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 22 23 #include <linux/crc32.h> 24 #include <linux/ethtool.h> 25 #include <linux/kernel.h> 26 #include <linux/list.h> 27 #include <linux/mii.h> 28 #include <linux/module.h> 29 #include <linux/net_tstamp.h> 30 #include <linux/netdevice.h> 31 #include <linux/if_vlan.h> 32 #include <linux/phy.h> 33 #include <linux/ptp_classify.h> 34 #include <linux/ptp_clock_kernel.h> 35 36 #include "dp83640_reg.h" 37 38 #define DP83640_PHY_ID 0x20005ce1 39 #define PAGESEL 0x13 40 #define MAX_RXTS 64 41 #define N_EXT_TS 6 42 #define N_PER_OUT 7 43 #define PSF_PTPVER 2 44 #define PSF_EVNT 0x4000 45 #define PSF_RX 0x2000 46 #define PSF_TX 0x1000 47 #define EXT_EVENT 1 48 #define CAL_EVENT 7 49 #define CAL_TRIGGER 1 50 #define DP83640_N_PINS 12 51 52 #define MII_DP83640_MICR 0x11 53 #define MII_DP83640_MISR 0x12 54 55 #define MII_DP83640_MICR_OE 0x1 56 #define MII_DP83640_MICR_IE 0x2 57 58 #define MII_DP83640_MISR_RHF_INT_EN 0x01 59 #define MII_DP83640_MISR_FHF_INT_EN 0x02 60 #define MII_DP83640_MISR_ANC_INT_EN 0x04 61 #define MII_DP83640_MISR_DUP_INT_EN 0x08 62 #define MII_DP83640_MISR_SPD_INT_EN 0x10 63 #define MII_DP83640_MISR_LINK_INT_EN 0x20 64 #define MII_DP83640_MISR_ED_INT_EN 0x40 65 #define MII_DP83640_MISR_LQ_INT_EN 0x80 66 67 /* phyter seems to miss the mark by 16 ns */ 68 #define ADJTIME_FIX 16 69 70 #define SKB_TIMESTAMP_TIMEOUT 2 /* jiffies */ 71 72 #if defined(__BIG_ENDIAN) 73 #define ENDIAN_FLAG 0 74 #elif defined(__LITTLE_ENDIAN) 75 #define ENDIAN_FLAG PSF_ENDIAN 76 #endif 77 78 struct dp83640_skb_info { 79 int ptp_type; 80 unsigned long tmo; 81 }; 82 83 struct phy_rxts { 84 u16 ns_lo; /* ns[15:0] */ 85 u16 ns_hi; /* overflow[1:0], ns[29:16] */ 86 u16 sec_lo; /* sec[15:0] */ 87 u16 sec_hi; /* sec[31:16] */ 88 u16 seqid; /* sequenceId[15:0] */ 89 u16 msgtype; /* messageType[3:0], hash[11:0] */ 90 }; 91 92 struct phy_txts { 93 u16 ns_lo; /* ns[15:0] */ 94 u16 ns_hi; /* overflow[1:0], ns[29:16] */ 95 u16 sec_lo; /* sec[15:0] */ 96 u16 sec_hi; /* sec[31:16] */ 97 }; 98 99 struct rxts { 100 struct list_head list; 101 unsigned long tmo; 102 u64 ns; 103 u16 seqid; 104 u8 msgtype; 105 u16 hash; 106 }; 107 108 struct dp83640_clock; 109 110 struct dp83640_private { 111 struct list_head list; 112 struct dp83640_clock *clock; 113 struct phy_device *phydev; 114 struct delayed_work ts_work; 115 int hwts_tx_en; 116 int hwts_rx_en; 117 int layer; 118 int version; 119 /* remember state of cfg0 during calibration */ 120 int cfg0; 121 /* remember the last event time stamp */ 122 struct phy_txts edata; 123 /* list of rx timestamps */ 124 struct list_head rxts; 125 struct list_head rxpool; 126 struct rxts rx_pool_data[MAX_RXTS]; 127 /* protects above three fields from concurrent access */ 128 spinlock_t rx_lock; 129 /* queues of incoming and outgoing packets */ 130 struct sk_buff_head rx_queue; 131 struct sk_buff_head tx_queue; 132 }; 133 134 struct dp83640_clock { 135 /* keeps the instance in the 'phyter_clocks' list */ 136 struct list_head list; 137 /* we create one clock instance per MII bus */ 138 struct mii_bus *bus; 139 /* protects extended registers from concurrent access */ 140 struct mutex extreg_lock; 141 /* remembers which page was last selected */ 142 int page; 143 /* our advertised capabilities */ 144 struct ptp_clock_info caps; 145 /* protects the three fields below from concurrent access */ 146 struct mutex clock_lock; 147 /* the one phyter from which we shall read */ 148 struct dp83640_private *chosen; 149 /* list of the other attached phyters, not chosen */ 150 struct list_head phylist; 151 /* reference to our PTP hardware clock */ 152 struct ptp_clock *ptp_clock; 153 }; 154 155 /* globals */ 156 157 enum { 158 CALIBRATE_GPIO, 159 PEROUT_GPIO, 160 EXTTS0_GPIO, 161 EXTTS1_GPIO, 162 EXTTS2_GPIO, 163 EXTTS3_GPIO, 164 EXTTS4_GPIO, 165 EXTTS5_GPIO, 166 GPIO_TABLE_SIZE 167 }; 168 169 static int chosen_phy = -1; 170 static ushort gpio_tab[GPIO_TABLE_SIZE] = { 171 1, 2, 3, 4, 8, 9, 10, 11 172 }; 173 174 module_param(chosen_phy, int, 0444); 175 module_param_array(gpio_tab, ushort, NULL, 0444); 176 177 MODULE_PARM_DESC(chosen_phy, \ 178 "The address of the PHY to use for the ancillary clock features"); 179 MODULE_PARM_DESC(gpio_tab, \ 180 "Which GPIO line to use for which purpose: cal,perout,extts1,...,extts6"); 181 182 static void dp83640_gpio_defaults(struct ptp_pin_desc *pd) 183 { 184 int i, index; 185 186 for (i = 0; i < DP83640_N_PINS; i++) { 187 snprintf(pd[i].name, sizeof(pd[i].name), "GPIO%d", 1 + i); 188 pd[i].index = i; 189 } 190 191 for (i = 0; i < GPIO_TABLE_SIZE; i++) { 192 if (gpio_tab[i] < 1 || gpio_tab[i] > DP83640_N_PINS) { 193 pr_err("gpio_tab[%d]=%hu out of range", i, gpio_tab[i]); 194 return; 195 } 196 } 197 198 index = gpio_tab[CALIBRATE_GPIO] - 1; 199 pd[index].func = PTP_PF_PHYSYNC; 200 pd[index].chan = 0; 201 202 index = gpio_tab[PEROUT_GPIO] - 1; 203 pd[index].func = PTP_PF_PEROUT; 204 pd[index].chan = 0; 205 206 for (i = EXTTS0_GPIO; i < GPIO_TABLE_SIZE; i++) { 207 index = gpio_tab[i] - 1; 208 pd[index].func = PTP_PF_EXTTS; 209 pd[index].chan = i - EXTTS0_GPIO; 210 } 211 } 212 213 /* a list of clocks and a mutex to protect it */ 214 static LIST_HEAD(phyter_clocks); 215 static DEFINE_MUTEX(phyter_clocks_lock); 216 217 static void rx_timestamp_work(struct work_struct *work); 218 219 /* extended register access functions */ 220 221 #define BROADCAST_ADDR 31 222 223 static inline int broadcast_write(struct phy_device *phydev, u32 regnum, 224 u16 val) 225 { 226 return mdiobus_write(phydev->mdio.bus, BROADCAST_ADDR, regnum, val); 227 } 228 229 /* Caller must hold extreg_lock. */ 230 static int ext_read(struct phy_device *phydev, int page, u32 regnum) 231 { 232 struct dp83640_private *dp83640 = phydev->priv; 233 int val; 234 235 if (dp83640->clock->page != page) { 236 broadcast_write(phydev, PAGESEL, page); 237 dp83640->clock->page = page; 238 } 239 val = phy_read(phydev, regnum); 240 241 return val; 242 } 243 244 /* Caller must hold extreg_lock. */ 245 static void ext_write(int broadcast, struct phy_device *phydev, 246 int page, u32 regnum, u16 val) 247 { 248 struct dp83640_private *dp83640 = phydev->priv; 249 250 if (dp83640->clock->page != page) { 251 broadcast_write(phydev, PAGESEL, page); 252 dp83640->clock->page = page; 253 } 254 if (broadcast) 255 broadcast_write(phydev, regnum, val); 256 else 257 phy_write(phydev, regnum, val); 258 } 259 260 /* Caller must hold extreg_lock. */ 261 static int tdr_write(int bc, struct phy_device *dev, 262 const struct timespec64 *ts, u16 cmd) 263 { 264 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec & 0xffff);/* ns[15:0] */ 265 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec >> 16); /* ns[31:16] */ 266 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec & 0xffff); /* sec[15:0] */ 267 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec >> 16); /* sec[31:16]*/ 268 269 ext_write(bc, dev, PAGE4, PTP_CTL, cmd); 270 271 return 0; 272 } 273 274 /* convert phy timestamps into driver timestamps */ 275 276 static void phy2rxts(struct phy_rxts *p, struct rxts *rxts) 277 { 278 u32 sec; 279 280 sec = p->sec_lo; 281 sec |= p->sec_hi << 16; 282 283 rxts->ns = p->ns_lo; 284 rxts->ns |= (p->ns_hi & 0x3fff) << 16; 285 rxts->ns += ((u64)sec) * 1000000000ULL; 286 rxts->seqid = p->seqid; 287 rxts->msgtype = (p->msgtype >> 12) & 0xf; 288 rxts->hash = p->msgtype & 0x0fff; 289 rxts->tmo = jiffies + SKB_TIMESTAMP_TIMEOUT; 290 } 291 292 static u64 phy2txts(struct phy_txts *p) 293 { 294 u64 ns; 295 u32 sec; 296 297 sec = p->sec_lo; 298 sec |= p->sec_hi << 16; 299 300 ns = p->ns_lo; 301 ns |= (p->ns_hi & 0x3fff) << 16; 302 ns += ((u64)sec) * 1000000000ULL; 303 304 return ns; 305 } 306 307 static int periodic_output(struct dp83640_clock *clock, 308 struct ptp_clock_request *clkreq, bool on, 309 int trigger) 310 { 311 struct dp83640_private *dp83640 = clock->chosen; 312 struct phy_device *phydev = dp83640->phydev; 313 u32 sec, nsec, pwidth; 314 u16 gpio, ptp_trig, val; 315 316 if (on) { 317 gpio = 1 + ptp_find_pin(clock->ptp_clock, PTP_PF_PEROUT, 318 trigger); 319 if (gpio < 1) 320 return -EINVAL; 321 } else { 322 gpio = 0; 323 } 324 325 ptp_trig = TRIG_WR | 326 (trigger & TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT | 327 (gpio & TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT | 328 TRIG_PER | 329 TRIG_PULSE; 330 331 val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT; 332 333 if (!on) { 334 val |= TRIG_DIS; 335 mutex_lock(&clock->extreg_lock); 336 ext_write(0, phydev, PAGE5, PTP_TRIG, ptp_trig); 337 ext_write(0, phydev, PAGE4, PTP_CTL, val); 338 mutex_unlock(&clock->extreg_lock); 339 return 0; 340 } 341 342 sec = clkreq->perout.start.sec; 343 nsec = clkreq->perout.start.nsec; 344 pwidth = clkreq->perout.period.sec * 1000000000UL; 345 pwidth += clkreq->perout.period.nsec; 346 pwidth /= 2; 347 348 mutex_lock(&clock->extreg_lock); 349 350 ext_write(0, phydev, PAGE5, PTP_TRIG, ptp_trig); 351 352 /*load trigger*/ 353 val |= TRIG_LOAD; 354 ext_write(0, phydev, PAGE4, PTP_CTL, val); 355 ext_write(0, phydev, PAGE4, PTP_TDR, nsec & 0xffff); /* ns[15:0] */ 356 ext_write(0, phydev, PAGE4, PTP_TDR, nsec >> 16); /* ns[31:16] */ 357 ext_write(0, phydev, PAGE4, PTP_TDR, sec & 0xffff); /* sec[15:0] */ 358 ext_write(0, phydev, PAGE4, PTP_TDR, sec >> 16); /* sec[31:16] */ 359 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth & 0xffff); /* ns[15:0] */ 360 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth >> 16); /* ns[31:16] */ 361 /* Triggers 0 and 1 has programmable pulsewidth2 */ 362 if (trigger < 2) { 363 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth & 0xffff); 364 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth >> 16); 365 } 366 367 /*enable trigger*/ 368 val &= ~TRIG_LOAD; 369 val |= TRIG_EN; 370 ext_write(0, phydev, PAGE4, PTP_CTL, val); 371 372 mutex_unlock(&clock->extreg_lock); 373 return 0; 374 } 375 376 /* ptp clock methods */ 377 378 static int ptp_dp83640_adjfine(struct ptp_clock_info *ptp, long scaled_ppm) 379 { 380 struct dp83640_clock *clock = 381 container_of(ptp, struct dp83640_clock, caps); 382 struct phy_device *phydev = clock->chosen->phydev; 383 u64 rate; 384 int neg_adj = 0; 385 u16 hi, lo; 386 387 if (scaled_ppm < 0) { 388 neg_adj = 1; 389 scaled_ppm = -scaled_ppm; 390 } 391 rate = scaled_ppm; 392 rate <<= 13; 393 rate = div_u64(rate, 15625); 394 395 hi = (rate >> 16) & PTP_RATE_HI_MASK; 396 if (neg_adj) 397 hi |= PTP_RATE_DIR; 398 399 lo = rate & 0xffff; 400 401 mutex_lock(&clock->extreg_lock); 402 403 ext_write(1, phydev, PAGE4, PTP_RATEH, hi); 404 ext_write(1, phydev, PAGE4, PTP_RATEL, lo); 405 406 mutex_unlock(&clock->extreg_lock); 407 408 return 0; 409 } 410 411 static int ptp_dp83640_adjtime(struct ptp_clock_info *ptp, s64 delta) 412 { 413 struct dp83640_clock *clock = 414 container_of(ptp, struct dp83640_clock, caps); 415 struct phy_device *phydev = clock->chosen->phydev; 416 struct timespec64 ts; 417 int err; 418 419 delta += ADJTIME_FIX; 420 421 ts = ns_to_timespec64(delta); 422 423 mutex_lock(&clock->extreg_lock); 424 425 err = tdr_write(1, phydev, &ts, PTP_STEP_CLK); 426 427 mutex_unlock(&clock->extreg_lock); 428 429 return err; 430 } 431 432 static int ptp_dp83640_gettime(struct ptp_clock_info *ptp, 433 struct timespec64 *ts) 434 { 435 struct dp83640_clock *clock = 436 container_of(ptp, struct dp83640_clock, caps); 437 struct phy_device *phydev = clock->chosen->phydev; 438 unsigned int val[4]; 439 440 mutex_lock(&clock->extreg_lock); 441 442 ext_write(0, phydev, PAGE4, PTP_CTL, PTP_RD_CLK); 443 444 val[0] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[15:0] */ 445 val[1] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[31:16] */ 446 val[2] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[15:0] */ 447 val[3] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[31:16] */ 448 449 mutex_unlock(&clock->extreg_lock); 450 451 ts->tv_nsec = val[0] | (val[1] << 16); 452 ts->tv_sec = val[2] | (val[3] << 16); 453 454 return 0; 455 } 456 457 static int ptp_dp83640_settime(struct ptp_clock_info *ptp, 458 const struct timespec64 *ts) 459 { 460 struct dp83640_clock *clock = 461 container_of(ptp, struct dp83640_clock, caps); 462 struct phy_device *phydev = clock->chosen->phydev; 463 int err; 464 465 mutex_lock(&clock->extreg_lock); 466 467 err = tdr_write(1, phydev, ts, PTP_LOAD_CLK); 468 469 mutex_unlock(&clock->extreg_lock); 470 471 return err; 472 } 473 474 static int ptp_dp83640_enable(struct ptp_clock_info *ptp, 475 struct ptp_clock_request *rq, int on) 476 { 477 struct dp83640_clock *clock = 478 container_of(ptp, struct dp83640_clock, caps); 479 struct phy_device *phydev = clock->chosen->phydev; 480 unsigned int index; 481 u16 evnt, event_num, gpio_num; 482 483 switch (rq->type) { 484 case PTP_CLK_REQ_EXTTS: 485 index = rq->extts.index; 486 if (index >= N_EXT_TS) 487 return -EINVAL; 488 event_num = EXT_EVENT + index; 489 evnt = EVNT_WR | (event_num & EVNT_SEL_MASK) << EVNT_SEL_SHIFT; 490 if (on) { 491 gpio_num = 1 + ptp_find_pin(clock->ptp_clock, 492 PTP_PF_EXTTS, index); 493 if (gpio_num < 1) 494 return -EINVAL; 495 evnt |= (gpio_num & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT; 496 if (rq->extts.flags & PTP_FALLING_EDGE) 497 evnt |= EVNT_FALL; 498 else 499 evnt |= EVNT_RISE; 500 } 501 mutex_lock(&clock->extreg_lock); 502 ext_write(0, phydev, PAGE5, PTP_EVNT, evnt); 503 mutex_unlock(&clock->extreg_lock); 504 return 0; 505 506 case PTP_CLK_REQ_PEROUT: 507 if (rq->perout.index >= N_PER_OUT) 508 return -EINVAL; 509 return periodic_output(clock, rq, on, rq->perout.index); 510 511 default: 512 break; 513 } 514 515 return -EOPNOTSUPP; 516 } 517 518 static int ptp_dp83640_verify(struct ptp_clock_info *ptp, unsigned int pin, 519 enum ptp_pin_function func, unsigned int chan) 520 { 521 struct dp83640_clock *clock = 522 container_of(ptp, struct dp83640_clock, caps); 523 524 if (clock->caps.pin_config[pin].func == PTP_PF_PHYSYNC && 525 !list_empty(&clock->phylist)) 526 return 1; 527 528 if (func == PTP_PF_PHYSYNC) 529 return 1; 530 531 return 0; 532 } 533 534 static u8 status_frame_dst[6] = { 0x01, 0x1B, 0x19, 0x00, 0x00, 0x00 }; 535 static u8 status_frame_src[6] = { 0x08, 0x00, 0x17, 0x0B, 0x6B, 0x0F }; 536 537 static void enable_status_frames(struct phy_device *phydev, bool on) 538 { 539 struct dp83640_private *dp83640 = phydev->priv; 540 struct dp83640_clock *clock = dp83640->clock; 541 u16 cfg0 = 0, ver; 542 543 if (on) 544 cfg0 = PSF_EVNT_EN | PSF_RXTS_EN | PSF_TXTS_EN | ENDIAN_FLAG; 545 546 ver = (PSF_PTPVER & VERSIONPTP_MASK) << VERSIONPTP_SHIFT; 547 548 mutex_lock(&clock->extreg_lock); 549 550 ext_write(0, phydev, PAGE5, PSF_CFG0, cfg0); 551 ext_write(0, phydev, PAGE6, PSF_CFG1, ver); 552 553 mutex_unlock(&clock->extreg_lock); 554 555 if (!phydev->attached_dev) { 556 pr_warn("expected to find an attached netdevice\n"); 557 return; 558 } 559 560 if (on) { 561 if (dev_mc_add(phydev->attached_dev, status_frame_dst)) 562 pr_warn("failed to add mc address\n"); 563 } else { 564 if (dev_mc_del(phydev->attached_dev, status_frame_dst)) 565 pr_warn("failed to delete mc address\n"); 566 } 567 } 568 569 static bool is_status_frame(struct sk_buff *skb, int type) 570 { 571 struct ethhdr *h = eth_hdr(skb); 572 573 if (PTP_CLASS_V2_L2 == type && 574 !memcmp(h->h_source, status_frame_src, sizeof(status_frame_src))) 575 return true; 576 else 577 return false; 578 } 579 580 static int expired(struct rxts *rxts) 581 { 582 return time_after(jiffies, rxts->tmo); 583 } 584 585 /* Caller must hold rx_lock. */ 586 static void prune_rx_ts(struct dp83640_private *dp83640) 587 { 588 struct list_head *this, *next; 589 struct rxts *rxts; 590 591 list_for_each_safe(this, next, &dp83640->rxts) { 592 rxts = list_entry(this, struct rxts, list); 593 if (expired(rxts)) { 594 list_del_init(&rxts->list); 595 list_add(&rxts->list, &dp83640->rxpool); 596 } 597 } 598 } 599 600 /* synchronize the phyters so they act as one clock */ 601 602 static void enable_broadcast(struct phy_device *phydev, int init_page, int on) 603 { 604 int val; 605 phy_write(phydev, PAGESEL, 0); 606 val = phy_read(phydev, PHYCR2); 607 if (on) 608 val |= BC_WRITE; 609 else 610 val &= ~BC_WRITE; 611 phy_write(phydev, PHYCR2, val); 612 phy_write(phydev, PAGESEL, init_page); 613 } 614 615 static void recalibrate(struct dp83640_clock *clock) 616 { 617 s64 now, diff; 618 struct phy_txts event_ts; 619 struct timespec64 ts; 620 struct list_head *this; 621 struct dp83640_private *tmp; 622 struct phy_device *master = clock->chosen->phydev; 623 u16 cal_gpio, cfg0, evnt, ptp_trig, trigger, val; 624 625 trigger = CAL_TRIGGER; 626 cal_gpio = 1 + ptp_find_pin(clock->ptp_clock, PTP_PF_PHYSYNC, 0); 627 if (cal_gpio < 1) { 628 pr_err("PHY calibration pin not available - PHY is not calibrated."); 629 return; 630 } 631 632 mutex_lock(&clock->extreg_lock); 633 634 /* 635 * enable broadcast, disable status frames, enable ptp clock 636 */ 637 list_for_each(this, &clock->phylist) { 638 tmp = list_entry(this, struct dp83640_private, list); 639 enable_broadcast(tmp->phydev, clock->page, 1); 640 tmp->cfg0 = ext_read(tmp->phydev, PAGE5, PSF_CFG0); 641 ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, 0); 642 ext_write(0, tmp->phydev, PAGE4, PTP_CTL, PTP_ENABLE); 643 } 644 enable_broadcast(master, clock->page, 1); 645 cfg0 = ext_read(master, PAGE5, PSF_CFG0); 646 ext_write(0, master, PAGE5, PSF_CFG0, 0); 647 ext_write(0, master, PAGE4, PTP_CTL, PTP_ENABLE); 648 649 /* 650 * enable an event timestamp 651 */ 652 evnt = EVNT_WR | EVNT_RISE | EVNT_SINGLE; 653 evnt |= (CAL_EVENT & EVNT_SEL_MASK) << EVNT_SEL_SHIFT; 654 evnt |= (cal_gpio & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT; 655 656 list_for_each(this, &clock->phylist) { 657 tmp = list_entry(this, struct dp83640_private, list); 658 ext_write(0, tmp->phydev, PAGE5, PTP_EVNT, evnt); 659 } 660 ext_write(0, master, PAGE5, PTP_EVNT, evnt); 661 662 /* 663 * configure a trigger 664 */ 665 ptp_trig = TRIG_WR | TRIG_IF_LATE | TRIG_PULSE; 666 ptp_trig |= (trigger & TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT; 667 ptp_trig |= (cal_gpio & TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT; 668 ext_write(0, master, PAGE5, PTP_TRIG, ptp_trig); 669 670 /* load trigger */ 671 val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT; 672 val |= TRIG_LOAD; 673 ext_write(0, master, PAGE4, PTP_CTL, val); 674 675 /* enable trigger */ 676 val &= ~TRIG_LOAD; 677 val |= TRIG_EN; 678 ext_write(0, master, PAGE4, PTP_CTL, val); 679 680 /* disable trigger */ 681 val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT; 682 val |= TRIG_DIS; 683 ext_write(0, master, PAGE4, PTP_CTL, val); 684 685 /* 686 * read out and correct offsets 687 */ 688 val = ext_read(master, PAGE4, PTP_STS); 689 pr_info("master PTP_STS 0x%04hx\n", val); 690 val = ext_read(master, PAGE4, PTP_ESTS); 691 pr_info("master PTP_ESTS 0x%04hx\n", val); 692 event_ts.ns_lo = ext_read(master, PAGE4, PTP_EDATA); 693 event_ts.ns_hi = ext_read(master, PAGE4, PTP_EDATA); 694 event_ts.sec_lo = ext_read(master, PAGE4, PTP_EDATA); 695 event_ts.sec_hi = ext_read(master, PAGE4, PTP_EDATA); 696 now = phy2txts(&event_ts); 697 698 list_for_each(this, &clock->phylist) { 699 tmp = list_entry(this, struct dp83640_private, list); 700 val = ext_read(tmp->phydev, PAGE4, PTP_STS); 701 pr_info("slave PTP_STS 0x%04hx\n", val); 702 val = ext_read(tmp->phydev, PAGE4, PTP_ESTS); 703 pr_info("slave PTP_ESTS 0x%04hx\n", val); 704 event_ts.ns_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA); 705 event_ts.ns_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA); 706 event_ts.sec_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA); 707 event_ts.sec_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA); 708 diff = now - (s64) phy2txts(&event_ts); 709 pr_info("slave offset %lld nanoseconds\n", diff); 710 diff += ADJTIME_FIX; 711 ts = ns_to_timespec64(diff); 712 tdr_write(0, tmp->phydev, &ts, PTP_STEP_CLK); 713 } 714 715 /* 716 * restore status frames 717 */ 718 list_for_each(this, &clock->phylist) { 719 tmp = list_entry(this, struct dp83640_private, list); 720 ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, tmp->cfg0); 721 } 722 ext_write(0, master, PAGE5, PSF_CFG0, cfg0); 723 724 mutex_unlock(&clock->extreg_lock); 725 } 726 727 /* time stamping methods */ 728 729 static inline u16 exts_chan_to_edata(int ch) 730 { 731 return 1 << ((ch + EXT_EVENT) * 2); 732 } 733 734 static int decode_evnt(struct dp83640_private *dp83640, 735 void *data, int len, u16 ests) 736 { 737 struct phy_txts *phy_txts; 738 struct ptp_clock_event event; 739 int i, parsed; 740 int words = (ests >> EVNT_TS_LEN_SHIFT) & EVNT_TS_LEN_MASK; 741 u16 ext_status = 0; 742 743 /* calculate length of the event timestamp status message */ 744 if (ests & MULT_EVNT) 745 parsed = (words + 2) * sizeof(u16); 746 else 747 parsed = (words + 1) * sizeof(u16); 748 749 /* check if enough data is available */ 750 if (len < parsed) 751 return len; 752 753 if (ests & MULT_EVNT) { 754 ext_status = *(u16 *) data; 755 data += sizeof(ext_status); 756 } 757 758 phy_txts = data; 759 760 switch (words) { 761 case 3: 762 dp83640->edata.sec_hi = phy_txts->sec_hi; 763 /* fall through */ 764 case 2: 765 dp83640->edata.sec_lo = phy_txts->sec_lo; 766 /* fall through */ 767 case 1: 768 dp83640->edata.ns_hi = phy_txts->ns_hi; 769 /* fall through */ 770 case 0: 771 dp83640->edata.ns_lo = phy_txts->ns_lo; 772 } 773 774 if (!ext_status) { 775 i = ((ests >> EVNT_NUM_SHIFT) & EVNT_NUM_MASK) - EXT_EVENT; 776 ext_status = exts_chan_to_edata(i); 777 } 778 779 event.type = PTP_CLOCK_EXTTS; 780 event.timestamp = phy2txts(&dp83640->edata); 781 782 /* Compensate for input path and synchronization delays */ 783 event.timestamp -= 35; 784 785 for (i = 0; i < N_EXT_TS; i++) { 786 if (ext_status & exts_chan_to_edata(i)) { 787 event.index = i; 788 ptp_clock_event(dp83640->clock->ptp_clock, &event); 789 } 790 } 791 792 return parsed; 793 } 794 795 #define DP83640_PACKET_HASH_OFFSET 20 796 #define DP83640_PACKET_HASH_LEN 10 797 798 static int match(struct sk_buff *skb, unsigned int type, struct rxts *rxts) 799 { 800 u16 *seqid, hash; 801 unsigned int offset = 0; 802 u8 *msgtype, *data = skb_mac_header(skb); 803 804 /* check sequenceID, messageType, 12 bit hash of offset 20-29 */ 805 806 if (type & PTP_CLASS_VLAN) 807 offset += VLAN_HLEN; 808 809 switch (type & PTP_CLASS_PMASK) { 810 case PTP_CLASS_IPV4: 811 offset += ETH_HLEN + IPV4_HLEN(data + offset) + UDP_HLEN; 812 break; 813 case PTP_CLASS_IPV6: 814 offset += ETH_HLEN + IP6_HLEN + UDP_HLEN; 815 break; 816 case PTP_CLASS_L2: 817 offset += ETH_HLEN; 818 break; 819 default: 820 return 0; 821 } 822 823 if (skb->len + ETH_HLEN < offset + OFF_PTP_SEQUENCE_ID + sizeof(*seqid)) 824 return 0; 825 826 if (unlikely(type & PTP_CLASS_V1)) 827 msgtype = data + offset + OFF_PTP_CONTROL; 828 else 829 msgtype = data + offset; 830 if (rxts->msgtype != (*msgtype & 0xf)) 831 return 0; 832 833 seqid = (u16 *)(data + offset + OFF_PTP_SEQUENCE_ID); 834 if (rxts->seqid != ntohs(*seqid)) 835 return 0; 836 837 hash = ether_crc(DP83640_PACKET_HASH_LEN, 838 data + offset + DP83640_PACKET_HASH_OFFSET) >> 20; 839 if (rxts->hash != hash) 840 return 0; 841 842 return 1; 843 } 844 845 static void decode_rxts(struct dp83640_private *dp83640, 846 struct phy_rxts *phy_rxts) 847 { 848 struct rxts *rxts; 849 struct skb_shared_hwtstamps *shhwtstamps = NULL; 850 struct sk_buff *skb; 851 unsigned long flags; 852 u8 overflow; 853 854 overflow = (phy_rxts->ns_hi >> 14) & 0x3; 855 if (overflow) 856 pr_debug("rx timestamp queue overflow, count %d\n", overflow); 857 858 spin_lock_irqsave(&dp83640->rx_lock, flags); 859 860 prune_rx_ts(dp83640); 861 862 if (list_empty(&dp83640->rxpool)) { 863 pr_debug("rx timestamp pool is empty\n"); 864 goto out; 865 } 866 rxts = list_first_entry(&dp83640->rxpool, struct rxts, list); 867 list_del_init(&rxts->list); 868 phy2rxts(phy_rxts, rxts); 869 870 spin_lock(&dp83640->rx_queue.lock); 871 skb_queue_walk(&dp83640->rx_queue, skb) { 872 struct dp83640_skb_info *skb_info; 873 874 skb_info = (struct dp83640_skb_info *)skb->cb; 875 if (match(skb, skb_info->ptp_type, rxts)) { 876 __skb_unlink(skb, &dp83640->rx_queue); 877 shhwtstamps = skb_hwtstamps(skb); 878 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 879 shhwtstamps->hwtstamp = ns_to_ktime(rxts->ns); 880 list_add(&rxts->list, &dp83640->rxpool); 881 break; 882 } 883 } 884 spin_unlock(&dp83640->rx_queue.lock); 885 886 if (!shhwtstamps) 887 list_add_tail(&rxts->list, &dp83640->rxts); 888 out: 889 spin_unlock_irqrestore(&dp83640->rx_lock, flags); 890 891 if (shhwtstamps) 892 netif_rx_ni(skb); 893 } 894 895 static void decode_txts(struct dp83640_private *dp83640, 896 struct phy_txts *phy_txts) 897 { 898 struct skb_shared_hwtstamps shhwtstamps; 899 struct sk_buff *skb; 900 u64 ns; 901 u8 overflow; 902 903 /* We must already have the skb that triggered this. */ 904 905 skb = skb_dequeue(&dp83640->tx_queue); 906 907 if (!skb) { 908 pr_debug("have timestamp but tx_queue empty\n"); 909 return; 910 } 911 912 overflow = (phy_txts->ns_hi >> 14) & 0x3; 913 if (overflow) { 914 pr_debug("tx timestamp queue overflow, count %d\n", overflow); 915 while (skb) { 916 kfree_skb(skb); 917 skb = skb_dequeue(&dp83640->tx_queue); 918 } 919 return; 920 } 921 922 ns = phy2txts(phy_txts); 923 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 924 shhwtstamps.hwtstamp = ns_to_ktime(ns); 925 skb_complete_tx_timestamp(skb, &shhwtstamps); 926 } 927 928 static void decode_status_frame(struct dp83640_private *dp83640, 929 struct sk_buff *skb) 930 { 931 struct phy_rxts *phy_rxts; 932 struct phy_txts *phy_txts; 933 u8 *ptr; 934 int len, size; 935 u16 ests, type; 936 937 ptr = skb->data + 2; 938 939 for (len = skb_headlen(skb) - 2; len > sizeof(type); len -= size) { 940 941 type = *(u16 *)ptr; 942 ests = type & 0x0fff; 943 type = type & 0xf000; 944 len -= sizeof(type); 945 ptr += sizeof(type); 946 947 if (PSF_RX == type && len >= sizeof(*phy_rxts)) { 948 949 phy_rxts = (struct phy_rxts *) ptr; 950 decode_rxts(dp83640, phy_rxts); 951 size = sizeof(*phy_rxts); 952 953 } else if (PSF_TX == type && len >= sizeof(*phy_txts)) { 954 955 phy_txts = (struct phy_txts *) ptr; 956 decode_txts(dp83640, phy_txts); 957 size = sizeof(*phy_txts); 958 959 } else if (PSF_EVNT == type) { 960 961 size = decode_evnt(dp83640, ptr, len, ests); 962 963 } else { 964 size = 0; 965 break; 966 } 967 ptr += size; 968 } 969 } 970 971 static int is_sync(struct sk_buff *skb, int type) 972 { 973 u8 *data = skb->data, *msgtype; 974 unsigned int offset = 0; 975 976 if (type & PTP_CLASS_VLAN) 977 offset += VLAN_HLEN; 978 979 switch (type & PTP_CLASS_PMASK) { 980 case PTP_CLASS_IPV4: 981 offset += ETH_HLEN + IPV4_HLEN(data + offset) + UDP_HLEN; 982 break; 983 case PTP_CLASS_IPV6: 984 offset += ETH_HLEN + IP6_HLEN + UDP_HLEN; 985 break; 986 case PTP_CLASS_L2: 987 offset += ETH_HLEN; 988 break; 989 default: 990 return 0; 991 } 992 993 if (type & PTP_CLASS_V1) 994 offset += OFF_PTP_CONTROL; 995 996 if (skb->len < offset + 1) 997 return 0; 998 999 msgtype = data + offset; 1000 1001 return (*msgtype & 0xf) == 0; 1002 } 1003 1004 static void dp83640_free_clocks(void) 1005 { 1006 struct dp83640_clock *clock; 1007 struct list_head *this, *next; 1008 1009 mutex_lock(&phyter_clocks_lock); 1010 1011 list_for_each_safe(this, next, &phyter_clocks) { 1012 clock = list_entry(this, struct dp83640_clock, list); 1013 if (!list_empty(&clock->phylist)) { 1014 pr_warn("phy list non-empty while unloading\n"); 1015 BUG(); 1016 } 1017 list_del(&clock->list); 1018 mutex_destroy(&clock->extreg_lock); 1019 mutex_destroy(&clock->clock_lock); 1020 put_device(&clock->bus->dev); 1021 kfree(clock->caps.pin_config); 1022 kfree(clock); 1023 } 1024 1025 mutex_unlock(&phyter_clocks_lock); 1026 } 1027 1028 static void dp83640_clock_init(struct dp83640_clock *clock, struct mii_bus *bus) 1029 { 1030 INIT_LIST_HEAD(&clock->list); 1031 clock->bus = bus; 1032 mutex_init(&clock->extreg_lock); 1033 mutex_init(&clock->clock_lock); 1034 INIT_LIST_HEAD(&clock->phylist); 1035 clock->caps.owner = THIS_MODULE; 1036 sprintf(clock->caps.name, "dp83640 timer"); 1037 clock->caps.max_adj = 1953124; 1038 clock->caps.n_alarm = 0; 1039 clock->caps.n_ext_ts = N_EXT_TS; 1040 clock->caps.n_per_out = N_PER_OUT; 1041 clock->caps.n_pins = DP83640_N_PINS; 1042 clock->caps.pps = 0; 1043 clock->caps.adjfine = ptp_dp83640_adjfine; 1044 clock->caps.adjtime = ptp_dp83640_adjtime; 1045 clock->caps.gettime64 = ptp_dp83640_gettime; 1046 clock->caps.settime64 = ptp_dp83640_settime; 1047 clock->caps.enable = ptp_dp83640_enable; 1048 clock->caps.verify = ptp_dp83640_verify; 1049 /* 1050 * Convert the module param defaults into a dynamic pin configuration. 1051 */ 1052 dp83640_gpio_defaults(clock->caps.pin_config); 1053 /* 1054 * Get a reference to this bus instance. 1055 */ 1056 get_device(&bus->dev); 1057 } 1058 1059 static int choose_this_phy(struct dp83640_clock *clock, 1060 struct phy_device *phydev) 1061 { 1062 if (chosen_phy == -1 && !clock->chosen) 1063 return 1; 1064 1065 if (chosen_phy == phydev->mdio.addr) 1066 return 1; 1067 1068 return 0; 1069 } 1070 1071 static struct dp83640_clock *dp83640_clock_get(struct dp83640_clock *clock) 1072 { 1073 if (clock) 1074 mutex_lock(&clock->clock_lock); 1075 return clock; 1076 } 1077 1078 /* 1079 * Look up and lock a clock by bus instance. 1080 * If there is no clock for this bus, then create it first. 1081 */ 1082 static struct dp83640_clock *dp83640_clock_get_bus(struct mii_bus *bus) 1083 { 1084 struct dp83640_clock *clock = NULL, *tmp; 1085 struct list_head *this; 1086 1087 mutex_lock(&phyter_clocks_lock); 1088 1089 list_for_each(this, &phyter_clocks) { 1090 tmp = list_entry(this, struct dp83640_clock, list); 1091 if (tmp->bus == bus) { 1092 clock = tmp; 1093 break; 1094 } 1095 } 1096 if (clock) 1097 goto out; 1098 1099 clock = kzalloc(sizeof(struct dp83640_clock), GFP_KERNEL); 1100 if (!clock) 1101 goto out; 1102 1103 clock->caps.pin_config = kcalloc(DP83640_N_PINS, 1104 sizeof(struct ptp_pin_desc), 1105 GFP_KERNEL); 1106 if (!clock->caps.pin_config) { 1107 kfree(clock); 1108 clock = NULL; 1109 goto out; 1110 } 1111 dp83640_clock_init(clock, bus); 1112 list_add_tail(&phyter_clocks, &clock->list); 1113 out: 1114 mutex_unlock(&phyter_clocks_lock); 1115 1116 return dp83640_clock_get(clock); 1117 } 1118 1119 static void dp83640_clock_put(struct dp83640_clock *clock) 1120 { 1121 mutex_unlock(&clock->clock_lock); 1122 } 1123 1124 static int dp83640_probe(struct phy_device *phydev) 1125 { 1126 struct dp83640_clock *clock; 1127 struct dp83640_private *dp83640; 1128 int err = -ENOMEM, i; 1129 1130 if (phydev->mdio.addr == BROADCAST_ADDR) 1131 return 0; 1132 1133 clock = dp83640_clock_get_bus(phydev->mdio.bus); 1134 if (!clock) 1135 goto no_clock; 1136 1137 dp83640 = kzalloc(sizeof(struct dp83640_private), GFP_KERNEL); 1138 if (!dp83640) 1139 goto no_memory; 1140 1141 dp83640->phydev = phydev; 1142 INIT_DELAYED_WORK(&dp83640->ts_work, rx_timestamp_work); 1143 1144 INIT_LIST_HEAD(&dp83640->rxts); 1145 INIT_LIST_HEAD(&dp83640->rxpool); 1146 for (i = 0; i < MAX_RXTS; i++) 1147 list_add(&dp83640->rx_pool_data[i].list, &dp83640->rxpool); 1148 1149 phydev->priv = dp83640; 1150 1151 spin_lock_init(&dp83640->rx_lock); 1152 skb_queue_head_init(&dp83640->rx_queue); 1153 skb_queue_head_init(&dp83640->tx_queue); 1154 1155 dp83640->clock = clock; 1156 1157 if (choose_this_phy(clock, phydev)) { 1158 clock->chosen = dp83640; 1159 clock->ptp_clock = ptp_clock_register(&clock->caps, 1160 &phydev->mdio.dev); 1161 if (IS_ERR(clock->ptp_clock)) { 1162 err = PTR_ERR(clock->ptp_clock); 1163 goto no_register; 1164 } 1165 } else 1166 list_add_tail(&dp83640->list, &clock->phylist); 1167 1168 dp83640_clock_put(clock); 1169 return 0; 1170 1171 no_register: 1172 clock->chosen = NULL; 1173 kfree(dp83640); 1174 no_memory: 1175 dp83640_clock_put(clock); 1176 no_clock: 1177 return err; 1178 } 1179 1180 static void dp83640_remove(struct phy_device *phydev) 1181 { 1182 struct dp83640_clock *clock; 1183 struct list_head *this, *next; 1184 struct dp83640_private *tmp, *dp83640 = phydev->priv; 1185 1186 if (phydev->mdio.addr == BROADCAST_ADDR) 1187 return; 1188 1189 enable_status_frames(phydev, false); 1190 cancel_delayed_work_sync(&dp83640->ts_work); 1191 1192 skb_queue_purge(&dp83640->rx_queue); 1193 skb_queue_purge(&dp83640->tx_queue); 1194 1195 clock = dp83640_clock_get(dp83640->clock); 1196 1197 if (dp83640 == clock->chosen) { 1198 ptp_clock_unregister(clock->ptp_clock); 1199 clock->chosen = NULL; 1200 } else { 1201 list_for_each_safe(this, next, &clock->phylist) { 1202 tmp = list_entry(this, struct dp83640_private, list); 1203 if (tmp == dp83640) { 1204 list_del_init(&tmp->list); 1205 break; 1206 } 1207 } 1208 } 1209 1210 dp83640_clock_put(clock); 1211 kfree(dp83640); 1212 } 1213 1214 static int dp83640_soft_reset(struct phy_device *phydev) 1215 { 1216 int ret; 1217 1218 ret = genphy_soft_reset(phydev); 1219 if (ret < 0) 1220 return ret; 1221 1222 /* From DP83640 datasheet: "Software driver code must wait 3 us 1223 * following a software reset before allowing further serial MII 1224 * operations with the DP83640." 1225 */ 1226 udelay(10); /* Taking udelay inaccuracy into account */ 1227 1228 return 0; 1229 } 1230 1231 static int dp83640_config_init(struct phy_device *phydev) 1232 { 1233 struct dp83640_private *dp83640 = phydev->priv; 1234 struct dp83640_clock *clock = dp83640->clock; 1235 1236 if (clock->chosen && !list_empty(&clock->phylist)) 1237 recalibrate(clock); 1238 else { 1239 mutex_lock(&clock->extreg_lock); 1240 enable_broadcast(phydev, clock->page, 1); 1241 mutex_unlock(&clock->extreg_lock); 1242 } 1243 1244 enable_status_frames(phydev, true); 1245 1246 mutex_lock(&clock->extreg_lock); 1247 ext_write(0, phydev, PAGE4, PTP_CTL, PTP_ENABLE); 1248 mutex_unlock(&clock->extreg_lock); 1249 1250 return 0; 1251 } 1252 1253 static int dp83640_ack_interrupt(struct phy_device *phydev) 1254 { 1255 int err = phy_read(phydev, MII_DP83640_MISR); 1256 1257 if (err < 0) 1258 return err; 1259 1260 return 0; 1261 } 1262 1263 static int dp83640_config_intr(struct phy_device *phydev) 1264 { 1265 int micr; 1266 int misr; 1267 int err; 1268 1269 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 1270 misr = phy_read(phydev, MII_DP83640_MISR); 1271 if (misr < 0) 1272 return misr; 1273 misr |= 1274 (MII_DP83640_MISR_ANC_INT_EN | 1275 MII_DP83640_MISR_DUP_INT_EN | 1276 MII_DP83640_MISR_SPD_INT_EN | 1277 MII_DP83640_MISR_LINK_INT_EN); 1278 err = phy_write(phydev, MII_DP83640_MISR, misr); 1279 if (err < 0) 1280 return err; 1281 1282 micr = phy_read(phydev, MII_DP83640_MICR); 1283 if (micr < 0) 1284 return micr; 1285 micr |= 1286 (MII_DP83640_MICR_OE | 1287 MII_DP83640_MICR_IE); 1288 return phy_write(phydev, MII_DP83640_MICR, micr); 1289 } else { 1290 micr = phy_read(phydev, MII_DP83640_MICR); 1291 if (micr < 0) 1292 return micr; 1293 micr &= 1294 ~(MII_DP83640_MICR_OE | 1295 MII_DP83640_MICR_IE); 1296 err = phy_write(phydev, MII_DP83640_MICR, micr); 1297 if (err < 0) 1298 return err; 1299 1300 misr = phy_read(phydev, MII_DP83640_MISR); 1301 if (misr < 0) 1302 return misr; 1303 misr &= 1304 ~(MII_DP83640_MISR_ANC_INT_EN | 1305 MII_DP83640_MISR_DUP_INT_EN | 1306 MII_DP83640_MISR_SPD_INT_EN | 1307 MII_DP83640_MISR_LINK_INT_EN); 1308 return phy_write(phydev, MII_DP83640_MISR, misr); 1309 } 1310 } 1311 1312 static int dp83640_hwtstamp(struct phy_device *phydev, struct ifreq *ifr) 1313 { 1314 struct dp83640_private *dp83640 = phydev->priv; 1315 struct hwtstamp_config cfg; 1316 u16 txcfg0, rxcfg0; 1317 1318 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 1319 return -EFAULT; 1320 1321 if (cfg.flags) /* reserved for future extensions */ 1322 return -EINVAL; 1323 1324 if (cfg.tx_type < 0 || cfg.tx_type > HWTSTAMP_TX_ONESTEP_SYNC) 1325 return -ERANGE; 1326 1327 dp83640->hwts_tx_en = cfg.tx_type; 1328 1329 switch (cfg.rx_filter) { 1330 case HWTSTAMP_FILTER_NONE: 1331 dp83640->hwts_rx_en = 0; 1332 dp83640->layer = 0; 1333 dp83640->version = 0; 1334 break; 1335 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 1336 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 1337 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 1338 dp83640->hwts_rx_en = 1; 1339 dp83640->layer = PTP_CLASS_L4; 1340 dp83640->version = PTP_CLASS_V1; 1341 break; 1342 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1343 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1344 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1345 dp83640->hwts_rx_en = 1; 1346 dp83640->layer = PTP_CLASS_L4; 1347 dp83640->version = PTP_CLASS_V2; 1348 break; 1349 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1350 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1351 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1352 dp83640->hwts_rx_en = 1; 1353 dp83640->layer = PTP_CLASS_L2; 1354 dp83640->version = PTP_CLASS_V2; 1355 break; 1356 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1357 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1358 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1359 dp83640->hwts_rx_en = 1; 1360 dp83640->layer = PTP_CLASS_L4 | PTP_CLASS_L2; 1361 dp83640->version = PTP_CLASS_V2; 1362 break; 1363 default: 1364 return -ERANGE; 1365 } 1366 1367 txcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT; 1368 rxcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT; 1369 1370 if (dp83640->layer & PTP_CLASS_L2) { 1371 txcfg0 |= TX_L2_EN; 1372 rxcfg0 |= RX_L2_EN; 1373 } 1374 if (dp83640->layer & PTP_CLASS_L4) { 1375 txcfg0 |= TX_IPV6_EN | TX_IPV4_EN; 1376 rxcfg0 |= RX_IPV6_EN | RX_IPV4_EN; 1377 } 1378 1379 if (dp83640->hwts_tx_en) 1380 txcfg0 |= TX_TS_EN; 1381 1382 if (dp83640->hwts_tx_en == HWTSTAMP_TX_ONESTEP_SYNC) 1383 txcfg0 |= SYNC_1STEP | CHK_1STEP; 1384 1385 if (dp83640->hwts_rx_en) 1386 rxcfg0 |= RX_TS_EN; 1387 1388 mutex_lock(&dp83640->clock->extreg_lock); 1389 1390 ext_write(0, phydev, PAGE5, PTP_TXCFG0, txcfg0); 1391 ext_write(0, phydev, PAGE5, PTP_RXCFG0, rxcfg0); 1392 1393 mutex_unlock(&dp83640->clock->extreg_lock); 1394 1395 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1396 } 1397 1398 static void rx_timestamp_work(struct work_struct *work) 1399 { 1400 struct dp83640_private *dp83640 = 1401 container_of(work, struct dp83640_private, ts_work.work); 1402 struct sk_buff *skb; 1403 1404 /* Deliver expired packets. */ 1405 while ((skb = skb_dequeue(&dp83640->rx_queue))) { 1406 struct dp83640_skb_info *skb_info; 1407 1408 skb_info = (struct dp83640_skb_info *)skb->cb; 1409 if (!time_after(jiffies, skb_info->tmo)) { 1410 skb_queue_head(&dp83640->rx_queue, skb); 1411 break; 1412 } 1413 1414 netif_rx_ni(skb); 1415 } 1416 1417 if (!skb_queue_empty(&dp83640->rx_queue)) 1418 schedule_delayed_work(&dp83640->ts_work, SKB_TIMESTAMP_TIMEOUT); 1419 } 1420 1421 static bool dp83640_rxtstamp(struct phy_device *phydev, 1422 struct sk_buff *skb, int type) 1423 { 1424 struct dp83640_private *dp83640 = phydev->priv; 1425 struct dp83640_skb_info *skb_info = (struct dp83640_skb_info *)skb->cb; 1426 struct list_head *this, *next; 1427 struct rxts *rxts; 1428 struct skb_shared_hwtstamps *shhwtstamps = NULL; 1429 unsigned long flags; 1430 1431 if (is_status_frame(skb, type)) { 1432 decode_status_frame(dp83640, skb); 1433 kfree_skb(skb); 1434 return true; 1435 } 1436 1437 if (!dp83640->hwts_rx_en) 1438 return false; 1439 1440 if ((type & dp83640->version) == 0 || (type & dp83640->layer) == 0) 1441 return false; 1442 1443 spin_lock_irqsave(&dp83640->rx_lock, flags); 1444 prune_rx_ts(dp83640); 1445 list_for_each_safe(this, next, &dp83640->rxts) { 1446 rxts = list_entry(this, struct rxts, list); 1447 if (match(skb, type, rxts)) { 1448 shhwtstamps = skb_hwtstamps(skb); 1449 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 1450 shhwtstamps->hwtstamp = ns_to_ktime(rxts->ns); 1451 list_del_init(&rxts->list); 1452 list_add(&rxts->list, &dp83640->rxpool); 1453 break; 1454 } 1455 } 1456 spin_unlock_irqrestore(&dp83640->rx_lock, flags); 1457 1458 if (!shhwtstamps) { 1459 skb_info->ptp_type = type; 1460 skb_info->tmo = jiffies + SKB_TIMESTAMP_TIMEOUT; 1461 skb_queue_tail(&dp83640->rx_queue, skb); 1462 schedule_delayed_work(&dp83640->ts_work, SKB_TIMESTAMP_TIMEOUT); 1463 } else { 1464 netif_rx_ni(skb); 1465 } 1466 1467 return true; 1468 } 1469 1470 static void dp83640_txtstamp(struct phy_device *phydev, 1471 struct sk_buff *skb, int type) 1472 { 1473 struct dp83640_private *dp83640 = phydev->priv; 1474 1475 switch (dp83640->hwts_tx_en) { 1476 1477 case HWTSTAMP_TX_ONESTEP_SYNC: 1478 if (is_sync(skb, type)) { 1479 kfree_skb(skb); 1480 return; 1481 } 1482 /* fall through */ 1483 case HWTSTAMP_TX_ON: 1484 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1485 skb_queue_tail(&dp83640->tx_queue, skb); 1486 break; 1487 1488 case HWTSTAMP_TX_OFF: 1489 default: 1490 kfree_skb(skb); 1491 break; 1492 } 1493 } 1494 1495 static int dp83640_ts_info(struct phy_device *dev, struct ethtool_ts_info *info) 1496 { 1497 struct dp83640_private *dp83640 = dev->priv; 1498 1499 info->so_timestamping = 1500 SOF_TIMESTAMPING_TX_HARDWARE | 1501 SOF_TIMESTAMPING_RX_HARDWARE | 1502 SOF_TIMESTAMPING_RAW_HARDWARE; 1503 info->phc_index = ptp_clock_index(dp83640->clock->ptp_clock); 1504 info->tx_types = 1505 (1 << HWTSTAMP_TX_OFF) | 1506 (1 << HWTSTAMP_TX_ON) | 1507 (1 << HWTSTAMP_TX_ONESTEP_SYNC); 1508 info->rx_filters = 1509 (1 << HWTSTAMP_FILTER_NONE) | 1510 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) | 1511 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) | 1512 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 1513 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT); 1514 return 0; 1515 } 1516 1517 static struct phy_driver dp83640_driver = { 1518 .phy_id = DP83640_PHY_ID, 1519 .phy_id_mask = 0xfffffff0, 1520 .name = "NatSemi DP83640", 1521 .features = PHY_BASIC_FEATURES, 1522 .flags = PHY_HAS_INTERRUPT, 1523 .probe = dp83640_probe, 1524 .remove = dp83640_remove, 1525 .soft_reset = dp83640_soft_reset, 1526 .config_init = dp83640_config_init, 1527 .ack_interrupt = dp83640_ack_interrupt, 1528 .config_intr = dp83640_config_intr, 1529 .ts_info = dp83640_ts_info, 1530 .hwtstamp = dp83640_hwtstamp, 1531 .rxtstamp = dp83640_rxtstamp, 1532 .txtstamp = dp83640_txtstamp, 1533 }; 1534 1535 static int __init dp83640_init(void) 1536 { 1537 return phy_driver_register(&dp83640_driver, THIS_MODULE); 1538 } 1539 1540 static void __exit dp83640_exit(void) 1541 { 1542 dp83640_free_clocks(); 1543 phy_driver_unregister(&dp83640_driver); 1544 } 1545 1546 MODULE_DESCRIPTION("National Semiconductor DP83640 PHY driver"); 1547 MODULE_AUTHOR("Richard Cochran <richardcochran@gmail.com>"); 1548 MODULE_LICENSE("GPL"); 1549 1550 module_init(dp83640_init); 1551 module_exit(dp83640_exit); 1552 1553 static struct mdio_device_id __maybe_unused dp83640_tbl[] = { 1554 { DP83640_PHY_ID, 0xfffffff0 }, 1555 { } 1556 }; 1557 1558 MODULE_DEVICE_TABLE(mdio, dp83640_tbl); 1559