1 /* 2 * Driver for the National Semiconductor DP83640 PHYTER 3 * 4 * Copyright (C) 2010 OMICRON electronics GmbH 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 19 */ 20 21 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 22 23 #include <linux/crc32.h> 24 #include <linux/ethtool.h> 25 #include <linux/kernel.h> 26 #include <linux/list.h> 27 #include <linux/mii.h> 28 #include <linux/module.h> 29 #include <linux/net_tstamp.h> 30 #include <linux/netdevice.h> 31 #include <linux/if_vlan.h> 32 #include <linux/phy.h> 33 #include <linux/ptp_classify.h> 34 #include <linux/ptp_clock_kernel.h> 35 36 #include "dp83640_reg.h" 37 38 #define DP83640_PHY_ID 0x20005ce1 39 #define PAGESEL 0x13 40 #define MAX_RXTS 64 41 #define N_EXT_TS 6 42 #define N_PER_OUT 7 43 #define PSF_PTPVER 2 44 #define PSF_EVNT 0x4000 45 #define PSF_RX 0x2000 46 #define PSF_TX 0x1000 47 #define EXT_EVENT 1 48 #define CAL_EVENT 7 49 #define CAL_TRIGGER 1 50 #define DP83640_N_PINS 12 51 52 #define MII_DP83640_MICR 0x11 53 #define MII_DP83640_MISR 0x12 54 55 #define MII_DP83640_MICR_OE 0x1 56 #define MII_DP83640_MICR_IE 0x2 57 58 #define MII_DP83640_MISR_RHF_INT_EN 0x01 59 #define MII_DP83640_MISR_FHF_INT_EN 0x02 60 #define MII_DP83640_MISR_ANC_INT_EN 0x04 61 #define MII_DP83640_MISR_DUP_INT_EN 0x08 62 #define MII_DP83640_MISR_SPD_INT_EN 0x10 63 #define MII_DP83640_MISR_LINK_INT_EN 0x20 64 #define MII_DP83640_MISR_ED_INT_EN 0x40 65 #define MII_DP83640_MISR_LQ_INT_EN 0x80 66 67 /* phyter seems to miss the mark by 16 ns */ 68 #define ADJTIME_FIX 16 69 70 #define SKB_TIMESTAMP_TIMEOUT 2 /* jiffies */ 71 72 #if defined(__BIG_ENDIAN) 73 #define ENDIAN_FLAG 0 74 #elif defined(__LITTLE_ENDIAN) 75 #define ENDIAN_FLAG PSF_ENDIAN 76 #endif 77 78 struct dp83640_skb_info { 79 int ptp_type; 80 unsigned long tmo; 81 }; 82 83 struct phy_rxts { 84 u16 ns_lo; /* ns[15:0] */ 85 u16 ns_hi; /* overflow[1:0], ns[29:16] */ 86 u16 sec_lo; /* sec[15:0] */ 87 u16 sec_hi; /* sec[31:16] */ 88 u16 seqid; /* sequenceId[15:0] */ 89 u16 msgtype; /* messageType[3:0], hash[11:0] */ 90 }; 91 92 struct phy_txts { 93 u16 ns_lo; /* ns[15:0] */ 94 u16 ns_hi; /* overflow[1:0], ns[29:16] */ 95 u16 sec_lo; /* sec[15:0] */ 96 u16 sec_hi; /* sec[31:16] */ 97 }; 98 99 struct rxts { 100 struct list_head list; 101 unsigned long tmo; 102 u64 ns; 103 u16 seqid; 104 u8 msgtype; 105 u16 hash; 106 }; 107 108 struct dp83640_clock; 109 110 struct dp83640_private { 111 struct list_head list; 112 struct dp83640_clock *clock; 113 struct phy_device *phydev; 114 struct delayed_work ts_work; 115 int hwts_tx_en; 116 int hwts_rx_en; 117 int layer; 118 int version; 119 /* remember state of cfg0 during calibration */ 120 int cfg0; 121 /* remember the last event time stamp */ 122 struct phy_txts edata; 123 /* list of rx timestamps */ 124 struct list_head rxts; 125 struct list_head rxpool; 126 struct rxts rx_pool_data[MAX_RXTS]; 127 /* protects above three fields from concurrent access */ 128 spinlock_t rx_lock; 129 /* queues of incoming and outgoing packets */ 130 struct sk_buff_head rx_queue; 131 struct sk_buff_head tx_queue; 132 }; 133 134 struct dp83640_clock { 135 /* keeps the instance in the 'phyter_clocks' list */ 136 struct list_head list; 137 /* we create one clock instance per MII bus */ 138 struct mii_bus *bus; 139 /* protects extended registers from concurrent access */ 140 struct mutex extreg_lock; 141 /* remembers which page was last selected */ 142 int page; 143 /* our advertised capabilities */ 144 struct ptp_clock_info caps; 145 /* protects the three fields below from concurrent access */ 146 struct mutex clock_lock; 147 /* the one phyter from which we shall read */ 148 struct dp83640_private *chosen; 149 /* list of the other attached phyters, not chosen */ 150 struct list_head phylist; 151 /* reference to our PTP hardware clock */ 152 struct ptp_clock *ptp_clock; 153 }; 154 155 /* globals */ 156 157 enum { 158 CALIBRATE_GPIO, 159 PEROUT_GPIO, 160 EXTTS0_GPIO, 161 EXTTS1_GPIO, 162 EXTTS2_GPIO, 163 EXTTS3_GPIO, 164 EXTTS4_GPIO, 165 EXTTS5_GPIO, 166 GPIO_TABLE_SIZE 167 }; 168 169 static int chosen_phy = -1; 170 static ushort gpio_tab[GPIO_TABLE_SIZE] = { 171 1, 2, 3, 4, 8, 9, 10, 11 172 }; 173 174 module_param(chosen_phy, int, 0444); 175 module_param_array(gpio_tab, ushort, NULL, 0444); 176 177 MODULE_PARM_DESC(chosen_phy, \ 178 "The address of the PHY to use for the ancillary clock features"); 179 MODULE_PARM_DESC(gpio_tab, \ 180 "Which GPIO line to use for which purpose: cal,perout,extts1,...,extts6"); 181 182 static void dp83640_gpio_defaults(struct ptp_pin_desc *pd) 183 { 184 int i, index; 185 186 for (i = 0; i < DP83640_N_PINS; i++) { 187 snprintf(pd[i].name, sizeof(pd[i].name), "GPIO%d", 1 + i); 188 pd[i].index = i; 189 } 190 191 for (i = 0; i < GPIO_TABLE_SIZE; i++) { 192 if (gpio_tab[i] < 1 || gpio_tab[i] > DP83640_N_PINS) { 193 pr_err("gpio_tab[%d]=%hu out of range", i, gpio_tab[i]); 194 return; 195 } 196 } 197 198 index = gpio_tab[CALIBRATE_GPIO] - 1; 199 pd[index].func = PTP_PF_PHYSYNC; 200 pd[index].chan = 0; 201 202 index = gpio_tab[PEROUT_GPIO] - 1; 203 pd[index].func = PTP_PF_PEROUT; 204 pd[index].chan = 0; 205 206 for (i = EXTTS0_GPIO; i < GPIO_TABLE_SIZE; i++) { 207 index = gpio_tab[i] - 1; 208 pd[index].func = PTP_PF_EXTTS; 209 pd[index].chan = i - EXTTS0_GPIO; 210 } 211 } 212 213 /* a list of clocks and a mutex to protect it */ 214 static LIST_HEAD(phyter_clocks); 215 static DEFINE_MUTEX(phyter_clocks_lock); 216 217 static void rx_timestamp_work(struct work_struct *work); 218 219 /* extended register access functions */ 220 221 #define BROADCAST_ADDR 31 222 223 static inline int broadcast_write(struct phy_device *phydev, u32 regnum, 224 u16 val) 225 { 226 return mdiobus_write(phydev->mdio.bus, BROADCAST_ADDR, regnum, val); 227 } 228 229 /* Caller must hold extreg_lock. */ 230 static int ext_read(struct phy_device *phydev, int page, u32 regnum) 231 { 232 struct dp83640_private *dp83640 = phydev->priv; 233 int val; 234 235 if (dp83640->clock->page != page) { 236 broadcast_write(phydev, PAGESEL, page); 237 dp83640->clock->page = page; 238 } 239 val = phy_read(phydev, regnum); 240 241 return val; 242 } 243 244 /* Caller must hold extreg_lock. */ 245 static void ext_write(int broadcast, struct phy_device *phydev, 246 int page, u32 regnum, u16 val) 247 { 248 struct dp83640_private *dp83640 = phydev->priv; 249 250 if (dp83640->clock->page != page) { 251 broadcast_write(phydev, PAGESEL, page); 252 dp83640->clock->page = page; 253 } 254 if (broadcast) 255 broadcast_write(phydev, regnum, val); 256 else 257 phy_write(phydev, regnum, val); 258 } 259 260 /* Caller must hold extreg_lock. */ 261 static int tdr_write(int bc, struct phy_device *dev, 262 const struct timespec64 *ts, u16 cmd) 263 { 264 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec & 0xffff);/* ns[15:0] */ 265 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec >> 16); /* ns[31:16] */ 266 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec & 0xffff); /* sec[15:0] */ 267 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec >> 16); /* sec[31:16]*/ 268 269 ext_write(bc, dev, PAGE4, PTP_CTL, cmd); 270 271 return 0; 272 } 273 274 /* convert phy timestamps into driver timestamps */ 275 276 static void phy2rxts(struct phy_rxts *p, struct rxts *rxts) 277 { 278 u32 sec; 279 280 sec = p->sec_lo; 281 sec |= p->sec_hi << 16; 282 283 rxts->ns = p->ns_lo; 284 rxts->ns |= (p->ns_hi & 0x3fff) << 16; 285 rxts->ns += ((u64)sec) * 1000000000ULL; 286 rxts->seqid = p->seqid; 287 rxts->msgtype = (p->msgtype >> 12) & 0xf; 288 rxts->hash = p->msgtype & 0x0fff; 289 rxts->tmo = jiffies + SKB_TIMESTAMP_TIMEOUT; 290 } 291 292 static u64 phy2txts(struct phy_txts *p) 293 { 294 u64 ns; 295 u32 sec; 296 297 sec = p->sec_lo; 298 sec |= p->sec_hi << 16; 299 300 ns = p->ns_lo; 301 ns |= (p->ns_hi & 0x3fff) << 16; 302 ns += ((u64)sec) * 1000000000ULL; 303 304 return ns; 305 } 306 307 static int periodic_output(struct dp83640_clock *clock, 308 struct ptp_clock_request *clkreq, bool on, 309 int trigger) 310 { 311 struct dp83640_private *dp83640 = clock->chosen; 312 struct phy_device *phydev = dp83640->phydev; 313 u32 sec, nsec, pwidth; 314 u16 gpio, ptp_trig, val; 315 316 if (on) { 317 gpio = 1 + ptp_find_pin(clock->ptp_clock, PTP_PF_PEROUT, 318 trigger); 319 if (gpio < 1) 320 return -EINVAL; 321 } else { 322 gpio = 0; 323 } 324 325 ptp_trig = TRIG_WR | 326 (trigger & TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT | 327 (gpio & TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT | 328 TRIG_PER | 329 TRIG_PULSE; 330 331 val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT; 332 333 if (!on) { 334 val |= TRIG_DIS; 335 mutex_lock(&clock->extreg_lock); 336 ext_write(0, phydev, PAGE5, PTP_TRIG, ptp_trig); 337 ext_write(0, phydev, PAGE4, PTP_CTL, val); 338 mutex_unlock(&clock->extreg_lock); 339 return 0; 340 } 341 342 sec = clkreq->perout.start.sec; 343 nsec = clkreq->perout.start.nsec; 344 pwidth = clkreq->perout.period.sec * 1000000000UL; 345 pwidth += clkreq->perout.period.nsec; 346 pwidth /= 2; 347 348 mutex_lock(&clock->extreg_lock); 349 350 ext_write(0, phydev, PAGE5, PTP_TRIG, ptp_trig); 351 352 /*load trigger*/ 353 val |= TRIG_LOAD; 354 ext_write(0, phydev, PAGE4, PTP_CTL, val); 355 ext_write(0, phydev, PAGE4, PTP_TDR, nsec & 0xffff); /* ns[15:0] */ 356 ext_write(0, phydev, PAGE4, PTP_TDR, nsec >> 16); /* ns[31:16] */ 357 ext_write(0, phydev, PAGE4, PTP_TDR, sec & 0xffff); /* sec[15:0] */ 358 ext_write(0, phydev, PAGE4, PTP_TDR, sec >> 16); /* sec[31:16] */ 359 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth & 0xffff); /* ns[15:0] */ 360 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth >> 16); /* ns[31:16] */ 361 /* Triggers 0 and 1 has programmable pulsewidth2 */ 362 if (trigger < 2) { 363 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth & 0xffff); 364 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth >> 16); 365 } 366 367 /*enable trigger*/ 368 val &= ~TRIG_LOAD; 369 val |= TRIG_EN; 370 ext_write(0, phydev, PAGE4, PTP_CTL, val); 371 372 mutex_unlock(&clock->extreg_lock); 373 return 0; 374 } 375 376 /* ptp clock methods */ 377 378 static int ptp_dp83640_adjfine(struct ptp_clock_info *ptp, long scaled_ppm) 379 { 380 struct dp83640_clock *clock = 381 container_of(ptp, struct dp83640_clock, caps); 382 struct phy_device *phydev = clock->chosen->phydev; 383 u64 rate; 384 int neg_adj = 0; 385 u16 hi, lo; 386 387 if (scaled_ppm < 0) { 388 neg_adj = 1; 389 scaled_ppm = -scaled_ppm; 390 } 391 rate = scaled_ppm; 392 rate <<= 13; 393 rate = div_u64(rate, 15625); 394 395 hi = (rate >> 16) & PTP_RATE_HI_MASK; 396 if (neg_adj) 397 hi |= PTP_RATE_DIR; 398 399 lo = rate & 0xffff; 400 401 mutex_lock(&clock->extreg_lock); 402 403 ext_write(1, phydev, PAGE4, PTP_RATEH, hi); 404 ext_write(1, phydev, PAGE4, PTP_RATEL, lo); 405 406 mutex_unlock(&clock->extreg_lock); 407 408 return 0; 409 } 410 411 static int ptp_dp83640_adjtime(struct ptp_clock_info *ptp, s64 delta) 412 { 413 struct dp83640_clock *clock = 414 container_of(ptp, struct dp83640_clock, caps); 415 struct phy_device *phydev = clock->chosen->phydev; 416 struct timespec64 ts; 417 int err; 418 419 delta += ADJTIME_FIX; 420 421 ts = ns_to_timespec64(delta); 422 423 mutex_lock(&clock->extreg_lock); 424 425 err = tdr_write(1, phydev, &ts, PTP_STEP_CLK); 426 427 mutex_unlock(&clock->extreg_lock); 428 429 return err; 430 } 431 432 static int ptp_dp83640_gettime(struct ptp_clock_info *ptp, 433 struct timespec64 *ts) 434 { 435 struct dp83640_clock *clock = 436 container_of(ptp, struct dp83640_clock, caps); 437 struct phy_device *phydev = clock->chosen->phydev; 438 unsigned int val[4]; 439 440 mutex_lock(&clock->extreg_lock); 441 442 ext_write(0, phydev, PAGE4, PTP_CTL, PTP_RD_CLK); 443 444 val[0] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[15:0] */ 445 val[1] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[31:16] */ 446 val[2] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[15:0] */ 447 val[3] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[31:16] */ 448 449 mutex_unlock(&clock->extreg_lock); 450 451 ts->tv_nsec = val[0] | (val[1] << 16); 452 ts->tv_sec = val[2] | (val[3] << 16); 453 454 return 0; 455 } 456 457 static int ptp_dp83640_settime(struct ptp_clock_info *ptp, 458 const struct timespec64 *ts) 459 { 460 struct dp83640_clock *clock = 461 container_of(ptp, struct dp83640_clock, caps); 462 struct phy_device *phydev = clock->chosen->phydev; 463 int err; 464 465 mutex_lock(&clock->extreg_lock); 466 467 err = tdr_write(1, phydev, ts, PTP_LOAD_CLK); 468 469 mutex_unlock(&clock->extreg_lock); 470 471 return err; 472 } 473 474 static int ptp_dp83640_enable(struct ptp_clock_info *ptp, 475 struct ptp_clock_request *rq, int on) 476 { 477 struct dp83640_clock *clock = 478 container_of(ptp, struct dp83640_clock, caps); 479 struct phy_device *phydev = clock->chosen->phydev; 480 unsigned int index; 481 u16 evnt, event_num, gpio_num; 482 483 switch (rq->type) { 484 case PTP_CLK_REQ_EXTTS: 485 index = rq->extts.index; 486 if (index >= N_EXT_TS) 487 return -EINVAL; 488 event_num = EXT_EVENT + index; 489 evnt = EVNT_WR | (event_num & EVNT_SEL_MASK) << EVNT_SEL_SHIFT; 490 if (on) { 491 gpio_num = 1 + ptp_find_pin(clock->ptp_clock, 492 PTP_PF_EXTTS, index); 493 if (gpio_num < 1) 494 return -EINVAL; 495 evnt |= (gpio_num & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT; 496 if (rq->extts.flags & PTP_FALLING_EDGE) 497 evnt |= EVNT_FALL; 498 else 499 evnt |= EVNT_RISE; 500 } 501 mutex_lock(&clock->extreg_lock); 502 ext_write(0, phydev, PAGE5, PTP_EVNT, evnt); 503 mutex_unlock(&clock->extreg_lock); 504 return 0; 505 506 case PTP_CLK_REQ_PEROUT: 507 if (rq->perout.index >= N_PER_OUT) 508 return -EINVAL; 509 return periodic_output(clock, rq, on, rq->perout.index); 510 511 default: 512 break; 513 } 514 515 return -EOPNOTSUPP; 516 } 517 518 static int ptp_dp83640_verify(struct ptp_clock_info *ptp, unsigned int pin, 519 enum ptp_pin_function func, unsigned int chan) 520 { 521 struct dp83640_clock *clock = 522 container_of(ptp, struct dp83640_clock, caps); 523 524 if (clock->caps.pin_config[pin].func == PTP_PF_PHYSYNC && 525 !list_empty(&clock->phylist)) 526 return 1; 527 528 if (func == PTP_PF_PHYSYNC) 529 return 1; 530 531 return 0; 532 } 533 534 static u8 status_frame_dst[6] = { 0x01, 0x1B, 0x19, 0x00, 0x00, 0x00 }; 535 static u8 status_frame_src[6] = { 0x08, 0x00, 0x17, 0x0B, 0x6B, 0x0F }; 536 537 static void enable_status_frames(struct phy_device *phydev, bool on) 538 { 539 struct dp83640_private *dp83640 = phydev->priv; 540 struct dp83640_clock *clock = dp83640->clock; 541 u16 cfg0 = 0, ver; 542 543 if (on) 544 cfg0 = PSF_EVNT_EN | PSF_RXTS_EN | PSF_TXTS_EN | ENDIAN_FLAG; 545 546 ver = (PSF_PTPVER & VERSIONPTP_MASK) << VERSIONPTP_SHIFT; 547 548 mutex_lock(&clock->extreg_lock); 549 550 ext_write(0, phydev, PAGE5, PSF_CFG0, cfg0); 551 ext_write(0, phydev, PAGE6, PSF_CFG1, ver); 552 553 mutex_unlock(&clock->extreg_lock); 554 555 if (!phydev->attached_dev) { 556 pr_warn("expected to find an attached netdevice\n"); 557 return; 558 } 559 560 if (on) { 561 if (dev_mc_add(phydev->attached_dev, status_frame_dst)) 562 pr_warn("failed to add mc address\n"); 563 } else { 564 if (dev_mc_del(phydev->attached_dev, status_frame_dst)) 565 pr_warn("failed to delete mc address\n"); 566 } 567 } 568 569 static bool is_status_frame(struct sk_buff *skb, int type) 570 { 571 struct ethhdr *h = eth_hdr(skb); 572 573 if (PTP_CLASS_V2_L2 == type && 574 !memcmp(h->h_source, status_frame_src, sizeof(status_frame_src))) 575 return true; 576 else 577 return false; 578 } 579 580 static int expired(struct rxts *rxts) 581 { 582 return time_after(jiffies, rxts->tmo); 583 } 584 585 /* Caller must hold rx_lock. */ 586 static void prune_rx_ts(struct dp83640_private *dp83640) 587 { 588 struct list_head *this, *next; 589 struct rxts *rxts; 590 591 list_for_each_safe(this, next, &dp83640->rxts) { 592 rxts = list_entry(this, struct rxts, list); 593 if (expired(rxts)) { 594 list_del_init(&rxts->list); 595 list_add(&rxts->list, &dp83640->rxpool); 596 } 597 } 598 } 599 600 /* synchronize the phyters so they act as one clock */ 601 602 static void enable_broadcast(struct phy_device *phydev, int init_page, int on) 603 { 604 int val; 605 phy_write(phydev, PAGESEL, 0); 606 val = phy_read(phydev, PHYCR2); 607 if (on) 608 val |= BC_WRITE; 609 else 610 val &= ~BC_WRITE; 611 phy_write(phydev, PHYCR2, val); 612 phy_write(phydev, PAGESEL, init_page); 613 } 614 615 static void recalibrate(struct dp83640_clock *clock) 616 { 617 s64 now, diff; 618 struct phy_txts event_ts; 619 struct timespec64 ts; 620 struct list_head *this; 621 struct dp83640_private *tmp; 622 struct phy_device *master = clock->chosen->phydev; 623 u16 cal_gpio, cfg0, evnt, ptp_trig, trigger, val; 624 625 trigger = CAL_TRIGGER; 626 cal_gpio = 1 + ptp_find_pin(clock->ptp_clock, PTP_PF_PHYSYNC, 0); 627 if (cal_gpio < 1) { 628 pr_err("PHY calibration pin not available - PHY is not calibrated."); 629 return; 630 } 631 632 mutex_lock(&clock->extreg_lock); 633 634 /* 635 * enable broadcast, disable status frames, enable ptp clock 636 */ 637 list_for_each(this, &clock->phylist) { 638 tmp = list_entry(this, struct dp83640_private, list); 639 enable_broadcast(tmp->phydev, clock->page, 1); 640 tmp->cfg0 = ext_read(tmp->phydev, PAGE5, PSF_CFG0); 641 ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, 0); 642 ext_write(0, tmp->phydev, PAGE4, PTP_CTL, PTP_ENABLE); 643 } 644 enable_broadcast(master, clock->page, 1); 645 cfg0 = ext_read(master, PAGE5, PSF_CFG0); 646 ext_write(0, master, PAGE5, PSF_CFG0, 0); 647 ext_write(0, master, PAGE4, PTP_CTL, PTP_ENABLE); 648 649 /* 650 * enable an event timestamp 651 */ 652 evnt = EVNT_WR | EVNT_RISE | EVNT_SINGLE; 653 evnt |= (CAL_EVENT & EVNT_SEL_MASK) << EVNT_SEL_SHIFT; 654 evnt |= (cal_gpio & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT; 655 656 list_for_each(this, &clock->phylist) { 657 tmp = list_entry(this, struct dp83640_private, list); 658 ext_write(0, tmp->phydev, PAGE5, PTP_EVNT, evnt); 659 } 660 ext_write(0, master, PAGE5, PTP_EVNT, evnt); 661 662 /* 663 * configure a trigger 664 */ 665 ptp_trig = TRIG_WR | TRIG_IF_LATE | TRIG_PULSE; 666 ptp_trig |= (trigger & TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT; 667 ptp_trig |= (cal_gpio & TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT; 668 ext_write(0, master, PAGE5, PTP_TRIG, ptp_trig); 669 670 /* load trigger */ 671 val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT; 672 val |= TRIG_LOAD; 673 ext_write(0, master, PAGE4, PTP_CTL, val); 674 675 /* enable trigger */ 676 val &= ~TRIG_LOAD; 677 val |= TRIG_EN; 678 ext_write(0, master, PAGE4, PTP_CTL, val); 679 680 /* disable trigger */ 681 val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT; 682 val |= TRIG_DIS; 683 ext_write(0, master, PAGE4, PTP_CTL, val); 684 685 /* 686 * read out and correct offsets 687 */ 688 val = ext_read(master, PAGE4, PTP_STS); 689 pr_info("master PTP_STS 0x%04hx\n", val); 690 val = ext_read(master, PAGE4, PTP_ESTS); 691 pr_info("master PTP_ESTS 0x%04hx\n", val); 692 event_ts.ns_lo = ext_read(master, PAGE4, PTP_EDATA); 693 event_ts.ns_hi = ext_read(master, PAGE4, PTP_EDATA); 694 event_ts.sec_lo = ext_read(master, PAGE4, PTP_EDATA); 695 event_ts.sec_hi = ext_read(master, PAGE4, PTP_EDATA); 696 now = phy2txts(&event_ts); 697 698 list_for_each(this, &clock->phylist) { 699 tmp = list_entry(this, struct dp83640_private, list); 700 val = ext_read(tmp->phydev, PAGE4, PTP_STS); 701 pr_info("slave PTP_STS 0x%04hx\n", val); 702 val = ext_read(tmp->phydev, PAGE4, PTP_ESTS); 703 pr_info("slave PTP_ESTS 0x%04hx\n", val); 704 event_ts.ns_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA); 705 event_ts.ns_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA); 706 event_ts.sec_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA); 707 event_ts.sec_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA); 708 diff = now - (s64) phy2txts(&event_ts); 709 pr_info("slave offset %lld nanoseconds\n", diff); 710 diff += ADJTIME_FIX; 711 ts = ns_to_timespec64(diff); 712 tdr_write(0, tmp->phydev, &ts, PTP_STEP_CLK); 713 } 714 715 /* 716 * restore status frames 717 */ 718 list_for_each(this, &clock->phylist) { 719 tmp = list_entry(this, struct dp83640_private, list); 720 ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, tmp->cfg0); 721 } 722 ext_write(0, master, PAGE5, PSF_CFG0, cfg0); 723 724 mutex_unlock(&clock->extreg_lock); 725 } 726 727 /* time stamping methods */ 728 729 static inline u16 exts_chan_to_edata(int ch) 730 { 731 return 1 << ((ch + EXT_EVENT) * 2); 732 } 733 734 static int decode_evnt(struct dp83640_private *dp83640, 735 void *data, int len, u16 ests) 736 { 737 struct phy_txts *phy_txts; 738 struct ptp_clock_event event; 739 int i, parsed; 740 int words = (ests >> EVNT_TS_LEN_SHIFT) & EVNT_TS_LEN_MASK; 741 u16 ext_status = 0; 742 743 /* calculate length of the event timestamp status message */ 744 if (ests & MULT_EVNT) 745 parsed = (words + 2) * sizeof(u16); 746 else 747 parsed = (words + 1) * sizeof(u16); 748 749 /* check if enough data is available */ 750 if (len < parsed) 751 return len; 752 753 if (ests & MULT_EVNT) { 754 ext_status = *(u16 *) data; 755 data += sizeof(ext_status); 756 } 757 758 phy_txts = data; 759 760 switch (words) { /* fall through in every case */ 761 case 3: 762 dp83640->edata.sec_hi = phy_txts->sec_hi; 763 case 2: 764 dp83640->edata.sec_lo = phy_txts->sec_lo; 765 case 1: 766 dp83640->edata.ns_hi = phy_txts->ns_hi; 767 case 0: 768 dp83640->edata.ns_lo = phy_txts->ns_lo; 769 } 770 771 if (!ext_status) { 772 i = ((ests >> EVNT_NUM_SHIFT) & EVNT_NUM_MASK) - EXT_EVENT; 773 ext_status = exts_chan_to_edata(i); 774 } 775 776 event.type = PTP_CLOCK_EXTTS; 777 event.timestamp = phy2txts(&dp83640->edata); 778 779 /* Compensate for input path and synchronization delays */ 780 event.timestamp -= 35; 781 782 for (i = 0; i < N_EXT_TS; i++) { 783 if (ext_status & exts_chan_to_edata(i)) { 784 event.index = i; 785 ptp_clock_event(dp83640->clock->ptp_clock, &event); 786 } 787 } 788 789 return parsed; 790 } 791 792 #define DP83640_PACKET_HASH_OFFSET 20 793 #define DP83640_PACKET_HASH_LEN 10 794 795 static int match(struct sk_buff *skb, unsigned int type, struct rxts *rxts) 796 { 797 u16 *seqid, hash; 798 unsigned int offset = 0; 799 u8 *msgtype, *data = skb_mac_header(skb); 800 801 /* check sequenceID, messageType, 12 bit hash of offset 20-29 */ 802 803 if (type & PTP_CLASS_VLAN) 804 offset += VLAN_HLEN; 805 806 switch (type & PTP_CLASS_PMASK) { 807 case PTP_CLASS_IPV4: 808 offset += ETH_HLEN + IPV4_HLEN(data + offset) + UDP_HLEN; 809 break; 810 case PTP_CLASS_IPV6: 811 offset += ETH_HLEN + IP6_HLEN + UDP_HLEN; 812 break; 813 case PTP_CLASS_L2: 814 offset += ETH_HLEN; 815 break; 816 default: 817 return 0; 818 } 819 820 if (skb->len + ETH_HLEN < offset + OFF_PTP_SEQUENCE_ID + sizeof(*seqid)) 821 return 0; 822 823 if (unlikely(type & PTP_CLASS_V1)) 824 msgtype = data + offset + OFF_PTP_CONTROL; 825 else 826 msgtype = data + offset; 827 if (rxts->msgtype != (*msgtype & 0xf)) 828 return 0; 829 830 seqid = (u16 *)(data + offset + OFF_PTP_SEQUENCE_ID); 831 if (rxts->seqid != ntohs(*seqid)) 832 return 0; 833 834 hash = ether_crc(DP83640_PACKET_HASH_LEN, 835 data + offset + DP83640_PACKET_HASH_OFFSET) >> 20; 836 if (rxts->hash != hash) 837 return 0; 838 839 return 1; 840 } 841 842 static void decode_rxts(struct dp83640_private *dp83640, 843 struct phy_rxts *phy_rxts) 844 { 845 struct rxts *rxts; 846 struct skb_shared_hwtstamps *shhwtstamps = NULL; 847 struct sk_buff *skb; 848 unsigned long flags; 849 u8 overflow; 850 851 overflow = (phy_rxts->ns_hi >> 14) & 0x3; 852 if (overflow) 853 pr_debug("rx timestamp queue overflow, count %d\n", overflow); 854 855 spin_lock_irqsave(&dp83640->rx_lock, flags); 856 857 prune_rx_ts(dp83640); 858 859 if (list_empty(&dp83640->rxpool)) { 860 pr_debug("rx timestamp pool is empty\n"); 861 goto out; 862 } 863 rxts = list_first_entry(&dp83640->rxpool, struct rxts, list); 864 list_del_init(&rxts->list); 865 phy2rxts(phy_rxts, rxts); 866 867 spin_lock(&dp83640->rx_queue.lock); 868 skb_queue_walk(&dp83640->rx_queue, skb) { 869 struct dp83640_skb_info *skb_info; 870 871 skb_info = (struct dp83640_skb_info *)skb->cb; 872 if (match(skb, skb_info->ptp_type, rxts)) { 873 __skb_unlink(skb, &dp83640->rx_queue); 874 shhwtstamps = skb_hwtstamps(skb); 875 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 876 shhwtstamps->hwtstamp = ns_to_ktime(rxts->ns); 877 netif_rx_ni(skb); 878 list_add(&rxts->list, &dp83640->rxpool); 879 break; 880 } 881 } 882 spin_unlock(&dp83640->rx_queue.lock); 883 884 if (!shhwtstamps) 885 list_add_tail(&rxts->list, &dp83640->rxts); 886 out: 887 spin_unlock_irqrestore(&dp83640->rx_lock, flags); 888 } 889 890 static void decode_txts(struct dp83640_private *dp83640, 891 struct phy_txts *phy_txts) 892 { 893 struct skb_shared_hwtstamps shhwtstamps; 894 struct sk_buff *skb; 895 u64 ns; 896 u8 overflow; 897 898 /* We must already have the skb that triggered this. */ 899 900 skb = skb_dequeue(&dp83640->tx_queue); 901 902 if (!skb) { 903 pr_debug("have timestamp but tx_queue empty\n"); 904 return; 905 } 906 907 overflow = (phy_txts->ns_hi >> 14) & 0x3; 908 if (overflow) { 909 pr_debug("tx timestamp queue overflow, count %d\n", overflow); 910 while (skb) { 911 kfree_skb(skb); 912 skb = skb_dequeue(&dp83640->tx_queue); 913 } 914 return; 915 } 916 917 ns = phy2txts(phy_txts); 918 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 919 shhwtstamps.hwtstamp = ns_to_ktime(ns); 920 skb_complete_tx_timestamp(skb, &shhwtstamps); 921 } 922 923 static void decode_status_frame(struct dp83640_private *dp83640, 924 struct sk_buff *skb) 925 { 926 struct phy_rxts *phy_rxts; 927 struct phy_txts *phy_txts; 928 u8 *ptr; 929 int len, size; 930 u16 ests, type; 931 932 ptr = skb->data + 2; 933 934 for (len = skb_headlen(skb) - 2; len > sizeof(type); len -= size) { 935 936 type = *(u16 *)ptr; 937 ests = type & 0x0fff; 938 type = type & 0xf000; 939 len -= sizeof(type); 940 ptr += sizeof(type); 941 942 if (PSF_RX == type && len >= sizeof(*phy_rxts)) { 943 944 phy_rxts = (struct phy_rxts *) ptr; 945 decode_rxts(dp83640, phy_rxts); 946 size = sizeof(*phy_rxts); 947 948 } else if (PSF_TX == type && len >= sizeof(*phy_txts)) { 949 950 phy_txts = (struct phy_txts *) ptr; 951 decode_txts(dp83640, phy_txts); 952 size = sizeof(*phy_txts); 953 954 } else if (PSF_EVNT == type) { 955 956 size = decode_evnt(dp83640, ptr, len, ests); 957 958 } else { 959 size = 0; 960 break; 961 } 962 ptr += size; 963 } 964 } 965 966 static int is_sync(struct sk_buff *skb, int type) 967 { 968 u8 *data = skb->data, *msgtype; 969 unsigned int offset = 0; 970 971 if (type & PTP_CLASS_VLAN) 972 offset += VLAN_HLEN; 973 974 switch (type & PTP_CLASS_PMASK) { 975 case PTP_CLASS_IPV4: 976 offset += ETH_HLEN + IPV4_HLEN(data + offset) + UDP_HLEN; 977 break; 978 case PTP_CLASS_IPV6: 979 offset += ETH_HLEN + IP6_HLEN + UDP_HLEN; 980 break; 981 case PTP_CLASS_L2: 982 offset += ETH_HLEN; 983 break; 984 default: 985 return 0; 986 } 987 988 if (type & PTP_CLASS_V1) 989 offset += OFF_PTP_CONTROL; 990 991 if (skb->len < offset + 1) 992 return 0; 993 994 msgtype = data + offset; 995 996 return (*msgtype & 0xf) == 0; 997 } 998 999 static void dp83640_free_clocks(void) 1000 { 1001 struct dp83640_clock *clock; 1002 struct list_head *this, *next; 1003 1004 mutex_lock(&phyter_clocks_lock); 1005 1006 list_for_each_safe(this, next, &phyter_clocks) { 1007 clock = list_entry(this, struct dp83640_clock, list); 1008 if (!list_empty(&clock->phylist)) { 1009 pr_warn("phy list non-empty while unloading\n"); 1010 BUG(); 1011 } 1012 list_del(&clock->list); 1013 mutex_destroy(&clock->extreg_lock); 1014 mutex_destroy(&clock->clock_lock); 1015 put_device(&clock->bus->dev); 1016 kfree(clock->caps.pin_config); 1017 kfree(clock); 1018 } 1019 1020 mutex_unlock(&phyter_clocks_lock); 1021 } 1022 1023 static void dp83640_clock_init(struct dp83640_clock *clock, struct mii_bus *bus) 1024 { 1025 INIT_LIST_HEAD(&clock->list); 1026 clock->bus = bus; 1027 mutex_init(&clock->extreg_lock); 1028 mutex_init(&clock->clock_lock); 1029 INIT_LIST_HEAD(&clock->phylist); 1030 clock->caps.owner = THIS_MODULE; 1031 sprintf(clock->caps.name, "dp83640 timer"); 1032 clock->caps.max_adj = 1953124; 1033 clock->caps.n_alarm = 0; 1034 clock->caps.n_ext_ts = N_EXT_TS; 1035 clock->caps.n_per_out = N_PER_OUT; 1036 clock->caps.n_pins = DP83640_N_PINS; 1037 clock->caps.pps = 0; 1038 clock->caps.adjfine = ptp_dp83640_adjfine; 1039 clock->caps.adjtime = ptp_dp83640_adjtime; 1040 clock->caps.gettime64 = ptp_dp83640_gettime; 1041 clock->caps.settime64 = ptp_dp83640_settime; 1042 clock->caps.enable = ptp_dp83640_enable; 1043 clock->caps.verify = ptp_dp83640_verify; 1044 /* 1045 * Convert the module param defaults into a dynamic pin configuration. 1046 */ 1047 dp83640_gpio_defaults(clock->caps.pin_config); 1048 /* 1049 * Get a reference to this bus instance. 1050 */ 1051 get_device(&bus->dev); 1052 } 1053 1054 static int choose_this_phy(struct dp83640_clock *clock, 1055 struct phy_device *phydev) 1056 { 1057 if (chosen_phy == -1 && !clock->chosen) 1058 return 1; 1059 1060 if (chosen_phy == phydev->mdio.addr) 1061 return 1; 1062 1063 return 0; 1064 } 1065 1066 static struct dp83640_clock *dp83640_clock_get(struct dp83640_clock *clock) 1067 { 1068 if (clock) 1069 mutex_lock(&clock->clock_lock); 1070 return clock; 1071 } 1072 1073 /* 1074 * Look up and lock a clock by bus instance. 1075 * If there is no clock for this bus, then create it first. 1076 */ 1077 static struct dp83640_clock *dp83640_clock_get_bus(struct mii_bus *bus) 1078 { 1079 struct dp83640_clock *clock = NULL, *tmp; 1080 struct list_head *this; 1081 1082 mutex_lock(&phyter_clocks_lock); 1083 1084 list_for_each(this, &phyter_clocks) { 1085 tmp = list_entry(this, struct dp83640_clock, list); 1086 if (tmp->bus == bus) { 1087 clock = tmp; 1088 break; 1089 } 1090 } 1091 if (clock) 1092 goto out; 1093 1094 clock = kzalloc(sizeof(struct dp83640_clock), GFP_KERNEL); 1095 if (!clock) 1096 goto out; 1097 1098 clock->caps.pin_config = kzalloc(sizeof(struct ptp_pin_desc) * 1099 DP83640_N_PINS, GFP_KERNEL); 1100 if (!clock->caps.pin_config) { 1101 kfree(clock); 1102 clock = NULL; 1103 goto out; 1104 } 1105 dp83640_clock_init(clock, bus); 1106 list_add_tail(&phyter_clocks, &clock->list); 1107 out: 1108 mutex_unlock(&phyter_clocks_lock); 1109 1110 return dp83640_clock_get(clock); 1111 } 1112 1113 static void dp83640_clock_put(struct dp83640_clock *clock) 1114 { 1115 mutex_unlock(&clock->clock_lock); 1116 } 1117 1118 static int dp83640_probe(struct phy_device *phydev) 1119 { 1120 struct dp83640_clock *clock; 1121 struct dp83640_private *dp83640; 1122 int err = -ENOMEM, i; 1123 1124 if (phydev->mdio.addr == BROADCAST_ADDR) 1125 return 0; 1126 1127 clock = dp83640_clock_get_bus(phydev->mdio.bus); 1128 if (!clock) 1129 goto no_clock; 1130 1131 dp83640 = kzalloc(sizeof(struct dp83640_private), GFP_KERNEL); 1132 if (!dp83640) 1133 goto no_memory; 1134 1135 dp83640->phydev = phydev; 1136 INIT_DELAYED_WORK(&dp83640->ts_work, rx_timestamp_work); 1137 1138 INIT_LIST_HEAD(&dp83640->rxts); 1139 INIT_LIST_HEAD(&dp83640->rxpool); 1140 for (i = 0; i < MAX_RXTS; i++) 1141 list_add(&dp83640->rx_pool_data[i].list, &dp83640->rxpool); 1142 1143 phydev->priv = dp83640; 1144 1145 spin_lock_init(&dp83640->rx_lock); 1146 skb_queue_head_init(&dp83640->rx_queue); 1147 skb_queue_head_init(&dp83640->tx_queue); 1148 1149 dp83640->clock = clock; 1150 1151 if (choose_this_phy(clock, phydev)) { 1152 clock->chosen = dp83640; 1153 clock->ptp_clock = ptp_clock_register(&clock->caps, 1154 &phydev->mdio.dev); 1155 if (IS_ERR(clock->ptp_clock)) { 1156 err = PTR_ERR(clock->ptp_clock); 1157 goto no_register; 1158 } 1159 } else 1160 list_add_tail(&dp83640->list, &clock->phylist); 1161 1162 dp83640_clock_put(clock); 1163 return 0; 1164 1165 no_register: 1166 clock->chosen = NULL; 1167 kfree(dp83640); 1168 no_memory: 1169 dp83640_clock_put(clock); 1170 no_clock: 1171 return err; 1172 } 1173 1174 static void dp83640_remove(struct phy_device *phydev) 1175 { 1176 struct dp83640_clock *clock; 1177 struct list_head *this, *next; 1178 struct dp83640_private *tmp, *dp83640 = phydev->priv; 1179 1180 if (phydev->mdio.addr == BROADCAST_ADDR) 1181 return; 1182 1183 enable_status_frames(phydev, false); 1184 cancel_delayed_work_sync(&dp83640->ts_work); 1185 1186 skb_queue_purge(&dp83640->rx_queue); 1187 skb_queue_purge(&dp83640->tx_queue); 1188 1189 clock = dp83640_clock_get(dp83640->clock); 1190 1191 if (dp83640 == clock->chosen) { 1192 ptp_clock_unregister(clock->ptp_clock); 1193 clock->chosen = NULL; 1194 } else { 1195 list_for_each_safe(this, next, &clock->phylist) { 1196 tmp = list_entry(this, struct dp83640_private, list); 1197 if (tmp == dp83640) { 1198 list_del_init(&tmp->list); 1199 break; 1200 } 1201 } 1202 } 1203 1204 dp83640_clock_put(clock); 1205 kfree(dp83640); 1206 } 1207 1208 static int dp83640_config_init(struct phy_device *phydev) 1209 { 1210 struct dp83640_private *dp83640 = phydev->priv; 1211 struct dp83640_clock *clock = dp83640->clock; 1212 1213 if (clock->chosen && !list_empty(&clock->phylist)) 1214 recalibrate(clock); 1215 else { 1216 mutex_lock(&clock->extreg_lock); 1217 enable_broadcast(phydev, clock->page, 1); 1218 mutex_unlock(&clock->extreg_lock); 1219 } 1220 1221 enable_status_frames(phydev, true); 1222 1223 mutex_lock(&clock->extreg_lock); 1224 ext_write(0, phydev, PAGE4, PTP_CTL, PTP_ENABLE); 1225 mutex_unlock(&clock->extreg_lock); 1226 1227 return 0; 1228 } 1229 1230 static int dp83640_ack_interrupt(struct phy_device *phydev) 1231 { 1232 int err = phy_read(phydev, MII_DP83640_MISR); 1233 1234 if (err < 0) 1235 return err; 1236 1237 return 0; 1238 } 1239 1240 static int dp83640_config_intr(struct phy_device *phydev) 1241 { 1242 int micr; 1243 int misr; 1244 int err; 1245 1246 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 1247 misr = phy_read(phydev, MII_DP83640_MISR); 1248 if (misr < 0) 1249 return misr; 1250 misr |= 1251 (MII_DP83640_MISR_ANC_INT_EN | 1252 MII_DP83640_MISR_DUP_INT_EN | 1253 MII_DP83640_MISR_SPD_INT_EN | 1254 MII_DP83640_MISR_LINK_INT_EN); 1255 err = phy_write(phydev, MII_DP83640_MISR, misr); 1256 if (err < 0) 1257 return err; 1258 1259 micr = phy_read(phydev, MII_DP83640_MICR); 1260 if (micr < 0) 1261 return micr; 1262 micr |= 1263 (MII_DP83640_MICR_OE | 1264 MII_DP83640_MICR_IE); 1265 return phy_write(phydev, MII_DP83640_MICR, micr); 1266 } else { 1267 micr = phy_read(phydev, MII_DP83640_MICR); 1268 if (micr < 0) 1269 return micr; 1270 micr &= 1271 ~(MII_DP83640_MICR_OE | 1272 MII_DP83640_MICR_IE); 1273 err = phy_write(phydev, MII_DP83640_MICR, micr); 1274 if (err < 0) 1275 return err; 1276 1277 misr = phy_read(phydev, MII_DP83640_MISR); 1278 if (misr < 0) 1279 return misr; 1280 misr &= 1281 ~(MII_DP83640_MISR_ANC_INT_EN | 1282 MII_DP83640_MISR_DUP_INT_EN | 1283 MII_DP83640_MISR_SPD_INT_EN | 1284 MII_DP83640_MISR_LINK_INT_EN); 1285 return phy_write(phydev, MII_DP83640_MISR, misr); 1286 } 1287 } 1288 1289 static int dp83640_hwtstamp(struct phy_device *phydev, struct ifreq *ifr) 1290 { 1291 struct dp83640_private *dp83640 = phydev->priv; 1292 struct hwtstamp_config cfg; 1293 u16 txcfg0, rxcfg0; 1294 1295 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 1296 return -EFAULT; 1297 1298 if (cfg.flags) /* reserved for future extensions */ 1299 return -EINVAL; 1300 1301 if (cfg.tx_type < 0 || cfg.tx_type > HWTSTAMP_TX_ONESTEP_SYNC) 1302 return -ERANGE; 1303 1304 dp83640->hwts_tx_en = cfg.tx_type; 1305 1306 switch (cfg.rx_filter) { 1307 case HWTSTAMP_FILTER_NONE: 1308 dp83640->hwts_rx_en = 0; 1309 dp83640->layer = 0; 1310 dp83640->version = 0; 1311 break; 1312 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 1313 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 1314 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 1315 dp83640->hwts_rx_en = 1; 1316 dp83640->layer = PTP_CLASS_L4; 1317 dp83640->version = PTP_CLASS_V1; 1318 break; 1319 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1320 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1321 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1322 dp83640->hwts_rx_en = 1; 1323 dp83640->layer = PTP_CLASS_L4; 1324 dp83640->version = PTP_CLASS_V2; 1325 break; 1326 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1327 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1328 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1329 dp83640->hwts_rx_en = 1; 1330 dp83640->layer = PTP_CLASS_L2; 1331 dp83640->version = PTP_CLASS_V2; 1332 break; 1333 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1334 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1335 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1336 dp83640->hwts_rx_en = 1; 1337 dp83640->layer = PTP_CLASS_L4 | PTP_CLASS_L2; 1338 dp83640->version = PTP_CLASS_V2; 1339 break; 1340 default: 1341 return -ERANGE; 1342 } 1343 1344 txcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT; 1345 rxcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT; 1346 1347 if (dp83640->layer & PTP_CLASS_L2) { 1348 txcfg0 |= TX_L2_EN; 1349 rxcfg0 |= RX_L2_EN; 1350 } 1351 if (dp83640->layer & PTP_CLASS_L4) { 1352 txcfg0 |= TX_IPV6_EN | TX_IPV4_EN; 1353 rxcfg0 |= RX_IPV6_EN | RX_IPV4_EN; 1354 } 1355 1356 if (dp83640->hwts_tx_en) 1357 txcfg0 |= TX_TS_EN; 1358 1359 if (dp83640->hwts_tx_en == HWTSTAMP_TX_ONESTEP_SYNC) 1360 txcfg0 |= SYNC_1STEP | CHK_1STEP; 1361 1362 if (dp83640->hwts_rx_en) 1363 rxcfg0 |= RX_TS_EN; 1364 1365 mutex_lock(&dp83640->clock->extreg_lock); 1366 1367 ext_write(0, phydev, PAGE5, PTP_TXCFG0, txcfg0); 1368 ext_write(0, phydev, PAGE5, PTP_RXCFG0, rxcfg0); 1369 1370 mutex_unlock(&dp83640->clock->extreg_lock); 1371 1372 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1373 } 1374 1375 static void rx_timestamp_work(struct work_struct *work) 1376 { 1377 struct dp83640_private *dp83640 = 1378 container_of(work, struct dp83640_private, ts_work.work); 1379 struct sk_buff *skb; 1380 1381 /* Deliver expired packets. */ 1382 while ((skb = skb_dequeue(&dp83640->rx_queue))) { 1383 struct dp83640_skb_info *skb_info; 1384 1385 skb_info = (struct dp83640_skb_info *)skb->cb; 1386 if (!time_after(jiffies, skb_info->tmo)) { 1387 skb_queue_head(&dp83640->rx_queue, skb); 1388 break; 1389 } 1390 1391 netif_rx_ni(skb); 1392 } 1393 1394 if (!skb_queue_empty(&dp83640->rx_queue)) 1395 schedule_delayed_work(&dp83640->ts_work, SKB_TIMESTAMP_TIMEOUT); 1396 } 1397 1398 static bool dp83640_rxtstamp(struct phy_device *phydev, 1399 struct sk_buff *skb, int type) 1400 { 1401 struct dp83640_private *dp83640 = phydev->priv; 1402 struct dp83640_skb_info *skb_info = (struct dp83640_skb_info *)skb->cb; 1403 struct list_head *this, *next; 1404 struct rxts *rxts; 1405 struct skb_shared_hwtstamps *shhwtstamps = NULL; 1406 unsigned long flags; 1407 1408 if (is_status_frame(skb, type)) { 1409 decode_status_frame(dp83640, skb); 1410 kfree_skb(skb); 1411 return true; 1412 } 1413 1414 if (!dp83640->hwts_rx_en) 1415 return false; 1416 1417 if ((type & dp83640->version) == 0 || (type & dp83640->layer) == 0) 1418 return false; 1419 1420 spin_lock_irqsave(&dp83640->rx_lock, flags); 1421 prune_rx_ts(dp83640); 1422 list_for_each_safe(this, next, &dp83640->rxts) { 1423 rxts = list_entry(this, struct rxts, list); 1424 if (match(skb, type, rxts)) { 1425 shhwtstamps = skb_hwtstamps(skb); 1426 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 1427 shhwtstamps->hwtstamp = ns_to_ktime(rxts->ns); 1428 netif_rx_ni(skb); 1429 list_del_init(&rxts->list); 1430 list_add(&rxts->list, &dp83640->rxpool); 1431 break; 1432 } 1433 } 1434 spin_unlock_irqrestore(&dp83640->rx_lock, flags); 1435 1436 if (!shhwtstamps) { 1437 skb_info->ptp_type = type; 1438 skb_info->tmo = jiffies + SKB_TIMESTAMP_TIMEOUT; 1439 skb_queue_tail(&dp83640->rx_queue, skb); 1440 schedule_delayed_work(&dp83640->ts_work, SKB_TIMESTAMP_TIMEOUT); 1441 } 1442 1443 return true; 1444 } 1445 1446 static void dp83640_txtstamp(struct phy_device *phydev, 1447 struct sk_buff *skb, int type) 1448 { 1449 struct dp83640_private *dp83640 = phydev->priv; 1450 1451 switch (dp83640->hwts_tx_en) { 1452 1453 case HWTSTAMP_TX_ONESTEP_SYNC: 1454 if (is_sync(skb, type)) { 1455 kfree_skb(skb); 1456 return; 1457 } 1458 /* fall through */ 1459 case HWTSTAMP_TX_ON: 1460 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1461 skb_queue_tail(&dp83640->tx_queue, skb); 1462 break; 1463 1464 case HWTSTAMP_TX_OFF: 1465 default: 1466 kfree_skb(skb); 1467 break; 1468 } 1469 } 1470 1471 static int dp83640_ts_info(struct phy_device *dev, struct ethtool_ts_info *info) 1472 { 1473 struct dp83640_private *dp83640 = dev->priv; 1474 1475 info->so_timestamping = 1476 SOF_TIMESTAMPING_TX_HARDWARE | 1477 SOF_TIMESTAMPING_RX_HARDWARE | 1478 SOF_TIMESTAMPING_RAW_HARDWARE; 1479 info->phc_index = ptp_clock_index(dp83640->clock->ptp_clock); 1480 info->tx_types = 1481 (1 << HWTSTAMP_TX_OFF) | 1482 (1 << HWTSTAMP_TX_ON) | 1483 (1 << HWTSTAMP_TX_ONESTEP_SYNC); 1484 info->rx_filters = 1485 (1 << HWTSTAMP_FILTER_NONE) | 1486 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) | 1487 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) | 1488 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 1489 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT); 1490 return 0; 1491 } 1492 1493 static struct phy_driver dp83640_driver = { 1494 .phy_id = DP83640_PHY_ID, 1495 .phy_id_mask = 0xfffffff0, 1496 .name = "NatSemi DP83640", 1497 .features = PHY_BASIC_FEATURES, 1498 .flags = PHY_HAS_INTERRUPT, 1499 .probe = dp83640_probe, 1500 .remove = dp83640_remove, 1501 .config_init = dp83640_config_init, 1502 .config_aneg = genphy_config_aneg, 1503 .read_status = genphy_read_status, 1504 .ack_interrupt = dp83640_ack_interrupt, 1505 .config_intr = dp83640_config_intr, 1506 .ts_info = dp83640_ts_info, 1507 .hwtstamp = dp83640_hwtstamp, 1508 .rxtstamp = dp83640_rxtstamp, 1509 .txtstamp = dp83640_txtstamp, 1510 }; 1511 1512 static int __init dp83640_init(void) 1513 { 1514 return phy_driver_register(&dp83640_driver, THIS_MODULE); 1515 } 1516 1517 static void __exit dp83640_exit(void) 1518 { 1519 dp83640_free_clocks(); 1520 phy_driver_unregister(&dp83640_driver); 1521 } 1522 1523 MODULE_DESCRIPTION("National Semiconductor DP83640 PHY driver"); 1524 MODULE_AUTHOR("Richard Cochran <richardcochran@gmail.com>"); 1525 MODULE_LICENSE("GPL"); 1526 1527 module_init(dp83640_init); 1528 module_exit(dp83640_exit); 1529 1530 static struct mdio_device_id __maybe_unused dp83640_tbl[] = { 1531 { DP83640_PHY_ID, 0xfffffff0 }, 1532 { } 1533 }; 1534 1535 MODULE_DEVICE_TABLE(mdio, dp83640_tbl); 1536