1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Driver for the National Semiconductor DP83640 PHYTER 4 * 5 * Copyright (C) 2010 OMICRON electronics GmbH 6 */ 7 8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 9 10 #include <linux/crc32.h> 11 #include <linux/ethtool.h> 12 #include <linux/kernel.h> 13 #include <linux/list.h> 14 #include <linux/mii.h> 15 #include <linux/module.h> 16 #include <linux/net_tstamp.h> 17 #include <linux/netdevice.h> 18 #include <linux/if_vlan.h> 19 #include <linux/phy.h> 20 #include <linux/ptp_classify.h> 21 #include <linux/ptp_clock_kernel.h> 22 23 #include "dp83640_reg.h" 24 25 #define DP83640_PHY_ID 0x20005ce1 26 #define PAGESEL 0x13 27 #define MAX_RXTS 64 28 #define N_EXT_TS 6 29 #define N_PER_OUT 7 30 #define PSF_PTPVER 2 31 #define PSF_EVNT 0x4000 32 #define PSF_RX 0x2000 33 #define PSF_TX 0x1000 34 #define EXT_EVENT 1 35 #define CAL_EVENT 7 36 #define CAL_TRIGGER 1 37 #define DP83640_N_PINS 12 38 39 #define MII_DP83640_MICR 0x11 40 #define MII_DP83640_MISR 0x12 41 42 #define MII_DP83640_MICR_OE 0x1 43 #define MII_DP83640_MICR_IE 0x2 44 45 #define MII_DP83640_MISR_RHF_INT_EN 0x01 46 #define MII_DP83640_MISR_FHF_INT_EN 0x02 47 #define MII_DP83640_MISR_ANC_INT_EN 0x04 48 #define MII_DP83640_MISR_DUP_INT_EN 0x08 49 #define MII_DP83640_MISR_SPD_INT_EN 0x10 50 #define MII_DP83640_MISR_LINK_INT_EN 0x20 51 #define MII_DP83640_MISR_ED_INT_EN 0x40 52 #define MII_DP83640_MISR_LQ_INT_EN 0x80 53 #define MII_DP83640_MISR_ANC_INT 0x400 54 #define MII_DP83640_MISR_DUP_INT 0x800 55 #define MII_DP83640_MISR_SPD_INT 0x1000 56 #define MII_DP83640_MISR_LINK_INT 0x2000 57 #define MII_DP83640_MISR_INT_MASK (MII_DP83640_MISR_ANC_INT |\ 58 MII_DP83640_MISR_DUP_INT |\ 59 MII_DP83640_MISR_SPD_INT |\ 60 MII_DP83640_MISR_LINK_INT) 61 62 /* phyter seems to miss the mark by 16 ns */ 63 #define ADJTIME_FIX 16 64 65 #define SKB_TIMESTAMP_TIMEOUT 2 /* jiffies */ 66 67 #if defined(__BIG_ENDIAN) 68 #define ENDIAN_FLAG 0 69 #elif defined(__LITTLE_ENDIAN) 70 #define ENDIAN_FLAG PSF_ENDIAN 71 #endif 72 73 struct dp83640_skb_info { 74 int ptp_type; 75 unsigned long tmo; 76 }; 77 78 struct phy_rxts { 79 u16 ns_lo; /* ns[15:0] */ 80 u16 ns_hi; /* overflow[1:0], ns[29:16] */ 81 u16 sec_lo; /* sec[15:0] */ 82 u16 sec_hi; /* sec[31:16] */ 83 u16 seqid; /* sequenceId[15:0] */ 84 u16 msgtype; /* messageType[3:0], hash[11:0] */ 85 }; 86 87 struct phy_txts { 88 u16 ns_lo; /* ns[15:0] */ 89 u16 ns_hi; /* overflow[1:0], ns[29:16] */ 90 u16 sec_lo; /* sec[15:0] */ 91 u16 sec_hi; /* sec[31:16] */ 92 }; 93 94 struct rxts { 95 struct list_head list; 96 unsigned long tmo; 97 u64 ns; 98 u16 seqid; 99 u8 msgtype; 100 u16 hash; 101 }; 102 103 struct dp83640_clock; 104 105 struct dp83640_private { 106 struct list_head list; 107 struct dp83640_clock *clock; 108 struct phy_device *phydev; 109 struct mii_timestamper mii_ts; 110 struct delayed_work ts_work; 111 int hwts_tx_en; 112 int hwts_rx_en; 113 int layer; 114 int version; 115 /* remember state of cfg0 during calibration */ 116 int cfg0; 117 /* remember the last event time stamp */ 118 struct phy_txts edata; 119 /* list of rx timestamps */ 120 struct list_head rxts; 121 struct list_head rxpool; 122 struct rxts rx_pool_data[MAX_RXTS]; 123 /* protects above three fields from concurrent access */ 124 spinlock_t rx_lock; 125 /* queues of incoming and outgoing packets */ 126 struct sk_buff_head rx_queue; 127 struct sk_buff_head tx_queue; 128 }; 129 130 struct dp83640_clock { 131 /* keeps the instance in the 'phyter_clocks' list */ 132 struct list_head list; 133 /* we create one clock instance per MII bus */ 134 struct mii_bus *bus; 135 /* protects extended registers from concurrent access */ 136 struct mutex extreg_lock; 137 /* remembers which page was last selected */ 138 int page; 139 /* our advertised capabilities */ 140 struct ptp_clock_info caps; 141 /* protects the three fields below from concurrent access */ 142 struct mutex clock_lock; 143 /* the one phyter from which we shall read */ 144 struct dp83640_private *chosen; 145 /* list of the other attached phyters, not chosen */ 146 struct list_head phylist; 147 /* reference to our PTP hardware clock */ 148 struct ptp_clock *ptp_clock; 149 }; 150 151 /* globals */ 152 153 enum { 154 CALIBRATE_GPIO, 155 PEROUT_GPIO, 156 EXTTS0_GPIO, 157 EXTTS1_GPIO, 158 EXTTS2_GPIO, 159 EXTTS3_GPIO, 160 EXTTS4_GPIO, 161 EXTTS5_GPIO, 162 GPIO_TABLE_SIZE 163 }; 164 165 static int chosen_phy = -1; 166 static ushort gpio_tab[GPIO_TABLE_SIZE] = { 167 1, 2, 3, 4, 8, 9, 10, 11 168 }; 169 170 module_param(chosen_phy, int, 0444); 171 module_param_array(gpio_tab, ushort, NULL, 0444); 172 173 MODULE_PARM_DESC(chosen_phy, \ 174 "The address of the PHY to use for the ancillary clock features"); 175 MODULE_PARM_DESC(gpio_tab, \ 176 "Which GPIO line to use for which purpose: cal,perout,extts1,...,extts6"); 177 178 static void dp83640_gpio_defaults(struct ptp_pin_desc *pd) 179 { 180 int i, index; 181 182 for (i = 0; i < DP83640_N_PINS; i++) { 183 snprintf(pd[i].name, sizeof(pd[i].name), "GPIO%d", 1 + i); 184 pd[i].index = i; 185 } 186 187 for (i = 0; i < GPIO_TABLE_SIZE; i++) { 188 if (gpio_tab[i] < 1 || gpio_tab[i] > DP83640_N_PINS) { 189 pr_err("gpio_tab[%d]=%hu out of range", i, gpio_tab[i]); 190 return; 191 } 192 } 193 194 index = gpio_tab[CALIBRATE_GPIO] - 1; 195 pd[index].func = PTP_PF_PHYSYNC; 196 pd[index].chan = 0; 197 198 index = gpio_tab[PEROUT_GPIO] - 1; 199 pd[index].func = PTP_PF_PEROUT; 200 pd[index].chan = 0; 201 202 for (i = EXTTS0_GPIO; i < GPIO_TABLE_SIZE; i++) { 203 index = gpio_tab[i] - 1; 204 pd[index].func = PTP_PF_EXTTS; 205 pd[index].chan = i - EXTTS0_GPIO; 206 } 207 } 208 209 /* a list of clocks and a mutex to protect it */ 210 static LIST_HEAD(phyter_clocks); 211 static DEFINE_MUTEX(phyter_clocks_lock); 212 213 static void rx_timestamp_work(struct work_struct *work); 214 215 /* extended register access functions */ 216 217 #define BROADCAST_ADDR 31 218 219 static inline int broadcast_write(struct phy_device *phydev, u32 regnum, 220 u16 val) 221 { 222 return mdiobus_write(phydev->mdio.bus, BROADCAST_ADDR, regnum, val); 223 } 224 225 /* Caller must hold extreg_lock. */ 226 static int ext_read(struct phy_device *phydev, int page, u32 regnum) 227 { 228 struct dp83640_private *dp83640 = phydev->priv; 229 int val; 230 231 if (dp83640->clock->page != page) { 232 broadcast_write(phydev, PAGESEL, page); 233 dp83640->clock->page = page; 234 } 235 val = phy_read(phydev, regnum); 236 237 return val; 238 } 239 240 /* Caller must hold extreg_lock. */ 241 static void ext_write(int broadcast, struct phy_device *phydev, 242 int page, u32 regnum, u16 val) 243 { 244 struct dp83640_private *dp83640 = phydev->priv; 245 246 if (dp83640->clock->page != page) { 247 broadcast_write(phydev, PAGESEL, page); 248 dp83640->clock->page = page; 249 } 250 if (broadcast) 251 broadcast_write(phydev, regnum, val); 252 else 253 phy_write(phydev, regnum, val); 254 } 255 256 /* Caller must hold extreg_lock. */ 257 static int tdr_write(int bc, struct phy_device *dev, 258 const struct timespec64 *ts, u16 cmd) 259 { 260 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec & 0xffff);/* ns[15:0] */ 261 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec >> 16); /* ns[31:16] */ 262 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec & 0xffff); /* sec[15:0] */ 263 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec >> 16); /* sec[31:16]*/ 264 265 ext_write(bc, dev, PAGE4, PTP_CTL, cmd); 266 267 return 0; 268 } 269 270 /* convert phy timestamps into driver timestamps */ 271 272 static void phy2rxts(struct phy_rxts *p, struct rxts *rxts) 273 { 274 u32 sec; 275 276 sec = p->sec_lo; 277 sec |= p->sec_hi << 16; 278 279 rxts->ns = p->ns_lo; 280 rxts->ns |= (p->ns_hi & 0x3fff) << 16; 281 rxts->ns += ((u64)sec) * 1000000000ULL; 282 rxts->seqid = p->seqid; 283 rxts->msgtype = (p->msgtype >> 12) & 0xf; 284 rxts->hash = p->msgtype & 0x0fff; 285 rxts->tmo = jiffies + SKB_TIMESTAMP_TIMEOUT; 286 } 287 288 static u64 phy2txts(struct phy_txts *p) 289 { 290 u64 ns; 291 u32 sec; 292 293 sec = p->sec_lo; 294 sec |= p->sec_hi << 16; 295 296 ns = p->ns_lo; 297 ns |= (p->ns_hi & 0x3fff) << 16; 298 ns += ((u64)sec) * 1000000000ULL; 299 300 return ns; 301 } 302 303 static int periodic_output(struct dp83640_clock *clock, 304 struct ptp_clock_request *clkreq, bool on, 305 int trigger) 306 { 307 struct dp83640_private *dp83640 = clock->chosen; 308 struct phy_device *phydev = dp83640->phydev; 309 u32 sec, nsec, pwidth; 310 u16 gpio, ptp_trig, val; 311 312 if (on) { 313 gpio = 1 + ptp_find_pin(clock->ptp_clock, PTP_PF_PEROUT, 314 trigger); 315 if (gpio < 1) 316 return -EINVAL; 317 } else { 318 gpio = 0; 319 } 320 321 ptp_trig = TRIG_WR | 322 (trigger & TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT | 323 (gpio & TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT | 324 TRIG_PER | 325 TRIG_PULSE; 326 327 val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT; 328 329 if (!on) { 330 val |= TRIG_DIS; 331 mutex_lock(&clock->extreg_lock); 332 ext_write(0, phydev, PAGE5, PTP_TRIG, ptp_trig); 333 ext_write(0, phydev, PAGE4, PTP_CTL, val); 334 mutex_unlock(&clock->extreg_lock); 335 return 0; 336 } 337 338 sec = clkreq->perout.start.sec; 339 nsec = clkreq->perout.start.nsec; 340 pwidth = clkreq->perout.period.sec * 1000000000UL; 341 pwidth += clkreq->perout.period.nsec; 342 pwidth /= 2; 343 344 mutex_lock(&clock->extreg_lock); 345 346 ext_write(0, phydev, PAGE5, PTP_TRIG, ptp_trig); 347 348 /*load trigger*/ 349 val |= TRIG_LOAD; 350 ext_write(0, phydev, PAGE4, PTP_CTL, val); 351 ext_write(0, phydev, PAGE4, PTP_TDR, nsec & 0xffff); /* ns[15:0] */ 352 ext_write(0, phydev, PAGE4, PTP_TDR, nsec >> 16); /* ns[31:16] */ 353 ext_write(0, phydev, PAGE4, PTP_TDR, sec & 0xffff); /* sec[15:0] */ 354 ext_write(0, phydev, PAGE4, PTP_TDR, sec >> 16); /* sec[31:16] */ 355 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth & 0xffff); /* ns[15:0] */ 356 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth >> 16); /* ns[31:16] */ 357 /* Triggers 0 and 1 has programmable pulsewidth2 */ 358 if (trigger < 2) { 359 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth & 0xffff); 360 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth >> 16); 361 } 362 363 /*enable trigger*/ 364 val &= ~TRIG_LOAD; 365 val |= TRIG_EN; 366 ext_write(0, phydev, PAGE4, PTP_CTL, val); 367 368 mutex_unlock(&clock->extreg_lock); 369 return 0; 370 } 371 372 /* ptp clock methods */ 373 374 static int ptp_dp83640_adjfine(struct ptp_clock_info *ptp, long scaled_ppm) 375 { 376 struct dp83640_clock *clock = 377 container_of(ptp, struct dp83640_clock, caps); 378 struct phy_device *phydev = clock->chosen->phydev; 379 u64 rate; 380 int neg_adj = 0; 381 u16 hi, lo; 382 383 if (scaled_ppm < 0) { 384 neg_adj = 1; 385 scaled_ppm = -scaled_ppm; 386 } 387 rate = scaled_ppm; 388 rate <<= 13; 389 rate = div_u64(rate, 15625); 390 391 hi = (rate >> 16) & PTP_RATE_HI_MASK; 392 if (neg_adj) 393 hi |= PTP_RATE_DIR; 394 395 lo = rate & 0xffff; 396 397 mutex_lock(&clock->extreg_lock); 398 399 ext_write(1, phydev, PAGE4, PTP_RATEH, hi); 400 ext_write(1, phydev, PAGE4, PTP_RATEL, lo); 401 402 mutex_unlock(&clock->extreg_lock); 403 404 return 0; 405 } 406 407 static int ptp_dp83640_adjtime(struct ptp_clock_info *ptp, s64 delta) 408 { 409 struct dp83640_clock *clock = 410 container_of(ptp, struct dp83640_clock, caps); 411 struct phy_device *phydev = clock->chosen->phydev; 412 struct timespec64 ts; 413 int err; 414 415 delta += ADJTIME_FIX; 416 417 ts = ns_to_timespec64(delta); 418 419 mutex_lock(&clock->extreg_lock); 420 421 err = tdr_write(1, phydev, &ts, PTP_STEP_CLK); 422 423 mutex_unlock(&clock->extreg_lock); 424 425 return err; 426 } 427 428 static int ptp_dp83640_gettime(struct ptp_clock_info *ptp, 429 struct timespec64 *ts) 430 { 431 struct dp83640_clock *clock = 432 container_of(ptp, struct dp83640_clock, caps); 433 struct phy_device *phydev = clock->chosen->phydev; 434 unsigned int val[4]; 435 436 mutex_lock(&clock->extreg_lock); 437 438 ext_write(0, phydev, PAGE4, PTP_CTL, PTP_RD_CLK); 439 440 val[0] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[15:0] */ 441 val[1] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[31:16] */ 442 val[2] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[15:0] */ 443 val[3] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[31:16] */ 444 445 mutex_unlock(&clock->extreg_lock); 446 447 ts->tv_nsec = val[0] | (val[1] << 16); 448 ts->tv_sec = val[2] | (val[3] << 16); 449 450 return 0; 451 } 452 453 static int ptp_dp83640_settime(struct ptp_clock_info *ptp, 454 const struct timespec64 *ts) 455 { 456 struct dp83640_clock *clock = 457 container_of(ptp, struct dp83640_clock, caps); 458 struct phy_device *phydev = clock->chosen->phydev; 459 int err; 460 461 mutex_lock(&clock->extreg_lock); 462 463 err = tdr_write(1, phydev, ts, PTP_LOAD_CLK); 464 465 mutex_unlock(&clock->extreg_lock); 466 467 return err; 468 } 469 470 static int ptp_dp83640_enable(struct ptp_clock_info *ptp, 471 struct ptp_clock_request *rq, int on) 472 { 473 struct dp83640_clock *clock = 474 container_of(ptp, struct dp83640_clock, caps); 475 struct phy_device *phydev = clock->chosen->phydev; 476 unsigned int index; 477 u16 evnt, event_num, gpio_num; 478 479 switch (rq->type) { 480 case PTP_CLK_REQ_EXTTS: 481 /* Reject requests with unsupported flags */ 482 if (rq->extts.flags & ~(PTP_ENABLE_FEATURE | 483 PTP_RISING_EDGE | 484 PTP_FALLING_EDGE | 485 PTP_STRICT_FLAGS)) 486 return -EOPNOTSUPP; 487 488 /* Reject requests to enable time stamping on both edges. */ 489 if ((rq->extts.flags & PTP_STRICT_FLAGS) && 490 (rq->extts.flags & PTP_ENABLE_FEATURE) && 491 (rq->extts.flags & PTP_EXTTS_EDGES) == PTP_EXTTS_EDGES) 492 return -EOPNOTSUPP; 493 494 index = rq->extts.index; 495 if (index >= N_EXT_TS) 496 return -EINVAL; 497 event_num = EXT_EVENT + index; 498 evnt = EVNT_WR | (event_num & EVNT_SEL_MASK) << EVNT_SEL_SHIFT; 499 if (on) { 500 gpio_num = 1 + ptp_find_pin(clock->ptp_clock, 501 PTP_PF_EXTTS, index); 502 if (gpio_num < 1) 503 return -EINVAL; 504 evnt |= (gpio_num & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT; 505 if (rq->extts.flags & PTP_FALLING_EDGE) 506 evnt |= EVNT_FALL; 507 else 508 evnt |= EVNT_RISE; 509 } 510 mutex_lock(&clock->extreg_lock); 511 ext_write(0, phydev, PAGE5, PTP_EVNT, evnt); 512 mutex_unlock(&clock->extreg_lock); 513 return 0; 514 515 case PTP_CLK_REQ_PEROUT: 516 /* Reject requests with unsupported flags */ 517 if (rq->perout.flags) 518 return -EOPNOTSUPP; 519 if (rq->perout.index >= N_PER_OUT) 520 return -EINVAL; 521 return periodic_output(clock, rq, on, rq->perout.index); 522 523 default: 524 break; 525 } 526 527 return -EOPNOTSUPP; 528 } 529 530 static int ptp_dp83640_verify(struct ptp_clock_info *ptp, unsigned int pin, 531 enum ptp_pin_function func, unsigned int chan) 532 { 533 struct dp83640_clock *clock = 534 container_of(ptp, struct dp83640_clock, caps); 535 536 if (clock->caps.pin_config[pin].func == PTP_PF_PHYSYNC && 537 !list_empty(&clock->phylist)) 538 return 1; 539 540 if (func == PTP_PF_PHYSYNC) 541 return 1; 542 543 return 0; 544 } 545 546 static u8 status_frame_dst[6] = { 0x01, 0x1B, 0x19, 0x00, 0x00, 0x00 }; 547 static u8 status_frame_src[6] = { 0x08, 0x00, 0x17, 0x0B, 0x6B, 0x0F }; 548 549 static void enable_status_frames(struct phy_device *phydev, bool on) 550 { 551 struct dp83640_private *dp83640 = phydev->priv; 552 struct dp83640_clock *clock = dp83640->clock; 553 u16 cfg0 = 0, ver; 554 555 if (on) 556 cfg0 = PSF_EVNT_EN | PSF_RXTS_EN | PSF_TXTS_EN | ENDIAN_FLAG; 557 558 ver = (PSF_PTPVER & VERSIONPTP_MASK) << VERSIONPTP_SHIFT; 559 560 mutex_lock(&clock->extreg_lock); 561 562 ext_write(0, phydev, PAGE5, PSF_CFG0, cfg0); 563 ext_write(0, phydev, PAGE6, PSF_CFG1, ver); 564 565 mutex_unlock(&clock->extreg_lock); 566 567 if (!phydev->attached_dev) { 568 phydev_warn(phydev, 569 "expected to find an attached netdevice\n"); 570 return; 571 } 572 573 if (on) { 574 if (dev_mc_add(phydev->attached_dev, status_frame_dst)) 575 phydev_warn(phydev, "failed to add mc address\n"); 576 } else { 577 if (dev_mc_del(phydev->attached_dev, status_frame_dst)) 578 phydev_warn(phydev, "failed to delete mc address\n"); 579 } 580 } 581 582 static bool is_status_frame(struct sk_buff *skb, int type) 583 { 584 struct ethhdr *h = eth_hdr(skb); 585 586 if (PTP_CLASS_V2_L2 == type && 587 !memcmp(h->h_source, status_frame_src, sizeof(status_frame_src))) 588 return true; 589 else 590 return false; 591 } 592 593 static int expired(struct rxts *rxts) 594 { 595 return time_after(jiffies, rxts->tmo); 596 } 597 598 /* Caller must hold rx_lock. */ 599 static void prune_rx_ts(struct dp83640_private *dp83640) 600 { 601 struct list_head *this, *next; 602 struct rxts *rxts; 603 604 list_for_each_safe(this, next, &dp83640->rxts) { 605 rxts = list_entry(this, struct rxts, list); 606 if (expired(rxts)) { 607 list_del_init(&rxts->list); 608 list_add(&rxts->list, &dp83640->rxpool); 609 } 610 } 611 } 612 613 /* synchronize the phyters so they act as one clock */ 614 615 static void enable_broadcast(struct phy_device *phydev, int init_page, int on) 616 { 617 int val; 618 phy_write(phydev, PAGESEL, 0); 619 val = phy_read(phydev, PHYCR2); 620 if (on) 621 val |= BC_WRITE; 622 else 623 val &= ~BC_WRITE; 624 phy_write(phydev, PHYCR2, val); 625 phy_write(phydev, PAGESEL, init_page); 626 } 627 628 static void recalibrate(struct dp83640_clock *clock) 629 { 630 s64 now, diff; 631 struct phy_txts event_ts; 632 struct timespec64 ts; 633 struct list_head *this; 634 struct dp83640_private *tmp; 635 struct phy_device *master = clock->chosen->phydev; 636 u16 cal_gpio, cfg0, evnt, ptp_trig, trigger, val; 637 638 trigger = CAL_TRIGGER; 639 cal_gpio = 1 + ptp_find_pin_unlocked(clock->ptp_clock, PTP_PF_PHYSYNC, 0); 640 if (cal_gpio < 1) { 641 pr_err("PHY calibration pin not available - PHY is not calibrated."); 642 return; 643 } 644 645 mutex_lock(&clock->extreg_lock); 646 647 /* 648 * enable broadcast, disable status frames, enable ptp clock 649 */ 650 list_for_each(this, &clock->phylist) { 651 tmp = list_entry(this, struct dp83640_private, list); 652 enable_broadcast(tmp->phydev, clock->page, 1); 653 tmp->cfg0 = ext_read(tmp->phydev, PAGE5, PSF_CFG0); 654 ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, 0); 655 ext_write(0, tmp->phydev, PAGE4, PTP_CTL, PTP_ENABLE); 656 } 657 enable_broadcast(master, clock->page, 1); 658 cfg0 = ext_read(master, PAGE5, PSF_CFG0); 659 ext_write(0, master, PAGE5, PSF_CFG0, 0); 660 ext_write(0, master, PAGE4, PTP_CTL, PTP_ENABLE); 661 662 /* 663 * enable an event timestamp 664 */ 665 evnt = EVNT_WR | EVNT_RISE | EVNT_SINGLE; 666 evnt |= (CAL_EVENT & EVNT_SEL_MASK) << EVNT_SEL_SHIFT; 667 evnt |= (cal_gpio & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT; 668 669 list_for_each(this, &clock->phylist) { 670 tmp = list_entry(this, struct dp83640_private, list); 671 ext_write(0, tmp->phydev, PAGE5, PTP_EVNT, evnt); 672 } 673 ext_write(0, master, PAGE5, PTP_EVNT, evnt); 674 675 /* 676 * configure a trigger 677 */ 678 ptp_trig = TRIG_WR | TRIG_IF_LATE | TRIG_PULSE; 679 ptp_trig |= (trigger & TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT; 680 ptp_trig |= (cal_gpio & TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT; 681 ext_write(0, master, PAGE5, PTP_TRIG, ptp_trig); 682 683 /* load trigger */ 684 val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT; 685 val |= TRIG_LOAD; 686 ext_write(0, master, PAGE4, PTP_CTL, val); 687 688 /* enable trigger */ 689 val &= ~TRIG_LOAD; 690 val |= TRIG_EN; 691 ext_write(0, master, PAGE4, PTP_CTL, val); 692 693 /* disable trigger */ 694 val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT; 695 val |= TRIG_DIS; 696 ext_write(0, master, PAGE4, PTP_CTL, val); 697 698 /* 699 * read out and correct offsets 700 */ 701 val = ext_read(master, PAGE4, PTP_STS); 702 phydev_info(master, "master PTP_STS 0x%04hx\n", val); 703 val = ext_read(master, PAGE4, PTP_ESTS); 704 phydev_info(master, "master PTP_ESTS 0x%04hx\n", val); 705 event_ts.ns_lo = ext_read(master, PAGE4, PTP_EDATA); 706 event_ts.ns_hi = ext_read(master, PAGE4, PTP_EDATA); 707 event_ts.sec_lo = ext_read(master, PAGE4, PTP_EDATA); 708 event_ts.sec_hi = ext_read(master, PAGE4, PTP_EDATA); 709 now = phy2txts(&event_ts); 710 711 list_for_each(this, &clock->phylist) { 712 tmp = list_entry(this, struct dp83640_private, list); 713 val = ext_read(tmp->phydev, PAGE4, PTP_STS); 714 phydev_info(tmp->phydev, "slave PTP_STS 0x%04hx\n", val); 715 val = ext_read(tmp->phydev, PAGE4, PTP_ESTS); 716 phydev_info(tmp->phydev, "slave PTP_ESTS 0x%04hx\n", val); 717 event_ts.ns_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA); 718 event_ts.ns_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA); 719 event_ts.sec_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA); 720 event_ts.sec_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA); 721 diff = now - (s64) phy2txts(&event_ts); 722 phydev_info(tmp->phydev, "slave offset %lld nanoseconds\n", 723 diff); 724 diff += ADJTIME_FIX; 725 ts = ns_to_timespec64(diff); 726 tdr_write(0, tmp->phydev, &ts, PTP_STEP_CLK); 727 } 728 729 /* 730 * restore status frames 731 */ 732 list_for_each(this, &clock->phylist) { 733 tmp = list_entry(this, struct dp83640_private, list); 734 ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, tmp->cfg0); 735 } 736 ext_write(0, master, PAGE5, PSF_CFG0, cfg0); 737 738 mutex_unlock(&clock->extreg_lock); 739 } 740 741 /* time stamping methods */ 742 743 static inline u16 exts_chan_to_edata(int ch) 744 { 745 return 1 << ((ch + EXT_EVENT) * 2); 746 } 747 748 static int decode_evnt(struct dp83640_private *dp83640, 749 void *data, int len, u16 ests) 750 { 751 struct phy_txts *phy_txts; 752 struct ptp_clock_event event; 753 int i, parsed; 754 int words = (ests >> EVNT_TS_LEN_SHIFT) & EVNT_TS_LEN_MASK; 755 u16 ext_status = 0; 756 757 /* calculate length of the event timestamp status message */ 758 if (ests & MULT_EVNT) 759 parsed = (words + 2) * sizeof(u16); 760 else 761 parsed = (words + 1) * sizeof(u16); 762 763 /* check if enough data is available */ 764 if (len < parsed) 765 return len; 766 767 if (ests & MULT_EVNT) { 768 ext_status = *(u16 *) data; 769 data += sizeof(ext_status); 770 } 771 772 phy_txts = data; 773 774 switch (words) { 775 case 3: 776 dp83640->edata.sec_hi = phy_txts->sec_hi; 777 fallthrough; 778 case 2: 779 dp83640->edata.sec_lo = phy_txts->sec_lo; 780 fallthrough; 781 case 1: 782 dp83640->edata.ns_hi = phy_txts->ns_hi; 783 fallthrough; 784 case 0: 785 dp83640->edata.ns_lo = phy_txts->ns_lo; 786 } 787 788 if (!ext_status) { 789 i = ((ests >> EVNT_NUM_SHIFT) & EVNT_NUM_MASK) - EXT_EVENT; 790 ext_status = exts_chan_to_edata(i); 791 } 792 793 event.type = PTP_CLOCK_EXTTS; 794 event.timestamp = phy2txts(&dp83640->edata); 795 796 /* Compensate for input path and synchronization delays */ 797 event.timestamp -= 35; 798 799 for (i = 0; i < N_EXT_TS; i++) { 800 if (ext_status & exts_chan_to_edata(i)) { 801 event.index = i; 802 ptp_clock_event(dp83640->clock->ptp_clock, &event); 803 } 804 } 805 806 return parsed; 807 } 808 809 #define DP83640_PACKET_HASH_LEN 10 810 811 static int match(struct sk_buff *skb, unsigned int type, struct rxts *rxts) 812 { 813 struct ptp_header *hdr; 814 u8 msgtype; 815 u16 seqid; 816 u16 hash; 817 818 /* check sequenceID, messageType, 12 bit hash of offset 20-29 */ 819 820 hdr = ptp_parse_header(skb, type); 821 if (!hdr) 822 return 0; 823 824 msgtype = ptp_get_msgtype(hdr, type); 825 826 if (rxts->msgtype != (msgtype & 0xf)) 827 return 0; 828 829 seqid = be16_to_cpu(hdr->sequence_id); 830 if (rxts->seqid != seqid) 831 return 0; 832 833 hash = ether_crc(DP83640_PACKET_HASH_LEN, 834 (unsigned char *)&hdr->source_port_identity) >> 20; 835 if (rxts->hash != hash) 836 return 0; 837 838 return 1; 839 } 840 841 static void decode_rxts(struct dp83640_private *dp83640, 842 struct phy_rxts *phy_rxts) 843 { 844 struct rxts *rxts; 845 struct skb_shared_hwtstamps *shhwtstamps = NULL; 846 struct sk_buff *skb; 847 unsigned long flags; 848 u8 overflow; 849 850 overflow = (phy_rxts->ns_hi >> 14) & 0x3; 851 if (overflow) 852 pr_debug("rx timestamp queue overflow, count %d\n", overflow); 853 854 spin_lock_irqsave(&dp83640->rx_lock, flags); 855 856 prune_rx_ts(dp83640); 857 858 if (list_empty(&dp83640->rxpool)) { 859 pr_debug("rx timestamp pool is empty\n"); 860 goto out; 861 } 862 rxts = list_first_entry(&dp83640->rxpool, struct rxts, list); 863 list_del_init(&rxts->list); 864 phy2rxts(phy_rxts, rxts); 865 866 spin_lock(&dp83640->rx_queue.lock); 867 skb_queue_walk(&dp83640->rx_queue, skb) { 868 struct dp83640_skb_info *skb_info; 869 870 skb_info = (struct dp83640_skb_info *)skb->cb; 871 if (match(skb, skb_info->ptp_type, rxts)) { 872 __skb_unlink(skb, &dp83640->rx_queue); 873 shhwtstamps = skb_hwtstamps(skb); 874 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 875 shhwtstamps->hwtstamp = ns_to_ktime(rxts->ns); 876 list_add(&rxts->list, &dp83640->rxpool); 877 break; 878 } 879 } 880 spin_unlock(&dp83640->rx_queue.lock); 881 882 if (!shhwtstamps) 883 list_add_tail(&rxts->list, &dp83640->rxts); 884 out: 885 spin_unlock_irqrestore(&dp83640->rx_lock, flags); 886 887 if (shhwtstamps) 888 netif_rx_ni(skb); 889 } 890 891 static void decode_txts(struct dp83640_private *dp83640, 892 struct phy_txts *phy_txts) 893 { 894 struct skb_shared_hwtstamps shhwtstamps; 895 struct dp83640_skb_info *skb_info; 896 struct sk_buff *skb; 897 u8 overflow; 898 u64 ns; 899 900 /* We must already have the skb that triggered this. */ 901 again: 902 skb = skb_dequeue(&dp83640->tx_queue); 903 if (!skb) { 904 pr_debug("have timestamp but tx_queue empty\n"); 905 return; 906 } 907 908 overflow = (phy_txts->ns_hi >> 14) & 0x3; 909 if (overflow) { 910 pr_debug("tx timestamp queue overflow, count %d\n", overflow); 911 while (skb) { 912 kfree_skb(skb); 913 skb = skb_dequeue(&dp83640->tx_queue); 914 } 915 return; 916 } 917 skb_info = (struct dp83640_skb_info *)skb->cb; 918 if (time_after(jiffies, skb_info->tmo)) { 919 kfree_skb(skb); 920 goto again; 921 } 922 923 ns = phy2txts(phy_txts); 924 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 925 shhwtstamps.hwtstamp = ns_to_ktime(ns); 926 skb_complete_tx_timestamp(skb, &shhwtstamps); 927 } 928 929 static void decode_status_frame(struct dp83640_private *dp83640, 930 struct sk_buff *skb) 931 { 932 struct phy_rxts *phy_rxts; 933 struct phy_txts *phy_txts; 934 u8 *ptr; 935 int len, size; 936 u16 ests, type; 937 938 ptr = skb->data + 2; 939 940 for (len = skb_headlen(skb) - 2; len > sizeof(type); len -= size) { 941 942 type = *(u16 *)ptr; 943 ests = type & 0x0fff; 944 type = type & 0xf000; 945 len -= sizeof(type); 946 ptr += sizeof(type); 947 948 if (PSF_RX == type && len >= sizeof(*phy_rxts)) { 949 950 phy_rxts = (struct phy_rxts *) ptr; 951 decode_rxts(dp83640, phy_rxts); 952 size = sizeof(*phy_rxts); 953 954 } else if (PSF_TX == type && len >= sizeof(*phy_txts)) { 955 956 phy_txts = (struct phy_txts *) ptr; 957 decode_txts(dp83640, phy_txts); 958 size = sizeof(*phy_txts); 959 960 } else if (PSF_EVNT == type) { 961 962 size = decode_evnt(dp83640, ptr, len, ests); 963 964 } else { 965 size = 0; 966 break; 967 } 968 ptr += size; 969 } 970 } 971 972 static int is_sync(struct sk_buff *skb, int type) 973 { 974 struct ptp_header *hdr; 975 976 hdr = ptp_parse_header(skb, type); 977 if (!hdr) 978 return 0; 979 980 return ptp_get_msgtype(hdr, type) == PTP_MSGTYPE_SYNC; 981 } 982 983 static void dp83640_free_clocks(void) 984 { 985 struct dp83640_clock *clock; 986 struct list_head *this, *next; 987 988 mutex_lock(&phyter_clocks_lock); 989 990 list_for_each_safe(this, next, &phyter_clocks) { 991 clock = list_entry(this, struct dp83640_clock, list); 992 if (!list_empty(&clock->phylist)) { 993 pr_warn("phy list non-empty while unloading\n"); 994 BUG(); 995 } 996 list_del(&clock->list); 997 mutex_destroy(&clock->extreg_lock); 998 mutex_destroy(&clock->clock_lock); 999 put_device(&clock->bus->dev); 1000 kfree(clock->caps.pin_config); 1001 kfree(clock); 1002 } 1003 1004 mutex_unlock(&phyter_clocks_lock); 1005 } 1006 1007 static void dp83640_clock_init(struct dp83640_clock *clock, struct mii_bus *bus) 1008 { 1009 INIT_LIST_HEAD(&clock->list); 1010 clock->bus = bus; 1011 mutex_init(&clock->extreg_lock); 1012 mutex_init(&clock->clock_lock); 1013 INIT_LIST_HEAD(&clock->phylist); 1014 clock->caps.owner = THIS_MODULE; 1015 sprintf(clock->caps.name, "dp83640 timer"); 1016 clock->caps.max_adj = 1953124; 1017 clock->caps.n_alarm = 0; 1018 clock->caps.n_ext_ts = N_EXT_TS; 1019 clock->caps.n_per_out = N_PER_OUT; 1020 clock->caps.n_pins = DP83640_N_PINS; 1021 clock->caps.pps = 0; 1022 clock->caps.adjfine = ptp_dp83640_adjfine; 1023 clock->caps.adjtime = ptp_dp83640_adjtime; 1024 clock->caps.gettime64 = ptp_dp83640_gettime; 1025 clock->caps.settime64 = ptp_dp83640_settime; 1026 clock->caps.enable = ptp_dp83640_enable; 1027 clock->caps.verify = ptp_dp83640_verify; 1028 /* 1029 * Convert the module param defaults into a dynamic pin configuration. 1030 */ 1031 dp83640_gpio_defaults(clock->caps.pin_config); 1032 /* 1033 * Get a reference to this bus instance. 1034 */ 1035 get_device(&bus->dev); 1036 } 1037 1038 static int choose_this_phy(struct dp83640_clock *clock, 1039 struct phy_device *phydev) 1040 { 1041 if (chosen_phy == -1 && !clock->chosen) 1042 return 1; 1043 1044 if (chosen_phy == phydev->mdio.addr) 1045 return 1; 1046 1047 return 0; 1048 } 1049 1050 static struct dp83640_clock *dp83640_clock_get(struct dp83640_clock *clock) 1051 { 1052 if (clock) 1053 mutex_lock(&clock->clock_lock); 1054 return clock; 1055 } 1056 1057 /* 1058 * Look up and lock a clock by bus instance. 1059 * If there is no clock for this bus, then create it first. 1060 */ 1061 static struct dp83640_clock *dp83640_clock_get_bus(struct mii_bus *bus) 1062 { 1063 struct dp83640_clock *clock = NULL, *tmp; 1064 struct list_head *this; 1065 1066 mutex_lock(&phyter_clocks_lock); 1067 1068 list_for_each(this, &phyter_clocks) { 1069 tmp = list_entry(this, struct dp83640_clock, list); 1070 if (tmp->bus == bus) { 1071 clock = tmp; 1072 break; 1073 } 1074 } 1075 if (clock) 1076 goto out; 1077 1078 clock = kzalloc(sizeof(struct dp83640_clock), GFP_KERNEL); 1079 if (!clock) 1080 goto out; 1081 1082 clock->caps.pin_config = kcalloc(DP83640_N_PINS, 1083 sizeof(struct ptp_pin_desc), 1084 GFP_KERNEL); 1085 if (!clock->caps.pin_config) { 1086 kfree(clock); 1087 clock = NULL; 1088 goto out; 1089 } 1090 dp83640_clock_init(clock, bus); 1091 list_add_tail(&clock->list, &phyter_clocks); 1092 out: 1093 mutex_unlock(&phyter_clocks_lock); 1094 1095 return dp83640_clock_get(clock); 1096 } 1097 1098 static void dp83640_clock_put(struct dp83640_clock *clock) 1099 { 1100 mutex_unlock(&clock->clock_lock); 1101 } 1102 1103 static int dp83640_soft_reset(struct phy_device *phydev) 1104 { 1105 int ret; 1106 1107 ret = genphy_soft_reset(phydev); 1108 if (ret < 0) 1109 return ret; 1110 1111 /* From DP83640 datasheet: "Software driver code must wait 3 us 1112 * following a software reset before allowing further serial MII 1113 * operations with the DP83640." 1114 */ 1115 udelay(10); /* Taking udelay inaccuracy into account */ 1116 1117 return 0; 1118 } 1119 1120 static int dp83640_config_init(struct phy_device *phydev) 1121 { 1122 struct dp83640_private *dp83640 = phydev->priv; 1123 struct dp83640_clock *clock = dp83640->clock; 1124 1125 if (clock->chosen && !list_empty(&clock->phylist)) 1126 recalibrate(clock); 1127 else { 1128 mutex_lock(&clock->extreg_lock); 1129 enable_broadcast(phydev, clock->page, 1); 1130 mutex_unlock(&clock->extreg_lock); 1131 } 1132 1133 enable_status_frames(phydev, true); 1134 1135 mutex_lock(&clock->extreg_lock); 1136 ext_write(0, phydev, PAGE4, PTP_CTL, PTP_ENABLE); 1137 mutex_unlock(&clock->extreg_lock); 1138 1139 return 0; 1140 } 1141 1142 static int dp83640_ack_interrupt(struct phy_device *phydev) 1143 { 1144 int err = phy_read(phydev, MII_DP83640_MISR); 1145 1146 if (err < 0) 1147 return err; 1148 1149 return 0; 1150 } 1151 1152 static int dp83640_config_intr(struct phy_device *phydev) 1153 { 1154 int micr; 1155 int misr; 1156 int err; 1157 1158 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 1159 err = dp83640_ack_interrupt(phydev); 1160 if (err) 1161 return err; 1162 1163 misr = phy_read(phydev, MII_DP83640_MISR); 1164 if (misr < 0) 1165 return misr; 1166 misr |= 1167 (MII_DP83640_MISR_ANC_INT_EN | 1168 MII_DP83640_MISR_DUP_INT_EN | 1169 MII_DP83640_MISR_SPD_INT_EN | 1170 MII_DP83640_MISR_LINK_INT_EN); 1171 err = phy_write(phydev, MII_DP83640_MISR, misr); 1172 if (err < 0) 1173 return err; 1174 1175 micr = phy_read(phydev, MII_DP83640_MICR); 1176 if (micr < 0) 1177 return micr; 1178 micr |= 1179 (MII_DP83640_MICR_OE | 1180 MII_DP83640_MICR_IE); 1181 return phy_write(phydev, MII_DP83640_MICR, micr); 1182 } else { 1183 micr = phy_read(phydev, MII_DP83640_MICR); 1184 if (micr < 0) 1185 return micr; 1186 micr &= 1187 ~(MII_DP83640_MICR_OE | 1188 MII_DP83640_MICR_IE); 1189 err = phy_write(phydev, MII_DP83640_MICR, micr); 1190 if (err < 0) 1191 return err; 1192 1193 misr = phy_read(phydev, MII_DP83640_MISR); 1194 if (misr < 0) 1195 return misr; 1196 misr &= 1197 ~(MII_DP83640_MISR_ANC_INT_EN | 1198 MII_DP83640_MISR_DUP_INT_EN | 1199 MII_DP83640_MISR_SPD_INT_EN | 1200 MII_DP83640_MISR_LINK_INT_EN); 1201 err = phy_write(phydev, MII_DP83640_MISR, misr); 1202 if (err) 1203 return err; 1204 1205 return dp83640_ack_interrupt(phydev); 1206 } 1207 } 1208 1209 static irqreturn_t dp83640_handle_interrupt(struct phy_device *phydev) 1210 { 1211 int irq_status; 1212 1213 irq_status = phy_read(phydev, MII_DP83640_MISR); 1214 if (irq_status < 0) { 1215 phy_error(phydev); 1216 return IRQ_NONE; 1217 } 1218 1219 if (!(irq_status & MII_DP83640_MISR_INT_MASK)) 1220 return IRQ_NONE; 1221 1222 phy_trigger_machine(phydev); 1223 1224 return IRQ_HANDLED; 1225 } 1226 1227 static int dp83640_hwtstamp(struct mii_timestamper *mii_ts, struct ifreq *ifr) 1228 { 1229 struct dp83640_private *dp83640 = 1230 container_of(mii_ts, struct dp83640_private, mii_ts); 1231 struct hwtstamp_config cfg; 1232 u16 txcfg0, rxcfg0; 1233 1234 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 1235 return -EFAULT; 1236 1237 if (cfg.flags) /* reserved for future extensions */ 1238 return -EINVAL; 1239 1240 if (cfg.tx_type < 0 || cfg.tx_type > HWTSTAMP_TX_ONESTEP_SYNC) 1241 return -ERANGE; 1242 1243 dp83640->hwts_tx_en = cfg.tx_type; 1244 1245 switch (cfg.rx_filter) { 1246 case HWTSTAMP_FILTER_NONE: 1247 dp83640->hwts_rx_en = 0; 1248 dp83640->layer = 0; 1249 dp83640->version = 0; 1250 break; 1251 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 1252 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 1253 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 1254 dp83640->hwts_rx_en = 1; 1255 dp83640->layer = PTP_CLASS_L4; 1256 dp83640->version = PTP_CLASS_V1; 1257 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 1258 break; 1259 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1260 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1261 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1262 dp83640->hwts_rx_en = 1; 1263 dp83640->layer = PTP_CLASS_L4; 1264 dp83640->version = PTP_CLASS_V2; 1265 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; 1266 break; 1267 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1268 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1269 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1270 dp83640->hwts_rx_en = 1; 1271 dp83640->layer = PTP_CLASS_L2; 1272 dp83640->version = PTP_CLASS_V2; 1273 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; 1274 break; 1275 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1276 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1277 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1278 dp83640->hwts_rx_en = 1; 1279 dp83640->layer = PTP_CLASS_L4 | PTP_CLASS_L2; 1280 dp83640->version = PTP_CLASS_V2; 1281 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 1282 break; 1283 default: 1284 return -ERANGE; 1285 } 1286 1287 txcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT; 1288 rxcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT; 1289 1290 if (dp83640->layer & PTP_CLASS_L2) { 1291 txcfg0 |= TX_L2_EN; 1292 rxcfg0 |= RX_L2_EN; 1293 } 1294 if (dp83640->layer & PTP_CLASS_L4) { 1295 txcfg0 |= TX_IPV6_EN | TX_IPV4_EN; 1296 rxcfg0 |= RX_IPV6_EN | RX_IPV4_EN; 1297 } 1298 1299 if (dp83640->hwts_tx_en) 1300 txcfg0 |= TX_TS_EN; 1301 1302 if (dp83640->hwts_tx_en == HWTSTAMP_TX_ONESTEP_SYNC) 1303 txcfg0 |= SYNC_1STEP | CHK_1STEP; 1304 1305 if (dp83640->hwts_rx_en) 1306 rxcfg0 |= RX_TS_EN; 1307 1308 mutex_lock(&dp83640->clock->extreg_lock); 1309 1310 ext_write(0, dp83640->phydev, PAGE5, PTP_TXCFG0, txcfg0); 1311 ext_write(0, dp83640->phydev, PAGE5, PTP_RXCFG0, rxcfg0); 1312 1313 mutex_unlock(&dp83640->clock->extreg_lock); 1314 1315 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1316 } 1317 1318 static void rx_timestamp_work(struct work_struct *work) 1319 { 1320 struct dp83640_private *dp83640 = 1321 container_of(work, struct dp83640_private, ts_work.work); 1322 struct sk_buff *skb; 1323 1324 /* Deliver expired packets. */ 1325 while ((skb = skb_dequeue(&dp83640->rx_queue))) { 1326 struct dp83640_skb_info *skb_info; 1327 1328 skb_info = (struct dp83640_skb_info *)skb->cb; 1329 if (!time_after(jiffies, skb_info->tmo)) { 1330 skb_queue_head(&dp83640->rx_queue, skb); 1331 break; 1332 } 1333 1334 netif_rx_ni(skb); 1335 } 1336 1337 if (!skb_queue_empty(&dp83640->rx_queue)) 1338 schedule_delayed_work(&dp83640->ts_work, SKB_TIMESTAMP_TIMEOUT); 1339 } 1340 1341 static bool dp83640_rxtstamp(struct mii_timestamper *mii_ts, 1342 struct sk_buff *skb, int type) 1343 { 1344 struct dp83640_private *dp83640 = 1345 container_of(mii_ts, struct dp83640_private, mii_ts); 1346 struct dp83640_skb_info *skb_info = (struct dp83640_skb_info *)skb->cb; 1347 struct list_head *this, *next; 1348 struct rxts *rxts; 1349 struct skb_shared_hwtstamps *shhwtstamps = NULL; 1350 unsigned long flags; 1351 1352 if (is_status_frame(skb, type)) { 1353 decode_status_frame(dp83640, skb); 1354 kfree_skb(skb); 1355 return true; 1356 } 1357 1358 if (!dp83640->hwts_rx_en) 1359 return false; 1360 1361 if ((type & dp83640->version) == 0 || (type & dp83640->layer) == 0) 1362 return false; 1363 1364 spin_lock_irqsave(&dp83640->rx_lock, flags); 1365 prune_rx_ts(dp83640); 1366 list_for_each_safe(this, next, &dp83640->rxts) { 1367 rxts = list_entry(this, struct rxts, list); 1368 if (match(skb, type, rxts)) { 1369 shhwtstamps = skb_hwtstamps(skb); 1370 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 1371 shhwtstamps->hwtstamp = ns_to_ktime(rxts->ns); 1372 list_del_init(&rxts->list); 1373 list_add(&rxts->list, &dp83640->rxpool); 1374 break; 1375 } 1376 } 1377 spin_unlock_irqrestore(&dp83640->rx_lock, flags); 1378 1379 if (!shhwtstamps) { 1380 skb_info->ptp_type = type; 1381 skb_info->tmo = jiffies + SKB_TIMESTAMP_TIMEOUT; 1382 skb_queue_tail(&dp83640->rx_queue, skb); 1383 schedule_delayed_work(&dp83640->ts_work, SKB_TIMESTAMP_TIMEOUT); 1384 } else { 1385 netif_rx_ni(skb); 1386 } 1387 1388 return true; 1389 } 1390 1391 static void dp83640_txtstamp(struct mii_timestamper *mii_ts, 1392 struct sk_buff *skb, int type) 1393 { 1394 struct dp83640_skb_info *skb_info = (struct dp83640_skb_info *)skb->cb; 1395 struct dp83640_private *dp83640 = 1396 container_of(mii_ts, struct dp83640_private, mii_ts); 1397 1398 switch (dp83640->hwts_tx_en) { 1399 1400 case HWTSTAMP_TX_ONESTEP_SYNC: 1401 if (is_sync(skb, type)) { 1402 kfree_skb(skb); 1403 return; 1404 } 1405 fallthrough; 1406 case HWTSTAMP_TX_ON: 1407 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1408 skb_info->tmo = jiffies + SKB_TIMESTAMP_TIMEOUT; 1409 skb_queue_tail(&dp83640->tx_queue, skb); 1410 break; 1411 1412 case HWTSTAMP_TX_OFF: 1413 default: 1414 kfree_skb(skb); 1415 break; 1416 } 1417 } 1418 1419 static int dp83640_ts_info(struct mii_timestamper *mii_ts, 1420 struct ethtool_ts_info *info) 1421 { 1422 struct dp83640_private *dp83640 = 1423 container_of(mii_ts, struct dp83640_private, mii_ts); 1424 1425 info->so_timestamping = 1426 SOF_TIMESTAMPING_TX_HARDWARE | 1427 SOF_TIMESTAMPING_RX_HARDWARE | 1428 SOF_TIMESTAMPING_RAW_HARDWARE; 1429 info->phc_index = ptp_clock_index(dp83640->clock->ptp_clock); 1430 info->tx_types = 1431 (1 << HWTSTAMP_TX_OFF) | 1432 (1 << HWTSTAMP_TX_ON) | 1433 (1 << HWTSTAMP_TX_ONESTEP_SYNC); 1434 info->rx_filters = 1435 (1 << HWTSTAMP_FILTER_NONE) | 1436 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) | 1437 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) | 1438 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 1439 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT); 1440 return 0; 1441 } 1442 1443 static int dp83640_probe(struct phy_device *phydev) 1444 { 1445 struct dp83640_clock *clock; 1446 struct dp83640_private *dp83640; 1447 int err = -ENOMEM, i; 1448 1449 if (phydev->mdio.addr == BROADCAST_ADDR) 1450 return 0; 1451 1452 clock = dp83640_clock_get_bus(phydev->mdio.bus); 1453 if (!clock) 1454 goto no_clock; 1455 1456 dp83640 = kzalloc(sizeof(struct dp83640_private), GFP_KERNEL); 1457 if (!dp83640) 1458 goto no_memory; 1459 1460 dp83640->phydev = phydev; 1461 dp83640->mii_ts.rxtstamp = dp83640_rxtstamp; 1462 dp83640->mii_ts.txtstamp = dp83640_txtstamp; 1463 dp83640->mii_ts.hwtstamp = dp83640_hwtstamp; 1464 dp83640->mii_ts.ts_info = dp83640_ts_info; 1465 1466 INIT_DELAYED_WORK(&dp83640->ts_work, rx_timestamp_work); 1467 INIT_LIST_HEAD(&dp83640->rxts); 1468 INIT_LIST_HEAD(&dp83640->rxpool); 1469 for (i = 0; i < MAX_RXTS; i++) 1470 list_add(&dp83640->rx_pool_data[i].list, &dp83640->rxpool); 1471 1472 phydev->mii_ts = &dp83640->mii_ts; 1473 phydev->priv = dp83640; 1474 1475 spin_lock_init(&dp83640->rx_lock); 1476 skb_queue_head_init(&dp83640->rx_queue); 1477 skb_queue_head_init(&dp83640->tx_queue); 1478 1479 dp83640->clock = clock; 1480 1481 if (choose_this_phy(clock, phydev)) { 1482 clock->chosen = dp83640; 1483 clock->ptp_clock = ptp_clock_register(&clock->caps, 1484 &phydev->mdio.dev); 1485 if (IS_ERR(clock->ptp_clock)) { 1486 err = PTR_ERR(clock->ptp_clock); 1487 goto no_register; 1488 } 1489 } else 1490 list_add_tail(&dp83640->list, &clock->phylist); 1491 1492 dp83640_clock_put(clock); 1493 return 0; 1494 1495 no_register: 1496 clock->chosen = NULL; 1497 kfree(dp83640); 1498 no_memory: 1499 dp83640_clock_put(clock); 1500 no_clock: 1501 return err; 1502 } 1503 1504 static void dp83640_remove(struct phy_device *phydev) 1505 { 1506 struct dp83640_clock *clock; 1507 struct list_head *this, *next; 1508 struct dp83640_private *tmp, *dp83640 = phydev->priv; 1509 1510 if (phydev->mdio.addr == BROADCAST_ADDR) 1511 return; 1512 1513 phydev->mii_ts = NULL; 1514 1515 enable_status_frames(phydev, false); 1516 cancel_delayed_work_sync(&dp83640->ts_work); 1517 1518 skb_queue_purge(&dp83640->rx_queue); 1519 skb_queue_purge(&dp83640->tx_queue); 1520 1521 clock = dp83640_clock_get(dp83640->clock); 1522 1523 if (dp83640 == clock->chosen) { 1524 ptp_clock_unregister(clock->ptp_clock); 1525 clock->chosen = NULL; 1526 } else { 1527 list_for_each_safe(this, next, &clock->phylist) { 1528 tmp = list_entry(this, struct dp83640_private, list); 1529 if (tmp == dp83640) { 1530 list_del_init(&tmp->list); 1531 break; 1532 } 1533 } 1534 } 1535 1536 dp83640_clock_put(clock); 1537 kfree(dp83640); 1538 } 1539 1540 static struct phy_driver dp83640_driver = { 1541 .phy_id = DP83640_PHY_ID, 1542 .phy_id_mask = 0xfffffff0, 1543 .name = "NatSemi DP83640", 1544 /* PHY_BASIC_FEATURES */ 1545 .probe = dp83640_probe, 1546 .remove = dp83640_remove, 1547 .soft_reset = dp83640_soft_reset, 1548 .config_init = dp83640_config_init, 1549 .config_intr = dp83640_config_intr, 1550 .handle_interrupt = dp83640_handle_interrupt, 1551 }; 1552 1553 static int __init dp83640_init(void) 1554 { 1555 return phy_driver_register(&dp83640_driver, THIS_MODULE); 1556 } 1557 1558 static void __exit dp83640_exit(void) 1559 { 1560 dp83640_free_clocks(); 1561 phy_driver_unregister(&dp83640_driver); 1562 } 1563 1564 MODULE_DESCRIPTION("National Semiconductor DP83640 PHY driver"); 1565 MODULE_AUTHOR("Richard Cochran <richardcochran@gmail.com>"); 1566 MODULE_LICENSE("GPL"); 1567 1568 module_init(dp83640_init); 1569 module_exit(dp83640_exit); 1570 1571 static struct mdio_device_id __maybe_unused dp83640_tbl[] = { 1572 { DP83640_PHY_ID, 0xfffffff0 }, 1573 { } 1574 }; 1575 1576 MODULE_DEVICE_TABLE(mdio, dp83640_tbl); 1577