1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Driver for the National Semiconductor DP83640 PHYTER 4 * 5 * Copyright (C) 2010 OMICRON electronics GmbH 6 */ 7 8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 9 10 #include <linux/crc32.h> 11 #include <linux/ethtool.h> 12 #include <linux/kernel.h> 13 #include <linux/list.h> 14 #include <linux/mii.h> 15 #include <linux/module.h> 16 #include <linux/net_tstamp.h> 17 #include <linux/netdevice.h> 18 #include <linux/if_vlan.h> 19 #include <linux/phy.h> 20 #include <linux/ptp_classify.h> 21 #include <linux/ptp_clock_kernel.h> 22 23 #include "dp83640_reg.h" 24 25 #define DP83640_PHY_ID 0x20005ce1 26 #define PAGESEL 0x13 27 #define MAX_RXTS 64 28 #define N_EXT_TS 6 29 #define N_PER_OUT 7 30 #define PSF_PTPVER 2 31 #define PSF_EVNT 0x4000 32 #define PSF_RX 0x2000 33 #define PSF_TX 0x1000 34 #define EXT_EVENT 1 35 #define CAL_EVENT 7 36 #define CAL_TRIGGER 1 37 #define DP83640_N_PINS 12 38 39 #define MII_DP83640_MICR 0x11 40 #define MII_DP83640_MISR 0x12 41 42 #define MII_DP83640_MICR_OE 0x1 43 #define MII_DP83640_MICR_IE 0x2 44 45 #define MII_DP83640_MISR_RHF_INT_EN 0x01 46 #define MII_DP83640_MISR_FHF_INT_EN 0x02 47 #define MII_DP83640_MISR_ANC_INT_EN 0x04 48 #define MII_DP83640_MISR_DUP_INT_EN 0x08 49 #define MII_DP83640_MISR_SPD_INT_EN 0x10 50 #define MII_DP83640_MISR_LINK_INT_EN 0x20 51 #define MII_DP83640_MISR_ED_INT_EN 0x40 52 #define MII_DP83640_MISR_LQ_INT_EN 0x80 53 #define MII_DP83640_MISR_ANC_INT 0x400 54 #define MII_DP83640_MISR_DUP_INT 0x800 55 #define MII_DP83640_MISR_SPD_INT 0x1000 56 #define MII_DP83640_MISR_LINK_INT 0x2000 57 #define MII_DP83640_MISR_INT_MASK (MII_DP83640_MISR_ANC_INT |\ 58 MII_DP83640_MISR_DUP_INT |\ 59 MII_DP83640_MISR_SPD_INT |\ 60 MII_DP83640_MISR_LINK_INT) 61 62 /* phyter seems to miss the mark by 16 ns */ 63 #define ADJTIME_FIX 16 64 65 #define SKB_TIMESTAMP_TIMEOUT 2 /* jiffies */ 66 67 #if defined(__BIG_ENDIAN) 68 #define ENDIAN_FLAG 0 69 #elif defined(__LITTLE_ENDIAN) 70 #define ENDIAN_FLAG PSF_ENDIAN 71 #endif 72 73 struct dp83640_skb_info { 74 int ptp_type; 75 unsigned long tmo; 76 }; 77 78 struct phy_rxts { 79 u16 ns_lo; /* ns[15:0] */ 80 u16 ns_hi; /* overflow[1:0], ns[29:16] */ 81 u16 sec_lo; /* sec[15:0] */ 82 u16 sec_hi; /* sec[31:16] */ 83 u16 seqid; /* sequenceId[15:0] */ 84 u16 msgtype; /* messageType[3:0], hash[11:0] */ 85 }; 86 87 struct phy_txts { 88 u16 ns_lo; /* ns[15:0] */ 89 u16 ns_hi; /* overflow[1:0], ns[29:16] */ 90 u16 sec_lo; /* sec[15:0] */ 91 u16 sec_hi; /* sec[31:16] */ 92 }; 93 94 struct rxts { 95 struct list_head list; 96 unsigned long tmo; 97 u64 ns; 98 u16 seqid; 99 u8 msgtype; 100 u16 hash; 101 }; 102 103 struct dp83640_clock; 104 105 struct dp83640_private { 106 struct list_head list; 107 struct dp83640_clock *clock; 108 struct phy_device *phydev; 109 struct mii_timestamper mii_ts; 110 struct delayed_work ts_work; 111 int hwts_tx_en; 112 int hwts_rx_en; 113 int layer; 114 int version; 115 /* remember state of cfg0 during calibration */ 116 int cfg0; 117 /* remember the last event time stamp */ 118 struct phy_txts edata; 119 /* list of rx timestamps */ 120 struct list_head rxts; 121 struct list_head rxpool; 122 struct rxts rx_pool_data[MAX_RXTS]; 123 /* protects above three fields from concurrent access */ 124 spinlock_t rx_lock; 125 /* queues of incoming and outgoing packets */ 126 struct sk_buff_head rx_queue; 127 struct sk_buff_head tx_queue; 128 }; 129 130 struct dp83640_clock { 131 /* keeps the instance in the 'phyter_clocks' list */ 132 struct list_head list; 133 /* we create one clock instance per MII bus */ 134 struct mii_bus *bus; 135 /* protects extended registers from concurrent access */ 136 struct mutex extreg_lock; 137 /* remembers which page was last selected */ 138 int page; 139 /* our advertised capabilities */ 140 struct ptp_clock_info caps; 141 /* protects the three fields below from concurrent access */ 142 struct mutex clock_lock; 143 /* the one phyter from which we shall read */ 144 struct dp83640_private *chosen; 145 /* list of the other attached phyters, not chosen */ 146 struct list_head phylist; 147 /* reference to our PTP hardware clock */ 148 struct ptp_clock *ptp_clock; 149 }; 150 151 /* globals */ 152 153 enum { 154 CALIBRATE_GPIO, 155 PEROUT_GPIO, 156 EXTTS0_GPIO, 157 EXTTS1_GPIO, 158 EXTTS2_GPIO, 159 EXTTS3_GPIO, 160 EXTTS4_GPIO, 161 EXTTS5_GPIO, 162 GPIO_TABLE_SIZE 163 }; 164 165 static int chosen_phy = -1; 166 static ushort gpio_tab[GPIO_TABLE_SIZE] = { 167 1, 2, 3, 4, 8, 9, 10, 11 168 }; 169 170 module_param(chosen_phy, int, 0444); 171 module_param_array(gpio_tab, ushort, NULL, 0444); 172 173 MODULE_PARM_DESC(chosen_phy, 174 "The address of the PHY to use for the ancillary clock features"); 175 MODULE_PARM_DESC(gpio_tab, 176 "Which GPIO line to use for which purpose: cal,perout,extts1,...,extts6"); 177 178 static void dp83640_gpio_defaults(struct ptp_pin_desc *pd) 179 { 180 int i, index; 181 182 for (i = 0; i < DP83640_N_PINS; i++) { 183 snprintf(pd[i].name, sizeof(pd[i].name), "GPIO%d", 1 + i); 184 pd[i].index = i; 185 } 186 187 for (i = 0; i < GPIO_TABLE_SIZE; i++) { 188 if (gpio_tab[i] < 1 || gpio_tab[i] > DP83640_N_PINS) { 189 pr_err("gpio_tab[%d]=%hu out of range", i, gpio_tab[i]); 190 return; 191 } 192 } 193 194 index = gpio_tab[CALIBRATE_GPIO] - 1; 195 pd[index].func = PTP_PF_PHYSYNC; 196 pd[index].chan = 0; 197 198 index = gpio_tab[PEROUT_GPIO] - 1; 199 pd[index].func = PTP_PF_PEROUT; 200 pd[index].chan = 0; 201 202 for (i = EXTTS0_GPIO; i < GPIO_TABLE_SIZE; i++) { 203 index = gpio_tab[i] - 1; 204 pd[index].func = PTP_PF_EXTTS; 205 pd[index].chan = i - EXTTS0_GPIO; 206 } 207 } 208 209 /* a list of clocks and a mutex to protect it */ 210 static LIST_HEAD(phyter_clocks); 211 static DEFINE_MUTEX(phyter_clocks_lock); 212 213 static void rx_timestamp_work(struct work_struct *work); 214 215 /* extended register access functions */ 216 217 #define BROADCAST_ADDR 31 218 219 static inline int broadcast_write(struct phy_device *phydev, u32 regnum, 220 u16 val) 221 { 222 return mdiobus_write(phydev->mdio.bus, BROADCAST_ADDR, regnum, val); 223 } 224 225 /* Caller must hold extreg_lock. */ 226 static int ext_read(struct phy_device *phydev, int page, u32 regnum) 227 { 228 struct dp83640_private *dp83640 = phydev->priv; 229 int val; 230 231 if (dp83640->clock->page != page) { 232 broadcast_write(phydev, PAGESEL, page); 233 dp83640->clock->page = page; 234 } 235 val = phy_read(phydev, regnum); 236 237 return val; 238 } 239 240 /* Caller must hold extreg_lock. */ 241 static void ext_write(int broadcast, struct phy_device *phydev, 242 int page, u32 regnum, u16 val) 243 { 244 struct dp83640_private *dp83640 = phydev->priv; 245 246 if (dp83640->clock->page != page) { 247 broadcast_write(phydev, PAGESEL, page); 248 dp83640->clock->page = page; 249 } 250 if (broadcast) 251 broadcast_write(phydev, regnum, val); 252 else 253 phy_write(phydev, regnum, val); 254 } 255 256 /* Caller must hold extreg_lock. */ 257 static int tdr_write(int bc, struct phy_device *dev, 258 const struct timespec64 *ts, u16 cmd) 259 { 260 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec & 0xffff);/* ns[15:0] */ 261 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec >> 16); /* ns[31:16] */ 262 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec & 0xffff); /* sec[15:0] */ 263 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec >> 16); /* sec[31:16]*/ 264 265 ext_write(bc, dev, PAGE4, PTP_CTL, cmd); 266 267 return 0; 268 } 269 270 /* convert phy timestamps into driver timestamps */ 271 272 static void phy2rxts(struct phy_rxts *p, struct rxts *rxts) 273 { 274 u32 sec; 275 276 sec = p->sec_lo; 277 sec |= p->sec_hi << 16; 278 279 rxts->ns = p->ns_lo; 280 rxts->ns |= (p->ns_hi & 0x3fff) << 16; 281 rxts->ns += ((u64)sec) * 1000000000ULL; 282 rxts->seqid = p->seqid; 283 rxts->msgtype = (p->msgtype >> 12) & 0xf; 284 rxts->hash = p->msgtype & 0x0fff; 285 rxts->tmo = jiffies + SKB_TIMESTAMP_TIMEOUT; 286 } 287 288 static u64 phy2txts(struct phy_txts *p) 289 { 290 u64 ns; 291 u32 sec; 292 293 sec = p->sec_lo; 294 sec |= p->sec_hi << 16; 295 296 ns = p->ns_lo; 297 ns |= (p->ns_hi & 0x3fff) << 16; 298 ns += ((u64)sec) * 1000000000ULL; 299 300 return ns; 301 } 302 303 static int periodic_output(struct dp83640_clock *clock, 304 struct ptp_clock_request *clkreq, bool on, 305 int trigger) 306 { 307 struct dp83640_private *dp83640 = clock->chosen; 308 struct phy_device *phydev = dp83640->phydev; 309 u32 sec, nsec, pwidth; 310 u16 gpio, ptp_trig, val; 311 312 if (on) { 313 gpio = 1 + ptp_find_pin(clock->ptp_clock, PTP_PF_PEROUT, 314 trigger); 315 if (gpio < 1) 316 return -EINVAL; 317 } else { 318 gpio = 0; 319 } 320 321 ptp_trig = TRIG_WR | 322 (trigger & TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT | 323 (gpio & TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT | 324 TRIG_PER | 325 TRIG_PULSE; 326 327 val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT; 328 329 if (!on) { 330 val |= TRIG_DIS; 331 mutex_lock(&clock->extreg_lock); 332 ext_write(0, phydev, PAGE5, PTP_TRIG, ptp_trig); 333 ext_write(0, phydev, PAGE4, PTP_CTL, val); 334 mutex_unlock(&clock->extreg_lock); 335 return 0; 336 } 337 338 sec = clkreq->perout.start.sec; 339 nsec = clkreq->perout.start.nsec; 340 pwidth = clkreq->perout.period.sec * 1000000000UL; 341 pwidth += clkreq->perout.period.nsec; 342 pwidth /= 2; 343 344 mutex_lock(&clock->extreg_lock); 345 346 ext_write(0, phydev, PAGE5, PTP_TRIG, ptp_trig); 347 348 /*load trigger*/ 349 val |= TRIG_LOAD; 350 ext_write(0, phydev, PAGE4, PTP_CTL, val); 351 ext_write(0, phydev, PAGE4, PTP_TDR, nsec & 0xffff); /* ns[15:0] */ 352 ext_write(0, phydev, PAGE4, PTP_TDR, nsec >> 16); /* ns[31:16] */ 353 ext_write(0, phydev, PAGE4, PTP_TDR, sec & 0xffff); /* sec[15:0] */ 354 ext_write(0, phydev, PAGE4, PTP_TDR, sec >> 16); /* sec[31:16] */ 355 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth & 0xffff); /* ns[15:0] */ 356 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth >> 16); /* ns[31:16] */ 357 /* Triggers 0 and 1 has programmable pulsewidth2 */ 358 if (trigger < 2) { 359 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth & 0xffff); 360 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth >> 16); 361 } 362 363 /*enable trigger*/ 364 val &= ~TRIG_LOAD; 365 val |= TRIG_EN; 366 ext_write(0, phydev, PAGE4, PTP_CTL, val); 367 368 mutex_unlock(&clock->extreg_lock); 369 return 0; 370 } 371 372 /* ptp clock methods */ 373 374 static int ptp_dp83640_adjfine(struct ptp_clock_info *ptp, long scaled_ppm) 375 { 376 struct dp83640_clock *clock = 377 container_of(ptp, struct dp83640_clock, caps); 378 struct phy_device *phydev = clock->chosen->phydev; 379 u64 rate; 380 int neg_adj = 0; 381 u16 hi, lo; 382 383 if (scaled_ppm < 0) { 384 neg_adj = 1; 385 scaled_ppm = -scaled_ppm; 386 } 387 rate = scaled_ppm; 388 rate <<= 13; 389 rate = div_u64(rate, 15625); 390 391 hi = (rate >> 16) & PTP_RATE_HI_MASK; 392 if (neg_adj) 393 hi |= PTP_RATE_DIR; 394 395 lo = rate & 0xffff; 396 397 mutex_lock(&clock->extreg_lock); 398 399 ext_write(1, phydev, PAGE4, PTP_RATEH, hi); 400 ext_write(1, phydev, PAGE4, PTP_RATEL, lo); 401 402 mutex_unlock(&clock->extreg_lock); 403 404 return 0; 405 } 406 407 static int ptp_dp83640_adjtime(struct ptp_clock_info *ptp, s64 delta) 408 { 409 struct dp83640_clock *clock = 410 container_of(ptp, struct dp83640_clock, caps); 411 struct phy_device *phydev = clock->chosen->phydev; 412 struct timespec64 ts; 413 int err; 414 415 delta += ADJTIME_FIX; 416 417 ts = ns_to_timespec64(delta); 418 419 mutex_lock(&clock->extreg_lock); 420 421 err = tdr_write(1, phydev, &ts, PTP_STEP_CLK); 422 423 mutex_unlock(&clock->extreg_lock); 424 425 return err; 426 } 427 428 static int ptp_dp83640_gettime(struct ptp_clock_info *ptp, 429 struct timespec64 *ts) 430 { 431 struct dp83640_clock *clock = 432 container_of(ptp, struct dp83640_clock, caps); 433 struct phy_device *phydev = clock->chosen->phydev; 434 unsigned int val[4]; 435 436 mutex_lock(&clock->extreg_lock); 437 438 ext_write(0, phydev, PAGE4, PTP_CTL, PTP_RD_CLK); 439 440 val[0] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[15:0] */ 441 val[1] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[31:16] */ 442 val[2] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[15:0] */ 443 val[3] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[31:16] */ 444 445 mutex_unlock(&clock->extreg_lock); 446 447 ts->tv_nsec = val[0] | (val[1] << 16); 448 ts->tv_sec = val[2] | (val[3] << 16); 449 450 return 0; 451 } 452 453 static int ptp_dp83640_settime(struct ptp_clock_info *ptp, 454 const struct timespec64 *ts) 455 { 456 struct dp83640_clock *clock = 457 container_of(ptp, struct dp83640_clock, caps); 458 struct phy_device *phydev = clock->chosen->phydev; 459 int err; 460 461 mutex_lock(&clock->extreg_lock); 462 463 err = tdr_write(1, phydev, ts, PTP_LOAD_CLK); 464 465 mutex_unlock(&clock->extreg_lock); 466 467 return err; 468 } 469 470 static int ptp_dp83640_enable(struct ptp_clock_info *ptp, 471 struct ptp_clock_request *rq, int on) 472 { 473 struct dp83640_clock *clock = 474 container_of(ptp, struct dp83640_clock, caps); 475 struct phy_device *phydev = clock->chosen->phydev; 476 unsigned int index; 477 u16 evnt, event_num, gpio_num; 478 479 switch (rq->type) { 480 case PTP_CLK_REQ_EXTTS: 481 /* Reject requests with unsupported flags */ 482 if (rq->extts.flags & ~(PTP_ENABLE_FEATURE | 483 PTP_RISING_EDGE | 484 PTP_FALLING_EDGE | 485 PTP_STRICT_FLAGS)) 486 return -EOPNOTSUPP; 487 488 /* Reject requests to enable time stamping on both edges. */ 489 if ((rq->extts.flags & PTP_STRICT_FLAGS) && 490 (rq->extts.flags & PTP_ENABLE_FEATURE) && 491 (rq->extts.flags & PTP_EXTTS_EDGES) == PTP_EXTTS_EDGES) 492 return -EOPNOTSUPP; 493 494 index = rq->extts.index; 495 if (index >= N_EXT_TS) 496 return -EINVAL; 497 event_num = EXT_EVENT + index; 498 evnt = EVNT_WR | (event_num & EVNT_SEL_MASK) << EVNT_SEL_SHIFT; 499 if (on) { 500 gpio_num = 1 + ptp_find_pin(clock->ptp_clock, 501 PTP_PF_EXTTS, index); 502 if (gpio_num < 1) 503 return -EINVAL; 504 evnt |= (gpio_num & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT; 505 if (rq->extts.flags & PTP_FALLING_EDGE) 506 evnt |= EVNT_FALL; 507 else 508 evnt |= EVNT_RISE; 509 } 510 mutex_lock(&clock->extreg_lock); 511 ext_write(0, phydev, PAGE5, PTP_EVNT, evnt); 512 mutex_unlock(&clock->extreg_lock); 513 return 0; 514 515 case PTP_CLK_REQ_PEROUT: 516 /* Reject requests with unsupported flags */ 517 if (rq->perout.flags) 518 return -EOPNOTSUPP; 519 if (rq->perout.index >= N_PER_OUT) 520 return -EINVAL; 521 return periodic_output(clock, rq, on, rq->perout.index); 522 523 default: 524 break; 525 } 526 527 return -EOPNOTSUPP; 528 } 529 530 static int ptp_dp83640_verify(struct ptp_clock_info *ptp, unsigned int pin, 531 enum ptp_pin_function func, unsigned int chan) 532 { 533 struct dp83640_clock *clock = 534 container_of(ptp, struct dp83640_clock, caps); 535 536 if (clock->caps.pin_config[pin].func == PTP_PF_PHYSYNC && 537 !list_empty(&clock->phylist)) 538 return 1; 539 540 if (func == PTP_PF_PHYSYNC) 541 return 1; 542 543 return 0; 544 } 545 546 static u8 status_frame_dst[6] = { 0x01, 0x1B, 0x19, 0x00, 0x00, 0x00 }; 547 static u8 status_frame_src[6] = { 0x08, 0x00, 0x17, 0x0B, 0x6B, 0x0F }; 548 549 static void enable_status_frames(struct phy_device *phydev, bool on) 550 { 551 struct dp83640_private *dp83640 = phydev->priv; 552 struct dp83640_clock *clock = dp83640->clock; 553 u16 cfg0 = 0, ver; 554 555 if (on) 556 cfg0 = PSF_EVNT_EN | PSF_RXTS_EN | PSF_TXTS_EN | ENDIAN_FLAG; 557 558 ver = (PSF_PTPVER & VERSIONPTP_MASK) << VERSIONPTP_SHIFT; 559 560 mutex_lock(&clock->extreg_lock); 561 562 ext_write(0, phydev, PAGE5, PSF_CFG0, cfg0); 563 ext_write(0, phydev, PAGE6, PSF_CFG1, ver); 564 565 mutex_unlock(&clock->extreg_lock); 566 567 if (!phydev->attached_dev) { 568 phydev_warn(phydev, 569 "expected to find an attached netdevice\n"); 570 return; 571 } 572 573 if (on) { 574 if (dev_mc_add(phydev->attached_dev, status_frame_dst)) 575 phydev_warn(phydev, "failed to add mc address\n"); 576 } else { 577 if (dev_mc_del(phydev->attached_dev, status_frame_dst)) 578 phydev_warn(phydev, "failed to delete mc address\n"); 579 } 580 } 581 582 static bool is_status_frame(struct sk_buff *skb, int type) 583 { 584 struct ethhdr *h = eth_hdr(skb); 585 586 if (PTP_CLASS_V2_L2 == type && 587 !memcmp(h->h_source, status_frame_src, sizeof(status_frame_src))) 588 return true; 589 else 590 return false; 591 } 592 593 static int expired(struct rxts *rxts) 594 { 595 return time_after(jiffies, rxts->tmo); 596 } 597 598 /* Caller must hold rx_lock. */ 599 static void prune_rx_ts(struct dp83640_private *dp83640) 600 { 601 struct list_head *this, *next; 602 struct rxts *rxts; 603 604 list_for_each_safe(this, next, &dp83640->rxts) { 605 rxts = list_entry(this, struct rxts, list); 606 if (expired(rxts)) { 607 list_del_init(&rxts->list); 608 list_add(&rxts->list, &dp83640->rxpool); 609 } 610 } 611 } 612 613 /* synchronize the phyters so they act as one clock */ 614 615 static void enable_broadcast(struct phy_device *phydev, int init_page, int on) 616 { 617 int val; 618 619 phy_write(phydev, PAGESEL, 0); 620 val = phy_read(phydev, PHYCR2); 621 if (on) 622 val |= BC_WRITE; 623 else 624 val &= ~BC_WRITE; 625 phy_write(phydev, PHYCR2, val); 626 phy_write(phydev, PAGESEL, init_page); 627 } 628 629 static void recalibrate(struct dp83640_clock *clock) 630 { 631 s64 now, diff; 632 struct phy_txts event_ts; 633 struct timespec64 ts; 634 struct list_head *this; 635 struct dp83640_private *tmp; 636 struct phy_device *master = clock->chosen->phydev; 637 u16 cal_gpio, cfg0, evnt, ptp_trig, trigger, val; 638 639 trigger = CAL_TRIGGER; 640 cal_gpio = 1 + ptp_find_pin_unlocked(clock->ptp_clock, PTP_PF_PHYSYNC, 0); 641 if (cal_gpio < 1) { 642 pr_err("PHY calibration pin not available - PHY is not calibrated."); 643 return; 644 } 645 646 mutex_lock(&clock->extreg_lock); 647 648 /* 649 * enable broadcast, disable status frames, enable ptp clock 650 */ 651 list_for_each(this, &clock->phylist) { 652 tmp = list_entry(this, struct dp83640_private, list); 653 enable_broadcast(tmp->phydev, clock->page, 1); 654 tmp->cfg0 = ext_read(tmp->phydev, PAGE5, PSF_CFG0); 655 ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, 0); 656 ext_write(0, tmp->phydev, PAGE4, PTP_CTL, PTP_ENABLE); 657 } 658 enable_broadcast(master, clock->page, 1); 659 cfg0 = ext_read(master, PAGE5, PSF_CFG0); 660 ext_write(0, master, PAGE5, PSF_CFG0, 0); 661 ext_write(0, master, PAGE4, PTP_CTL, PTP_ENABLE); 662 663 /* 664 * enable an event timestamp 665 */ 666 evnt = EVNT_WR | EVNT_RISE | EVNT_SINGLE; 667 evnt |= (CAL_EVENT & EVNT_SEL_MASK) << EVNT_SEL_SHIFT; 668 evnt |= (cal_gpio & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT; 669 670 list_for_each(this, &clock->phylist) { 671 tmp = list_entry(this, struct dp83640_private, list); 672 ext_write(0, tmp->phydev, PAGE5, PTP_EVNT, evnt); 673 } 674 ext_write(0, master, PAGE5, PTP_EVNT, evnt); 675 676 /* 677 * configure a trigger 678 */ 679 ptp_trig = TRIG_WR | TRIG_IF_LATE | TRIG_PULSE; 680 ptp_trig |= (trigger & TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT; 681 ptp_trig |= (cal_gpio & TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT; 682 ext_write(0, master, PAGE5, PTP_TRIG, ptp_trig); 683 684 /* load trigger */ 685 val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT; 686 val |= TRIG_LOAD; 687 ext_write(0, master, PAGE4, PTP_CTL, val); 688 689 /* enable trigger */ 690 val &= ~TRIG_LOAD; 691 val |= TRIG_EN; 692 ext_write(0, master, PAGE4, PTP_CTL, val); 693 694 /* disable trigger */ 695 val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT; 696 val |= TRIG_DIS; 697 ext_write(0, master, PAGE4, PTP_CTL, val); 698 699 /* 700 * read out and correct offsets 701 */ 702 val = ext_read(master, PAGE4, PTP_STS); 703 phydev_info(master, "master PTP_STS 0x%04hx\n", val); 704 val = ext_read(master, PAGE4, PTP_ESTS); 705 phydev_info(master, "master PTP_ESTS 0x%04hx\n", val); 706 event_ts.ns_lo = ext_read(master, PAGE4, PTP_EDATA); 707 event_ts.ns_hi = ext_read(master, PAGE4, PTP_EDATA); 708 event_ts.sec_lo = ext_read(master, PAGE4, PTP_EDATA); 709 event_ts.sec_hi = ext_read(master, PAGE4, PTP_EDATA); 710 now = phy2txts(&event_ts); 711 712 list_for_each(this, &clock->phylist) { 713 tmp = list_entry(this, struct dp83640_private, list); 714 val = ext_read(tmp->phydev, PAGE4, PTP_STS); 715 phydev_info(tmp->phydev, "slave PTP_STS 0x%04hx\n", val); 716 val = ext_read(tmp->phydev, PAGE4, PTP_ESTS); 717 phydev_info(tmp->phydev, "slave PTP_ESTS 0x%04hx\n", val); 718 event_ts.ns_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA); 719 event_ts.ns_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA); 720 event_ts.sec_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA); 721 event_ts.sec_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA); 722 diff = now - (s64) phy2txts(&event_ts); 723 phydev_info(tmp->phydev, "slave offset %lld nanoseconds\n", 724 diff); 725 diff += ADJTIME_FIX; 726 ts = ns_to_timespec64(diff); 727 tdr_write(0, tmp->phydev, &ts, PTP_STEP_CLK); 728 } 729 730 /* 731 * restore status frames 732 */ 733 list_for_each(this, &clock->phylist) { 734 tmp = list_entry(this, struct dp83640_private, list); 735 ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, tmp->cfg0); 736 } 737 ext_write(0, master, PAGE5, PSF_CFG0, cfg0); 738 739 mutex_unlock(&clock->extreg_lock); 740 } 741 742 /* time stamping methods */ 743 744 static inline u16 exts_chan_to_edata(int ch) 745 { 746 return 1 << ((ch + EXT_EVENT) * 2); 747 } 748 749 static int decode_evnt(struct dp83640_private *dp83640, 750 void *data, int len, u16 ests) 751 { 752 struct phy_txts *phy_txts; 753 struct ptp_clock_event event; 754 int i, parsed; 755 int words = (ests >> EVNT_TS_LEN_SHIFT) & EVNT_TS_LEN_MASK; 756 u16 ext_status = 0; 757 758 /* calculate length of the event timestamp status message */ 759 if (ests & MULT_EVNT) 760 parsed = (words + 2) * sizeof(u16); 761 else 762 parsed = (words + 1) * sizeof(u16); 763 764 /* check if enough data is available */ 765 if (len < parsed) 766 return len; 767 768 if (ests & MULT_EVNT) { 769 ext_status = *(u16 *) data; 770 data += sizeof(ext_status); 771 } 772 773 phy_txts = data; 774 775 switch (words) { 776 case 3: 777 dp83640->edata.sec_hi = phy_txts->sec_hi; 778 fallthrough; 779 case 2: 780 dp83640->edata.sec_lo = phy_txts->sec_lo; 781 fallthrough; 782 case 1: 783 dp83640->edata.ns_hi = phy_txts->ns_hi; 784 fallthrough; 785 case 0: 786 dp83640->edata.ns_lo = phy_txts->ns_lo; 787 } 788 789 if (!ext_status) { 790 i = ((ests >> EVNT_NUM_SHIFT) & EVNT_NUM_MASK) - EXT_EVENT; 791 ext_status = exts_chan_to_edata(i); 792 } 793 794 event.type = PTP_CLOCK_EXTTS; 795 event.timestamp = phy2txts(&dp83640->edata); 796 797 /* Compensate for input path and synchronization delays */ 798 event.timestamp -= 35; 799 800 for (i = 0; i < N_EXT_TS; i++) { 801 if (ext_status & exts_chan_to_edata(i)) { 802 event.index = i; 803 ptp_clock_event(dp83640->clock->ptp_clock, &event); 804 } 805 } 806 807 return parsed; 808 } 809 810 #define DP83640_PACKET_HASH_LEN 10 811 812 static int match(struct sk_buff *skb, unsigned int type, struct rxts *rxts) 813 { 814 struct ptp_header *hdr; 815 u8 msgtype; 816 u16 seqid; 817 u16 hash; 818 819 /* check sequenceID, messageType, 12 bit hash of offset 20-29 */ 820 821 hdr = ptp_parse_header(skb, type); 822 if (!hdr) 823 return 0; 824 825 msgtype = ptp_get_msgtype(hdr, type); 826 827 if (rxts->msgtype != (msgtype & 0xf)) 828 return 0; 829 830 seqid = be16_to_cpu(hdr->sequence_id); 831 if (rxts->seqid != seqid) 832 return 0; 833 834 hash = ether_crc(DP83640_PACKET_HASH_LEN, 835 (unsigned char *)&hdr->source_port_identity) >> 20; 836 if (rxts->hash != hash) 837 return 0; 838 839 return 1; 840 } 841 842 static void decode_rxts(struct dp83640_private *dp83640, 843 struct phy_rxts *phy_rxts) 844 { 845 struct rxts *rxts; 846 struct skb_shared_hwtstamps *shhwtstamps = NULL; 847 struct sk_buff *skb; 848 unsigned long flags; 849 u8 overflow; 850 851 overflow = (phy_rxts->ns_hi >> 14) & 0x3; 852 if (overflow) 853 pr_debug("rx timestamp queue overflow, count %d\n", overflow); 854 855 spin_lock_irqsave(&dp83640->rx_lock, flags); 856 857 prune_rx_ts(dp83640); 858 859 if (list_empty(&dp83640->rxpool)) { 860 pr_debug("rx timestamp pool is empty\n"); 861 goto out; 862 } 863 rxts = list_first_entry(&dp83640->rxpool, struct rxts, list); 864 list_del_init(&rxts->list); 865 phy2rxts(phy_rxts, rxts); 866 867 spin_lock(&dp83640->rx_queue.lock); 868 skb_queue_walk(&dp83640->rx_queue, skb) { 869 struct dp83640_skb_info *skb_info; 870 871 skb_info = (struct dp83640_skb_info *)skb->cb; 872 if (match(skb, skb_info->ptp_type, rxts)) { 873 __skb_unlink(skb, &dp83640->rx_queue); 874 shhwtstamps = skb_hwtstamps(skb); 875 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 876 shhwtstamps->hwtstamp = ns_to_ktime(rxts->ns); 877 list_add(&rxts->list, &dp83640->rxpool); 878 break; 879 } 880 } 881 spin_unlock(&dp83640->rx_queue.lock); 882 883 if (!shhwtstamps) 884 list_add_tail(&rxts->list, &dp83640->rxts); 885 out: 886 spin_unlock_irqrestore(&dp83640->rx_lock, flags); 887 888 if (shhwtstamps) 889 netif_rx_ni(skb); 890 } 891 892 static void decode_txts(struct dp83640_private *dp83640, 893 struct phy_txts *phy_txts) 894 { 895 struct skb_shared_hwtstamps shhwtstamps; 896 struct dp83640_skb_info *skb_info; 897 struct sk_buff *skb; 898 u8 overflow; 899 u64 ns; 900 901 /* We must already have the skb that triggered this. */ 902 again: 903 skb = skb_dequeue(&dp83640->tx_queue); 904 if (!skb) { 905 pr_debug("have timestamp but tx_queue empty\n"); 906 return; 907 } 908 909 overflow = (phy_txts->ns_hi >> 14) & 0x3; 910 if (overflow) { 911 pr_debug("tx timestamp queue overflow, count %d\n", overflow); 912 while (skb) { 913 kfree_skb(skb); 914 skb = skb_dequeue(&dp83640->tx_queue); 915 } 916 return; 917 } 918 skb_info = (struct dp83640_skb_info *)skb->cb; 919 if (time_after(jiffies, skb_info->tmo)) { 920 kfree_skb(skb); 921 goto again; 922 } 923 924 ns = phy2txts(phy_txts); 925 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 926 shhwtstamps.hwtstamp = ns_to_ktime(ns); 927 skb_complete_tx_timestamp(skb, &shhwtstamps); 928 } 929 930 static void decode_status_frame(struct dp83640_private *dp83640, 931 struct sk_buff *skb) 932 { 933 struct phy_rxts *phy_rxts; 934 struct phy_txts *phy_txts; 935 u8 *ptr; 936 int len, size; 937 u16 ests, type; 938 939 ptr = skb->data + 2; 940 941 for (len = skb_headlen(skb) - 2; len > sizeof(type); len -= size) { 942 943 type = *(u16 *)ptr; 944 ests = type & 0x0fff; 945 type = type & 0xf000; 946 len -= sizeof(type); 947 ptr += sizeof(type); 948 949 if (PSF_RX == type && len >= sizeof(*phy_rxts)) { 950 951 phy_rxts = (struct phy_rxts *) ptr; 952 decode_rxts(dp83640, phy_rxts); 953 size = sizeof(*phy_rxts); 954 955 } else if (PSF_TX == type && len >= sizeof(*phy_txts)) { 956 957 phy_txts = (struct phy_txts *) ptr; 958 decode_txts(dp83640, phy_txts); 959 size = sizeof(*phy_txts); 960 961 } else if (PSF_EVNT == type) { 962 963 size = decode_evnt(dp83640, ptr, len, ests); 964 965 } else { 966 size = 0; 967 break; 968 } 969 ptr += size; 970 } 971 } 972 973 static int is_sync(struct sk_buff *skb, int type) 974 { 975 struct ptp_header *hdr; 976 977 hdr = ptp_parse_header(skb, type); 978 if (!hdr) 979 return 0; 980 981 return ptp_get_msgtype(hdr, type) == PTP_MSGTYPE_SYNC; 982 } 983 984 static void dp83640_free_clocks(void) 985 { 986 struct dp83640_clock *clock; 987 struct list_head *this, *next; 988 989 mutex_lock(&phyter_clocks_lock); 990 991 list_for_each_safe(this, next, &phyter_clocks) { 992 clock = list_entry(this, struct dp83640_clock, list); 993 if (!list_empty(&clock->phylist)) { 994 pr_warn("phy list non-empty while unloading\n"); 995 BUG(); 996 } 997 list_del(&clock->list); 998 mutex_destroy(&clock->extreg_lock); 999 mutex_destroy(&clock->clock_lock); 1000 put_device(&clock->bus->dev); 1001 kfree(clock->caps.pin_config); 1002 kfree(clock); 1003 } 1004 1005 mutex_unlock(&phyter_clocks_lock); 1006 } 1007 1008 static void dp83640_clock_init(struct dp83640_clock *clock, struct mii_bus *bus) 1009 { 1010 INIT_LIST_HEAD(&clock->list); 1011 clock->bus = bus; 1012 mutex_init(&clock->extreg_lock); 1013 mutex_init(&clock->clock_lock); 1014 INIT_LIST_HEAD(&clock->phylist); 1015 clock->caps.owner = THIS_MODULE; 1016 sprintf(clock->caps.name, "dp83640 timer"); 1017 clock->caps.max_adj = 1953124; 1018 clock->caps.n_alarm = 0; 1019 clock->caps.n_ext_ts = N_EXT_TS; 1020 clock->caps.n_per_out = N_PER_OUT; 1021 clock->caps.n_pins = DP83640_N_PINS; 1022 clock->caps.pps = 0; 1023 clock->caps.adjfine = ptp_dp83640_adjfine; 1024 clock->caps.adjtime = ptp_dp83640_adjtime; 1025 clock->caps.gettime64 = ptp_dp83640_gettime; 1026 clock->caps.settime64 = ptp_dp83640_settime; 1027 clock->caps.enable = ptp_dp83640_enable; 1028 clock->caps.verify = ptp_dp83640_verify; 1029 /* 1030 * Convert the module param defaults into a dynamic pin configuration. 1031 */ 1032 dp83640_gpio_defaults(clock->caps.pin_config); 1033 /* 1034 * Get a reference to this bus instance. 1035 */ 1036 get_device(&bus->dev); 1037 } 1038 1039 static int choose_this_phy(struct dp83640_clock *clock, 1040 struct phy_device *phydev) 1041 { 1042 if (chosen_phy == -1 && !clock->chosen) 1043 return 1; 1044 1045 if (chosen_phy == phydev->mdio.addr) 1046 return 1; 1047 1048 return 0; 1049 } 1050 1051 static struct dp83640_clock *dp83640_clock_get(struct dp83640_clock *clock) 1052 { 1053 if (clock) 1054 mutex_lock(&clock->clock_lock); 1055 return clock; 1056 } 1057 1058 /* 1059 * Look up and lock a clock by bus instance. 1060 * If there is no clock for this bus, then create it first. 1061 */ 1062 static struct dp83640_clock *dp83640_clock_get_bus(struct mii_bus *bus) 1063 { 1064 struct dp83640_clock *clock = NULL, *tmp; 1065 struct list_head *this; 1066 1067 mutex_lock(&phyter_clocks_lock); 1068 1069 list_for_each(this, &phyter_clocks) { 1070 tmp = list_entry(this, struct dp83640_clock, list); 1071 if (tmp->bus == bus) { 1072 clock = tmp; 1073 break; 1074 } 1075 } 1076 if (clock) 1077 goto out; 1078 1079 clock = kzalloc(sizeof(struct dp83640_clock), GFP_KERNEL); 1080 if (!clock) 1081 goto out; 1082 1083 clock->caps.pin_config = kcalloc(DP83640_N_PINS, 1084 sizeof(struct ptp_pin_desc), 1085 GFP_KERNEL); 1086 if (!clock->caps.pin_config) { 1087 kfree(clock); 1088 clock = NULL; 1089 goto out; 1090 } 1091 dp83640_clock_init(clock, bus); 1092 list_add_tail(&clock->list, &phyter_clocks); 1093 out: 1094 mutex_unlock(&phyter_clocks_lock); 1095 1096 return dp83640_clock_get(clock); 1097 } 1098 1099 static void dp83640_clock_put(struct dp83640_clock *clock) 1100 { 1101 mutex_unlock(&clock->clock_lock); 1102 } 1103 1104 static int dp83640_soft_reset(struct phy_device *phydev) 1105 { 1106 int ret; 1107 1108 ret = genphy_soft_reset(phydev); 1109 if (ret < 0) 1110 return ret; 1111 1112 /* From DP83640 datasheet: "Software driver code must wait 3 us 1113 * following a software reset before allowing further serial MII 1114 * operations with the DP83640." 1115 */ 1116 udelay(10); /* Taking udelay inaccuracy into account */ 1117 1118 return 0; 1119 } 1120 1121 static int dp83640_config_init(struct phy_device *phydev) 1122 { 1123 struct dp83640_private *dp83640 = phydev->priv; 1124 struct dp83640_clock *clock = dp83640->clock; 1125 1126 if (clock->chosen && !list_empty(&clock->phylist)) 1127 recalibrate(clock); 1128 else { 1129 mutex_lock(&clock->extreg_lock); 1130 enable_broadcast(phydev, clock->page, 1); 1131 mutex_unlock(&clock->extreg_lock); 1132 } 1133 1134 enable_status_frames(phydev, true); 1135 1136 mutex_lock(&clock->extreg_lock); 1137 ext_write(0, phydev, PAGE4, PTP_CTL, PTP_ENABLE); 1138 mutex_unlock(&clock->extreg_lock); 1139 1140 return 0; 1141 } 1142 1143 static int dp83640_ack_interrupt(struct phy_device *phydev) 1144 { 1145 int err = phy_read(phydev, MII_DP83640_MISR); 1146 1147 if (err < 0) 1148 return err; 1149 1150 return 0; 1151 } 1152 1153 static int dp83640_config_intr(struct phy_device *phydev) 1154 { 1155 int micr; 1156 int misr; 1157 int err; 1158 1159 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 1160 err = dp83640_ack_interrupt(phydev); 1161 if (err) 1162 return err; 1163 1164 misr = phy_read(phydev, MII_DP83640_MISR); 1165 if (misr < 0) 1166 return misr; 1167 misr |= 1168 (MII_DP83640_MISR_ANC_INT_EN | 1169 MII_DP83640_MISR_DUP_INT_EN | 1170 MII_DP83640_MISR_SPD_INT_EN | 1171 MII_DP83640_MISR_LINK_INT_EN); 1172 err = phy_write(phydev, MII_DP83640_MISR, misr); 1173 if (err < 0) 1174 return err; 1175 1176 micr = phy_read(phydev, MII_DP83640_MICR); 1177 if (micr < 0) 1178 return micr; 1179 micr |= 1180 (MII_DP83640_MICR_OE | 1181 MII_DP83640_MICR_IE); 1182 return phy_write(phydev, MII_DP83640_MICR, micr); 1183 } else { 1184 micr = phy_read(phydev, MII_DP83640_MICR); 1185 if (micr < 0) 1186 return micr; 1187 micr &= 1188 ~(MII_DP83640_MICR_OE | 1189 MII_DP83640_MICR_IE); 1190 err = phy_write(phydev, MII_DP83640_MICR, micr); 1191 if (err < 0) 1192 return err; 1193 1194 misr = phy_read(phydev, MII_DP83640_MISR); 1195 if (misr < 0) 1196 return misr; 1197 misr &= 1198 ~(MII_DP83640_MISR_ANC_INT_EN | 1199 MII_DP83640_MISR_DUP_INT_EN | 1200 MII_DP83640_MISR_SPD_INT_EN | 1201 MII_DP83640_MISR_LINK_INT_EN); 1202 err = phy_write(phydev, MII_DP83640_MISR, misr); 1203 if (err) 1204 return err; 1205 1206 return dp83640_ack_interrupt(phydev); 1207 } 1208 } 1209 1210 static irqreturn_t dp83640_handle_interrupt(struct phy_device *phydev) 1211 { 1212 int irq_status; 1213 1214 irq_status = phy_read(phydev, MII_DP83640_MISR); 1215 if (irq_status < 0) { 1216 phy_error(phydev); 1217 return IRQ_NONE; 1218 } 1219 1220 if (!(irq_status & MII_DP83640_MISR_INT_MASK)) 1221 return IRQ_NONE; 1222 1223 phy_trigger_machine(phydev); 1224 1225 return IRQ_HANDLED; 1226 } 1227 1228 static int dp83640_hwtstamp(struct mii_timestamper *mii_ts, struct ifreq *ifr) 1229 { 1230 struct dp83640_private *dp83640 = 1231 container_of(mii_ts, struct dp83640_private, mii_ts); 1232 struct hwtstamp_config cfg; 1233 u16 txcfg0, rxcfg0; 1234 1235 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 1236 return -EFAULT; 1237 1238 if (cfg.tx_type < 0 || cfg.tx_type > HWTSTAMP_TX_ONESTEP_SYNC) 1239 return -ERANGE; 1240 1241 dp83640->hwts_tx_en = cfg.tx_type; 1242 1243 switch (cfg.rx_filter) { 1244 case HWTSTAMP_FILTER_NONE: 1245 dp83640->hwts_rx_en = 0; 1246 dp83640->layer = 0; 1247 dp83640->version = 0; 1248 break; 1249 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 1250 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 1251 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 1252 dp83640->hwts_rx_en = 1; 1253 dp83640->layer = PTP_CLASS_L4; 1254 dp83640->version = PTP_CLASS_V1; 1255 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 1256 break; 1257 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1258 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1259 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1260 dp83640->hwts_rx_en = 1; 1261 dp83640->layer = PTP_CLASS_L4; 1262 dp83640->version = PTP_CLASS_V2; 1263 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; 1264 break; 1265 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1266 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1267 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1268 dp83640->hwts_rx_en = 1; 1269 dp83640->layer = PTP_CLASS_L2; 1270 dp83640->version = PTP_CLASS_V2; 1271 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; 1272 break; 1273 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1274 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1275 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1276 dp83640->hwts_rx_en = 1; 1277 dp83640->layer = PTP_CLASS_L4 | PTP_CLASS_L2; 1278 dp83640->version = PTP_CLASS_V2; 1279 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 1280 break; 1281 default: 1282 return -ERANGE; 1283 } 1284 1285 txcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT; 1286 rxcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT; 1287 1288 if (dp83640->layer & PTP_CLASS_L2) { 1289 txcfg0 |= TX_L2_EN; 1290 rxcfg0 |= RX_L2_EN; 1291 } 1292 if (dp83640->layer & PTP_CLASS_L4) { 1293 txcfg0 |= TX_IPV6_EN | TX_IPV4_EN; 1294 rxcfg0 |= RX_IPV6_EN | RX_IPV4_EN; 1295 } 1296 1297 if (dp83640->hwts_tx_en) 1298 txcfg0 |= TX_TS_EN; 1299 1300 if (dp83640->hwts_tx_en == HWTSTAMP_TX_ONESTEP_SYNC) 1301 txcfg0 |= SYNC_1STEP | CHK_1STEP; 1302 1303 if (dp83640->hwts_rx_en) 1304 rxcfg0 |= RX_TS_EN; 1305 1306 mutex_lock(&dp83640->clock->extreg_lock); 1307 1308 ext_write(0, dp83640->phydev, PAGE5, PTP_TXCFG0, txcfg0); 1309 ext_write(0, dp83640->phydev, PAGE5, PTP_RXCFG0, rxcfg0); 1310 1311 mutex_unlock(&dp83640->clock->extreg_lock); 1312 1313 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1314 } 1315 1316 static void rx_timestamp_work(struct work_struct *work) 1317 { 1318 struct dp83640_private *dp83640 = 1319 container_of(work, struct dp83640_private, ts_work.work); 1320 struct sk_buff *skb; 1321 1322 /* Deliver expired packets. */ 1323 while ((skb = skb_dequeue(&dp83640->rx_queue))) { 1324 struct dp83640_skb_info *skb_info; 1325 1326 skb_info = (struct dp83640_skb_info *)skb->cb; 1327 if (!time_after(jiffies, skb_info->tmo)) { 1328 skb_queue_head(&dp83640->rx_queue, skb); 1329 break; 1330 } 1331 1332 netif_rx_ni(skb); 1333 } 1334 1335 if (!skb_queue_empty(&dp83640->rx_queue)) 1336 schedule_delayed_work(&dp83640->ts_work, SKB_TIMESTAMP_TIMEOUT); 1337 } 1338 1339 static bool dp83640_rxtstamp(struct mii_timestamper *mii_ts, 1340 struct sk_buff *skb, int type) 1341 { 1342 struct dp83640_private *dp83640 = 1343 container_of(mii_ts, struct dp83640_private, mii_ts); 1344 struct dp83640_skb_info *skb_info = (struct dp83640_skb_info *)skb->cb; 1345 struct list_head *this, *next; 1346 struct rxts *rxts; 1347 struct skb_shared_hwtstamps *shhwtstamps = NULL; 1348 unsigned long flags; 1349 1350 if (is_status_frame(skb, type)) { 1351 decode_status_frame(dp83640, skb); 1352 kfree_skb(skb); 1353 return true; 1354 } 1355 1356 if (!dp83640->hwts_rx_en) 1357 return false; 1358 1359 if ((type & dp83640->version) == 0 || (type & dp83640->layer) == 0) 1360 return false; 1361 1362 spin_lock_irqsave(&dp83640->rx_lock, flags); 1363 prune_rx_ts(dp83640); 1364 list_for_each_safe(this, next, &dp83640->rxts) { 1365 rxts = list_entry(this, struct rxts, list); 1366 if (match(skb, type, rxts)) { 1367 shhwtstamps = skb_hwtstamps(skb); 1368 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 1369 shhwtstamps->hwtstamp = ns_to_ktime(rxts->ns); 1370 list_del_init(&rxts->list); 1371 list_add(&rxts->list, &dp83640->rxpool); 1372 break; 1373 } 1374 } 1375 spin_unlock_irqrestore(&dp83640->rx_lock, flags); 1376 1377 if (!shhwtstamps) { 1378 skb_info->ptp_type = type; 1379 skb_info->tmo = jiffies + SKB_TIMESTAMP_TIMEOUT; 1380 skb_queue_tail(&dp83640->rx_queue, skb); 1381 schedule_delayed_work(&dp83640->ts_work, SKB_TIMESTAMP_TIMEOUT); 1382 } else { 1383 netif_rx_ni(skb); 1384 } 1385 1386 return true; 1387 } 1388 1389 static void dp83640_txtstamp(struct mii_timestamper *mii_ts, 1390 struct sk_buff *skb, int type) 1391 { 1392 struct dp83640_skb_info *skb_info = (struct dp83640_skb_info *)skb->cb; 1393 struct dp83640_private *dp83640 = 1394 container_of(mii_ts, struct dp83640_private, mii_ts); 1395 1396 switch (dp83640->hwts_tx_en) { 1397 1398 case HWTSTAMP_TX_ONESTEP_SYNC: 1399 if (is_sync(skb, type)) { 1400 kfree_skb(skb); 1401 return; 1402 } 1403 fallthrough; 1404 case HWTSTAMP_TX_ON: 1405 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1406 skb_info->tmo = jiffies + SKB_TIMESTAMP_TIMEOUT; 1407 skb_queue_tail(&dp83640->tx_queue, skb); 1408 break; 1409 1410 case HWTSTAMP_TX_OFF: 1411 default: 1412 kfree_skb(skb); 1413 break; 1414 } 1415 } 1416 1417 static int dp83640_ts_info(struct mii_timestamper *mii_ts, 1418 struct ethtool_ts_info *info) 1419 { 1420 struct dp83640_private *dp83640 = 1421 container_of(mii_ts, struct dp83640_private, mii_ts); 1422 1423 info->so_timestamping = 1424 SOF_TIMESTAMPING_TX_HARDWARE | 1425 SOF_TIMESTAMPING_RX_HARDWARE | 1426 SOF_TIMESTAMPING_RAW_HARDWARE; 1427 info->phc_index = ptp_clock_index(dp83640->clock->ptp_clock); 1428 info->tx_types = 1429 (1 << HWTSTAMP_TX_OFF) | 1430 (1 << HWTSTAMP_TX_ON) | 1431 (1 << HWTSTAMP_TX_ONESTEP_SYNC); 1432 info->rx_filters = 1433 (1 << HWTSTAMP_FILTER_NONE) | 1434 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) | 1435 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) | 1436 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 1437 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT); 1438 return 0; 1439 } 1440 1441 static int dp83640_probe(struct phy_device *phydev) 1442 { 1443 struct dp83640_clock *clock; 1444 struct dp83640_private *dp83640; 1445 int err = -ENOMEM, i; 1446 1447 if (phydev->mdio.addr == BROADCAST_ADDR) 1448 return 0; 1449 1450 clock = dp83640_clock_get_bus(phydev->mdio.bus); 1451 if (!clock) 1452 goto no_clock; 1453 1454 dp83640 = kzalloc(sizeof(struct dp83640_private), GFP_KERNEL); 1455 if (!dp83640) 1456 goto no_memory; 1457 1458 dp83640->phydev = phydev; 1459 dp83640->mii_ts.rxtstamp = dp83640_rxtstamp; 1460 dp83640->mii_ts.txtstamp = dp83640_txtstamp; 1461 dp83640->mii_ts.hwtstamp = dp83640_hwtstamp; 1462 dp83640->mii_ts.ts_info = dp83640_ts_info; 1463 1464 INIT_DELAYED_WORK(&dp83640->ts_work, rx_timestamp_work); 1465 INIT_LIST_HEAD(&dp83640->rxts); 1466 INIT_LIST_HEAD(&dp83640->rxpool); 1467 for (i = 0; i < MAX_RXTS; i++) 1468 list_add(&dp83640->rx_pool_data[i].list, &dp83640->rxpool); 1469 1470 phydev->mii_ts = &dp83640->mii_ts; 1471 phydev->priv = dp83640; 1472 1473 spin_lock_init(&dp83640->rx_lock); 1474 skb_queue_head_init(&dp83640->rx_queue); 1475 skb_queue_head_init(&dp83640->tx_queue); 1476 1477 dp83640->clock = clock; 1478 1479 if (choose_this_phy(clock, phydev)) { 1480 clock->chosen = dp83640; 1481 clock->ptp_clock = ptp_clock_register(&clock->caps, 1482 &phydev->mdio.dev); 1483 if (IS_ERR(clock->ptp_clock)) { 1484 err = PTR_ERR(clock->ptp_clock); 1485 goto no_register; 1486 } 1487 } else 1488 list_add_tail(&dp83640->list, &clock->phylist); 1489 1490 dp83640_clock_put(clock); 1491 return 0; 1492 1493 no_register: 1494 clock->chosen = NULL; 1495 kfree(dp83640); 1496 no_memory: 1497 dp83640_clock_put(clock); 1498 no_clock: 1499 return err; 1500 } 1501 1502 static void dp83640_remove(struct phy_device *phydev) 1503 { 1504 struct dp83640_clock *clock; 1505 struct list_head *this, *next; 1506 struct dp83640_private *tmp, *dp83640 = phydev->priv; 1507 1508 if (phydev->mdio.addr == BROADCAST_ADDR) 1509 return; 1510 1511 phydev->mii_ts = NULL; 1512 1513 enable_status_frames(phydev, false); 1514 cancel_delayed_work_sync(&dp83640->ts_work); 1515 1516 skb_queue_purge(&dp83640->rx_queue); 1517 skb_queue_purge(&dp83640->tx_queue); 1518 1519 clock = dp83640_clock_get(dp83640->clock); 1520 1521 if (dp83640 == clock->chosen) { 1522 ptp_clock_unregister(clock->ptp_clock); 1523 clock->chosen = NULL; 1524 } else { 1525 list_for_each_safe(this, next, &clock->phylist) { 1526 tmp = list_entry(this, struct dp83640_private, list); 1527 if (tmp == dp83640) { 1528 list_del_init(&tmp->list); 1529 break; 1530 } 1531 } 1532 } 1533 1534 dp83640_clock_put(clock); 1535 kfree(dp83640); 1536 } 1537 1538 static struct phy_driver dp83640_driver = { 1539 .phy_id = DP83640_PHY_ID, 1540 .phy_id_mask = 0xfffffff0, 1541 .name = "NatSemi DP83640", 1542 /* PHY_BASIC_FEATURES */ 1543 .probe = dp83640_probe, 1544 .remove = dp83640_remove, 1545 .soft_reset = dp83640_soft_reset, 1546 .config_init = dp83640_config_init, 1547 .config_intr = dp83640_config_intr, 1548 .handle_interrupt = dp83640_handle_interrupt, 1549 }; 1550 1551 static int __init dp83640_init(void) 1552 { 1553 return phy_driver_register(&dp83640_driver, THIS_MODULE); 1554 } 1555 1556 static void __exit dp83640_exit(void) 1557 { 1558 dp83640_free_clocks(); 1559 phy_driver_unregister(&dp83640_driver); 1560 } 1561 1562 MODULE_DESCRIPTION("National Semiconductor DP83640 PHY driver"); 1563 MODULE_AUTHOR("Richard Cochran <richardcochran@gmail.com>"); 1564 MODULE_LICENSE("GPL"); 1565 1566 module_init(dp83640_init); 1567 module_exit(dp83640_exit); 1568 1569 static struct mdio_device_id __maybe_unused dp83640_tbl[] = { 1570 { DP83640_PHY_ID, 0xfffffff0 }, 1571 { } 1572 }; 1573 1574 MODULE_DEVICE_TABLE(mdio, dp83640_tbl); 1575