1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * drivers/net/phy/broadcom.c 4 * 5 * Broadcom BCM5411, BCM5421 and BCM5461 Gigabit Ethernet 6 * transceivers. 7 * 8 * Copyright (c) 2006 Maciej W. Rozycki 9 * 10 * Inspired by code written by Amy Fong. 11 */ 12 13 #include "bcm-phy-lib.h" 14 #include <linux/delay.h> 15 #include <linux/module.h> 16 #include <linux/phy.h> 17 #include <linux/pm_wakeup.h> 18 #include <linux/brcmphy.h> 19 #include <linux/of.h> 20 #include <linux/interrupt.h> 21 #include <linux/irq.h> 22 #include <linux/gpio/consumer.h> 23 24 #define BRCM_PHY_MODEL(phydev) \ 25 ((phydev)->drv->phy_id & (phydev)->drv->phy_id_mask) 26 27 #define BRCM_PHY_REV(phydev) \ 28 ((phydev)->drv->phy_id & ~((phydev)->drv->phy_id_mask)) 29 30 MODULE_DESCRIPTION("Broadcom PHY driver"); 31 MODULE_AUTHOR("Maciej W. Rozycki"); 32 MODULE_LICENSE("GPL"); 33 34 struct bcm54xx_phy_priv { 35 u64 *stats; 36 struct bcm_ptp_private *ptp; 37 int wake_irq; 38 bool wake_irq_enabled; 39 }; 40 41 static bool bcm54xx_phy_can_wakeup(struct phy_device *phydev) 42 { 43 struct bcm54xx_phy_priv *priv = phydev->priv; 44 45 return phy_interrupt_is_valid(phydev) || priv->wake_irq >= 0; 46 } 47 48 static int bcm54xx_config_clock_delay(struct phy_device *phydev) 49 { 50 int rc, val; 51 52 /* handling PHY's internal RX clock delay */ 53 val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC); 54 val |= MII_BCM54XX_AUXCTL_MISC_WREN; 55 if (phydev->interface == PHY_INTERFACE_MODE_RGMII || 56 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) { 57 /* Disable RGMII RXC-RXD skew */ 58 val &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN; 59 } 60 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 61 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) { 62 /* Enable RGMII RXC-RXD skew */ 63 val |= MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN; 64 } 65 rc = bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC, 66 val); 67 if (rc < 0) 68 return rc; 69 70 /* handling PHY's internal TX clock delay */ 71 val = bcm_phy_read_shadow(phydev, BCM54810_SHD_CLK_CTL); 72 if (phydev->interface == PHY_INTERFACE_MODE_RGMII || 73 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) { 74 /* Disable internal TX clock delay */ 75 val &= ~BCM54810_SHD_CLK_CTL_GTXCLK_EN; 76 } 77 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 78 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) { 79 /* Enable internal TX clock delay */ 80 val |= BCM54810_SHD_CLK_CTL_GTXCLK_EN; 81 } 82 rc = bcm_phy_write_shadow(phydev, BCM54810_SHD_CLK_CTL, val); 83 if (rc < 0) 84 return rc; 85 86 return 0; 87 } 88 89 static int bcm54210e_config_init(struct phy_device *phydev) 90 { 91 int val; 92 93 bcm54xx_config_clock_delay(phydev); 94 95 if (phydev->dev_flags & PHY_BRCM_EN_MASTER_MODE) { 96 val = phy_read(phydev, MII_CTRL1000); 97 val |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER; 98 phy_write(phydev, MII_CTRL1000, val); 99 } 100 101 return 0; 102 } 103 104 static int bcm54612e_config_init(struct phy_device *phydev) 105 { 106 int reg; 107 108 bcm54xx_config_clock_delay(phydev); 109 110 /* Enable CLK125 MUX on LED4 if ref clock is enabled. */ 111 if (!(phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED)) { 112 int err; 113 114 reg = bcm_phy_read_exp(phydev, BCM54612E_EXP_SPARE0); 115 err = bcm_phy_write_exp(phydev, BCM54612E_EXP_SPARE0, 116 BCM54612E_LED4_CLK125OUT_EN | reg); 117 118 if (err < 0) 119 return err; 120 } 121 122 return 0; 123 } 124 125 static int bcm54616s_config_init(struct phy_device *phydev) 126 { 127 int rc, val; 128 129 if (phydev->interface != PHY_INTERFACE_MODE_SGMII && 130 phydev->interface != PHY_INTERFACE_MODE_1000BASEX) 131 return 0; 132 133 /* Ensure proper interface mode is selected. */ 134 /* Disable RGMII mode */ 135 val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC); 136 if (val < 0) 137 return val; 138 val &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_EN; 139 val |= MII_BCM54XX_AUXCTL_MISC_WREN; 140 rc = bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC, 141 val); 142 if (rc < 0) 143 return rc; 144 145 /* Select 1000BASE-X register set (primary SerDes) */ 146 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_MODE); 147 if (val < 0) 148 return val; 149 val |= BCM54XX_SHD_MODE_1000BX; 150 rc = bcm_phy_write_shadow(phydev, BCM54XX_SHD_MODE, val); 151 if (rc < 0) 152 return rc; 153 154 /* Power down SerDes interface */ 155 rc = phy_set_bits(phydev, MII_BMCR, BMCR_PDOWN); 156 if (rc < 0) 157 return rc; 158 159 /* Select proper interface mode */ 160 val &= ~BCM54XX_SHD_INTF_SEL_MASK; 161 val |= phydev->interface == PHY_INTERFACE_MODE_SGMII ? 162 BCM54XX_SHD_INTF_SEL_SGMII : 163 BCM54XX_SHD_INTF_SEL_GBIC; 164 rc = bcm_phy_write_shadow(phydev, BCM54XX_SHD_MODE, val); 165 if (rc < 0) 166 return rc; 167 168 /* Power up SerDes interface */ 169 rc = phy_clear_bits(phydev, MII_BMCR, BMCR_PDOWN); 170 if (rc < 0) 171 return rc; 172 173 /* Select copper register set */ 174 val &= ~BCM54XX_SHD_MODE_1000BX; 175 rc = bcm_phy_write_shadow(phydev, BCM54XX_SHD_MODE, val); 176 if (rc < 0) 177 return rc; 178 179 /* Power up copper interface */ 180 return phy_clear_bits(phydev, MII_BMCR, BMCR_PDOWN); 181 } 182 183 /* Needs SMDSP clock enabled via bcm54xx_phydsp_config() */ 184 static int bcm50610_a0_workaround(struct phy_device *phydev) 185 { 186 int err; 187 188 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_AADJ1CH0, 189 MII_BCM54XX_EXP_AADJ1CH0_SWP_ABCD_OEN | 190 MII_BCM54XX_EXP_AADJ1CH0_SWSEL_THPF); 191 if (err < 0) 192 return err; 193 194 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_AADJ1CH3, 195 MII_BCM54XX_EXP_AADJ1CH3_ADCCKADJ); 196 if (err < 0) 197 return err; 198 199 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP75, 200 MII_BCM54XX_EXP_EXP75_VDACCTRL); 201 if (err < 0) 202 return err; 203 204 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP96, 205 MII_BCM54XX_EXP_EXP96_MYST); 206 if (err < 0) 207 return err; 208 209 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP97, 210 MII_BCM54XX_EXP_EXP97_MYST); 211 212 return err; 213 } 214 215 static int bcm54xx_phydsp_config(struct phy_device *phydev) 216 { 217 int err, err2; 218 219 /* Enable the SMDSP clock */ 220 err = bcm54xx_auxctl_write(phydev, 221 MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL, 222 MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA | 223 MII_BCM54XX_AUXCTL_ACTL_TX_6DB); 224 if (err < 0) 225 return err; 226 227 if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 || 228 BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) { 229 /* Clear bit 9 to fix a phy interop issue. */ 230 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP08, 231 MII_BCM54XX_EXP_EXP08_RJCT_2MHZ); 232 if (err < 0) 233 goto error; 234 235 if (phydev->drv->phy_id == PHY_ID_BCM50610) { 236 err = bcm50610_a0_workaround(phydev); 237 if (err < 0) 238 goto error; 239 } 240 } 241 242 if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM57780) { 243 int val; 244 245 val = bcm_phy_read_exp(phydev, MII_BCM54XX_EXP_EXP75); 246 if (val < 0) 247 goto error; 248 249 val |= MII_BCM54XX_EXP_EXP75_CM_OSC; 250 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP75, val); 251 } 252 253 error: 254 /* Disable the SMDSP clock */ 255 err2 = bcm54xx_auxctl_write(phydev, 256 MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL, 257 MII_BCM54XX_AUXCTL_ACTL_TX_6DB); 258 259 /* Return the first error reported. */ 260 return err ? err : err2; 261 } 262 263 static void bcm54xx_adjust_rxrefclk(struct phy_device *phydev) 264 { 265 u32 orig; 266 int val; 267 bool clk125en = true; 268 269 /* Abort if we are using an untested phy. */ 270 if (BRCM_PHY_MODEL(phydev) != PHY_ID_BCM57780 && 271 BRCM_PHY_MODEL(phydev) != PHY_ID_BCM50610 && 272 BRCM_PHY_MODEL(phydev) != PHY_ID_BCM50610M && 273 BRCM_PHY_MODEL(phydev) != PHY_ID_BCM54210E && 274 BRCM_PHY_MODEL(phydev) != PHY_ID_BCM54810 && 275 BRCM_PHY_MODEL(phydev) != PHY_ID_BCM54811) 276 return; 277 278 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_SCR3); 279 if (val < 0) 280 return; 281 282 orig = val; 283 284 if ((BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 || 285 BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) && 286 BRCM_PHY_REV(phydev) >= 0x3) { 287 /* 288 * Here, bit 0 _disables_ CLK125 when set. 289 * This bit is set by default. 290 */ 291 clk125en = false; 292 } else { 293 if (phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED) { 294 if (BRCM_PHY_MODEL(phydev) != PHY_ID_BCM54811) { 295 /* Here, bit 0 _enables_ CLK125 when set */ 296 val &= ~BCM54XX_SHD_SCR3_DEF_CLK125; 297 } 298 clk125en = false; 299 } 300 } 301 302 if (!clk125en || (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE)) 303 val &= ~BCM54XX_SHD_SCR3_DLLAPD_DIS; 304 else 305 val |= BCM54XX_SHD_SCR3_DLLAPD_DIS; 306 307 if (phydev->dev_flags & PHY_BRCM_DIS_TXCRXC_NOENRGY) { 308 if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54210E || 309 BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54810 || 310 BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54811) 311 val |= BCM54XX_SHD_SCR3_RXCTXC_DIS; 312 else 313 val |= BCM54XX_SHD_SCR3_TRDDAPD; 314 } 315 316 if (orig != val) 317 bcm_phy_write_shadow(phydev, BCM54XX_SHD_SCR3, val); 318 319 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_APD); 320 if (val < 0) 321 return; 322 323 orig = val; 324 325 if (!clk125en || (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE)) 326 val |= BCM54XX_SHD_APD_EN; 327 else 328 val &= ~BCM54XX_SHD_APD_EN; 329 330 if (orig != val) 331 bcm_phy_write_shadow(phydev, BCM54XX_SHD_APD, val); 332 } 333 334 static void bcm54xx_ptp_stop(struct phy_device *phydev) 335 { 336 struct bcm54xx_phy_priv *priv = phydev->priv; 337 338 if (priv->ptp) 339 bcm_ptp_stop(priv->ptp); 340 } 341 342 static void bcm54xx_ptp_config_init(struct phy_device *phydev) 343 { 344 struct bcm54xx_phy_priv *priv = phydev->priv; 345 346 if (priv->ptp) 347 bcm_ptp_config_init(phydev); 348 } 349 350 static int bcm54xx_config_init(struct phy_device *phydev) 351 { 352 int reg, err, val; 353 354 reg = phy_read(phydev, MII_BCM54XX_ECR); 355 if (reg < 0) 356 return reg; 357 358 /* Mask interrupts globally. */ 359 reg |= MII_BCM54XX_ECR_IM; 360 err = phy_write(phydev, MII_BCM54XX_ECR, reg); 361 if (err < 0) 362 return err; 363 364 /* Unmask events we are interested in. */ 365 reg = ~(MII_BCM54XX_INT_DUPLEX | 366 MII_BCM54XX_INT_SPEED | 367 MII_BCM54XX_INT_LINK); 368 err = phy_write(phydev, MII_BCM54XX_IMR, reg); 369 if (err < 0) 370 return err; 371 372 if ((BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 || 373 BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) && 374 (phydev->dev_flags & PHY_BRCM_CLEAR_RGMII_MODE)) 375 bcm_phy_write_shadow(phydev, BCM54XX_SHD_RGMII_MODE, 0); 376 377 bcm54xx_adjust_rxrefclk(phydev); 378 379 switch (BRCM_PHY_MODEL(phydev)) { 380 case PHY_ID_BCM50610: 381 case PHY_ID_BCM50610M: 382 err = bcm54xx_config_clock_delay(phydev); 383 break; 384 case PHY_ID_BCM54210E: 385 err = bcm54210e_config_init(phydev); 386 break; 387 case PHY_ID_BCM54612E: 388 err = bcm54612e_config_init(phydev); 389 break; 390 case PHY_ID_BCM54616S: 391 err = bcm54616s_config_init(phydev); 392 break; 393 case PHY_ID_BCM54810: 394 /* For BCM54810, we need to disable BroadR-Reach function */ 395 val = bcm_phy_read_exp(phydev, 396 BCM54810_EXP_BROADREACH_LRE_MISC_CTL); 397 val &= ~BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN; 398 err = bcm_phy_write_exp(phydev, 399 BCM54810_EXP_BROADREACH_LRE_MISC_CTL, 400 val); 401 break; 402 } 403 if (err) 404 return err; 405 406 bcm54xx_phydsp_config(phydev); 407 408 /* For non-SFP setups, encode link speed into LED1 and LED3 pair 409 * (green/amber). 410 * Also flash these two LEDs on activity. This means configuring 411 * them for MULTICOLOR and encoding link/activity into them. 412 * Don't do this for devices on an SFP module, since some of these 413 * use the LED outputs to control the SFP LOS signal, and changing 414 * these settings will cause LOS to malfunction. 415 */ 416 if (!phy_on_sfp(phydev)) { 417 val = BCM54XX_SHD_LEDS1_LED1(BCM_LED_SRC_MULTICOLOR1) | 418 BCM54XX_SHD_LEDS1_LED3(BCM_LED_SRC_MULTICOLOR1); 419 bcm_phy_write_shadow(phydev, BCM54XX_SHD_LEDS1, val); 420 421 val = BCM_LED_MULTICOLOR_IN_PHASE | 422 BCM54XX_SHD_LEDS1_LED1(BCM_LED_MULTICOLOR_LINK_ACT) | 423 BCM54XX_SHD_LEDS1_LED3(BCM_LED_MULTICOLOR_LINK_ACT); 424 bcm_phy_write_exp(phydev, BCM_EXP_MULTICOLOR, val); 425 } 426 427 bcm54xx_ptp_config_init(phydev); 428 429 /* Acknowledge any left over interrupt and charge the device for 430 * wake-up. 431 */ 432 err = bcm_phy_read_exp(phydev, BCM54XX_WOL_INT_STATUS); 433 if (err < 0) 434 return err; 435 436 if (err) 437 pm_wakeup_event(&phydev->mdio.dev, 0); 438 439 return 0; 440 } 441 442 static int bcm54xx_iddq_set(struct phy_device *phydev, bool enable) 443 { 444 int ret = 0; 445 446 if (!(phydev->dev_flags & PHY_BRCM_IDDQ_SUSPEND)) 447 return ret; 448 449 ret = bcm_phy_read_exp(phydev, BCM54XX_TOP_MISC_IDDQ_CTRL); 450 if (ret < 0) 451 goto out; 452 453 if (enable) 454 ret |= BCM54XX_TOP_MISC_IDDQ_SR | BCM54XX_TOP_MISC_IDDQ_LP; 455 else 456 ret &= ~(BCM54XX_TOP_MISC_IDDQ_SR | BCM54XX_TOP_MISC_IDDQ_LP); 457 458 ret = bcm_phy_write_exp(phydev, BCM54XX_TOP_MISC_IDDQ_CTRL, ret); 459 out: 460 return ret; 461 } 462 463 static int bcm54xx_set_wakeup_irq(struct phy_device *phydev, bool state) 464 { 465 struct bcm54xx_phy_priv *priv = phydev->priv; 466 int ret = 0; 467 468 if (!bcm54xx_phy_can_wakeup(phydev)) 469 return ret; 470 471 if (priv->wake_irq_enabled != state) { 472 if (state) 473 ret = enable_irq_wake(priv->wake_irq); 474 else 475 ret = disable_irq_wake(priv->wake_irq); 476 priv->wake_irq_enabled = state; 477 } 478 479 return ret; 480 } 481 482 static int bcm54xx_suspend(struct phy_device *phydev) 483 { 484 int ret = 0; 485 486 bcm54xx_ptp_stop(phydev); 487 488 /* Acknowledge any Wake-on-LAN interrupt prior to suspend */ 489 ret = bcm_phy_read_exp(phydev, BCM54XX_WOL_INT_STATUS); 490 if (ret < 0) 491 return ret; 492 493 if (phydev->wol_enabled) 494 return bcm54xx_set_wakeup_irq(phydev, true); 495 496 /* We cannot use a read/modify/write here otherwise the PHY gets into 497 * a bad state where its LEDs keep flashing, thus defeating the purpose 498 * of low power mode. 499 */ 500 ret = phy_write(phydev, MII_BMCR, BMCR_PDOWN); 501 if (ret < 0) 502 return ret; 503 504 return bcm54xx_iddq_set(phydev, true); 505 } 506 507 static int bcm54xx_resume(struct phy_device *phydev) 508 { 509 int ret = 0; 510 511 if (phydev->wol_enabled) { 512 ret = bcm54xx_set_wakeup_irq(phydev, false); 513 if (ret) 514 return ret; 515 } 516 517 ret = bcm54xx_iddq_set(phydev, false); 518 if (ret < 0) 519 return ret; 520 521 /* Writes to register other than BMCR would be ignored 522 * unless we clear the PDOWN bit first 523 */ 524 ret = genphy_resume(phydev); 525 if (ret < 0) 526 return ret; 527 528 /* Upon exiting power down, the PHY remains in an internal reset state 529 * for 40us 530 */ 531 fsleep(40); 532 533 /* Issue a soft reset after clearing the power down bit 534 * and before doing any other configuration. 535 */ 536 if (phydev->dev_flags & PHY_BRCM_IDDQ_SUSPEND) { 537 ret = genphy_soft_reset(phydev); 538 if (ret < 0) 539 return ret; 540 } 541 542 return bcm54xx_config_init(phydev); 543 } 544 545 static int bcm54811_config_init(struct phy_device *phydev) 546 { 547 int err, reg; 548 549 /* Disable BroadR-Reach function. */ 550 reg = bcm_phy_read_exp(phydev, BCM54810_EXP_BROADREACH_LRE_MISC_CTL); 551 reg &= ~BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN; 552 err = bcm_phy_write_exp(phydev, BCM54810_EXP_BROADREACH_LRE_MISC_CTL, 553 reg); 554 if (err < 0) 555 return err; 556 557 err = bcm54xx_config_init(phydev); 558 559 /* Enable CLK125 MUX on LED4 if ref clock is enabled. */ 560 if (!(phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED)) { 561 reg = bcm_phy_read_exp(phydev, BCM54612E_EXP_SPARE0); 562 err = bcm_phy_write_exp(phydev, BCM54612E_EXP_SPARE0, 563 BCM54612E_LED4_CLK125OUT_EN | reg); 564 if (err < 0) 565 return err; 566 } 567 568 return err; 569 } 570 571 static int bcm5481_config_aneg(struct phy_device *phydev) 572 { 573 struct device_node *np = phydev->mdio.dev.of_node; 574 int ret; 575 576 /* Aneg firstly. */ 577 ret = genphy_config_aneg(phydev); 578 579 /* Then we can set up the delay. */ 580 bcm54xx_config_clock_delay(phydev); 581 582 if (of_property_read_bool(np, "enet-phy-lane-swap")) { 583 /* Lane Swap - Undocumented register...magic! */ 584 ret = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_SEL_ER + 0x9, 585 0x11B); 586 if (ret < 0) 587 return ret; 588 } 589 590 return ret; 591 } 592 593 struct bcm54616s_phy_priv { 594 bool mode_1000bx_en; 595 }; 596 597 static int bcm54616s_probe(struct phy_device *phydev) 598 { 599 struct bcm54616s_phy_priv *priv; 600 int val; 601 602 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); 603 if (!priv) 604 return -ENOMEM; 605 606 phydev->priv = priv; 607 608 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_MODE); 609 if (val < 0) 610 return val; 611 612 /* The PHY is strapped in RGMII-fiber mode when INTERF_SEL[1:0] 613 * is 01b, and the link between PHY and its link partner can be 614 * either 1000Base-X or 100Base-FX. 615 * RGMII-1000Base-X is properly supported, but RGMII-100Base-FX 616 * support is still missing as of now. 617 */ 618 if ((val & BCM54XX_SHD_INTF_SEL_MASK) == BCM54XX_SHD_INTF_SEL_RGMII) { 619 val = bcm_phy_read_shadow(phydev, BCM54616S_SHD_100FX_CTRL); 620 if (val < 0) 621 return val; 622 623 /* Bit 0 of the SerDes 100-FX Control register, when set 624 * to 1, sets the MII/RGMII -> 100BASE-FX configuration. 625 * When this bit is set to 0, it sets the GMII/RGMII -> 626 * 1000BASE-X configuration. 627 */ 628 if (!(val & BCM54616S_100FX_MODE)) 629 priv->mode_1000bx_en = true; 630 631 phydev->port = PORT_FIBRE; 632 } 633 634 return 0; 635 } 636 637 static int bcm54616s_config_aneg(struct phy_device *phydev) 638 { 639 struct bcm54616s_phy_priv *priv = phydev->priv; 640 int ret; 641 642 /* Aneg firstly. */ 643 if (priv->mode_1000bx_en) 644 ret = genphy_c37_config_aneg(phydev); 645 else 646 ret = genphy_config_aneg(phydev); 647 648 /* Then we can set up the delay. */ 649 bcm54xx_config_clock_delay(phydev); 650 651 return ret; 652 } 653 654 static int bcm54616s_read_status(struct phy_device *phydev) 655 { 656 struct bcm54616s_phy_priv *priv = phydev->priv; 657 int err; 658 659 if (priv->mode_1000bx_en) 660 err = genphy_c37_read_status(phydev); 661 else 662 err = genphy_read_status(phydev); 663 664 return err; 665 } 666 667 static int brcm_fet_config_init(struct phy_device *phydev) 668 { 669 int reg, err, err2, brcmtest; 670 671 /* Reset the PHY to bring it to a known state. */ 672 err = phy_write(phydev, MII_BMCR, BMCR_RESET); 673 if (err < 0) 674 return err; 675 676 /* The datasheet indicates the PHY needs up to 1us to complete a reset, 677 * build some slack here. 678 */ 679 usleep_range(1000, 2000); 680 681 /* The PHY requires 65 MDC clock cycles to complete a write operation 682 * and turnaround the line properly. 683 * 684 * We ignore -EIO here as the MDIO controller (e.g.: mdio-bcm-unimac) 685 * may flag the lack of turn-around as a read failure. This is 686 * particularly true with this combination since the MDIO controller 687 * only used 64 MDC cycles. This is not a critical failure in this 688 * specific case and it has no functional impact otherwise, so we let 689 * that one go through. If there is a genuine bus error, the next read 690 * of MII_BRCM_FET_INTREG will error out. 691 */ 692 err = phy_read(phydev, MII_BMCR); 693 if (err < 0 && err != -EIO) 694 return err; 695 696 reg = phy_read(phydev, MII_BRCM_FET_INTREG); 697 if (reg < 0) 698 return reg; 699 700 /* Unmask events we are interested in and mask interrupts globally. */ 701 reg = MII_BRCM_FET_IR_DUPLEX_EN | 702 MII_BRCM_FET_IR_SPEED_EN | 703 MII_BRCM_FET_IR_LINK_EN | 704 MII_BRCM_FET_IR_ENABLE | 705 MII_BRCM_FET_IR_MASK; 706 707 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg); 708 if (err < 0) 709 return err; 710 711 /* Enable shadow register access */ 712 brcmtest = phy_read(phydev, MII_BRCM_FET_BRCMTEST); 713 if (brcmtest < 0) 714 return brcmtest; 715 716 reg = brcmtest | MII_BRCM_FET_BT_SRE; 717 718 err = phy_write(phydev, MII_BRCM_FET_BRCMTEST, reg); 719 if (err < 0) 720 return err; 721 722 /* Set the LED mode */ 723 reg = phy_read(phydev, MII_BRCM_FET_SHDW_AUXMODE4); 724 if (reg < 0) { 725 err = reg; 726 goto done; 727 } 728 729 reg &= ~MII_BRCM_FET_SHDW_AM4_LED_MASK; 730 reg |= MII_BRCM_FET_SHDW_AM4_LED_MODE1; 731 732 err = phy_write(phydev, MII_BRCM_FET_SHDW_AUXMODE4, reg); 733 if (err < 0) 734 goto done; 735 736 /* Enable auto MDIX */ 737 err = phy_set_bits(phydev, MII_BRCM_FET_SHDW_MISCCTRL, 738 MII_BRCM_FET_SHDW_MC_FAME); 739 if (err < 0) 740 goto done; 741 742 if (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE) { 743 /* Enable auto power down */ 744 err = phy_set_bits(phydev, MII_BRCM_FET_SHDW_AUXSTAT2, 745 MII_BRCM_FET_SHDW_AS2_APDE); 746 } 747 748 done: 749 /* Disable shadow register access */ 750 err2 = phy_write(phydev, MII_BRCM_FET_BRCMTEST, brcmtest); 751 if (!err) 752 err = err2; 753 754 return err; 755 } 756 757 static int brcm_fet_ack_interrupt(struct phy_device *phydev) 758 { 759 int reg; 760 761 /* Clear pending interrupts. */ 762 reg = phy_read(phydev, MII_BRCM_FET_INTREG); 763 if (reg < 0) 764 return reg; 765 766 return 0; 767 } 768 769 static int brcm_fet_config_intr(struct phy_device *phydev) 770 { 771 int reg, err; 772 773 reg = phy_read(phydev, MII_BRCM_FET_INTREG); 774 if (reg < 0) 775 return reg; 776 777 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 778 err = brcm_fet_ack_interrupt(phydev); 779 if (err) 780 return err; 781 782 reg &= ~MII_BRCM_FET_IR_MASK; 783 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg); 784 } else { 785 reg |= MII_BRCM_FET_IR_MASK; 786 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg); 787 if (err) 788 return err; 789 790 err = brcm_fet_ack_interrupt(phydev); 791 } 792 793 return err; 794 } 795 796 static irqreturn_t brcm_fet_handle_interrupt(struct phy_device *phydev) 797 { 798 int irq_status; 799 800 irq_status = phy_read(phydev, MII_BRCM_FET_INTREG); 801 if (irq_status < 0) { 802 phy_error(phydev); 803 return IRQ_NONE; 804 } 805 806 if (irq_status == 0) 807 return IRQ_NONE; 808 809 phy_trigger_machine(phydev); 810 811 return IRQ_HANDLED; 812 } 813 814 static int brcm_fet_suspend(struct phy_device *phydev) 815 { 816 int reg, err, err2, brcmtest; 817 818 /* We cannot use a read/modify/write here otherwise the PHY continues 819 * to drive LEDs which defeats the purpose of low power mode. 820 */ 821 err = phy_write(phydev, MII_BMCR, BMCR_PDOWN); 822 if (err < 0) 823 return err; 824 825 /* Enable shadow register access */ 826 brcmtest = phy_read(phydev, MII_BRCM_FET_BRCMTEST); 827 if (brcmtest < 0) 828 return brcmtest; 829 830 reg = brcmtest | MII_BRCM_FET_BT_SRE; 831 832 err = phy_write(phydev, MII_BRCM_FET_BRCMTEST, reg); 833 if (err < 0) 834 return err; 835 836 /* Set standby mode */ 837 err = phy_modify(phydev, MII_BRCM_FET_SHDW_AUXMODE4, 838 MII_BRCM_FET_SHDW_AM4_STANDBY, 839 MII_BRCM_FET_SHDW_AM4_STANDBY); 840 841 /* Disable shadow register access */ 842 err2 = phy_write(phydev, MII_BRCM_FET_BRCMTEST, brcmtest); 843 if (!err) 844 err = err2; 845 846 return err; 847 } 848 849 static void bcm54xx_phy_get_wol(struct phy_device *phydev, 850 struct ethtool_wolinfo *wol) 851 { 852 /* We cannot wake-up if we do not have a dedicated PHY interrupt line 853 * or an out of band GPIO descriptor for wake-up. Zeroing 854 * wol->supported allows the caller (MAC driver) to play through and 855 * offer its own Wake-on-LAN scheme if available. 856 */ 857 if (!bcm54xx_phy_can_wakeup(phydev)) { 858 wol->supported = 0; 859 return; 860 } 861 862 bcm_phy_get_wol(phydev, wol); 863 } 864 865 static int bcm54xx_phy_set_wol(struct phy_device *phydev, 866 struct ethtool_wolinfo *wol) 867 { 868 int ret; 869 870 /* We cannot wake-up if we do not have a dedicated PHY interrupt line 871 * or an out of band GPIO descriptor for wake-up. Returning -EOPNOTSUPP 872 * allows the caller (MAC driver) to play through and offer its own 873 * Wake-on-LAN scheme if available. 874 */ 875 if (!bcm54xx_phy_can_wakeup(phydev)) 876 return -EOPNOTSUPP; 877 878 ret = bcm_phy_set_wol(phydev, wol); 879 if (ret < 0) 880 return ret; 881 882 return 0; 883 } 884 885 static int bcm54xx_phy_probe(struct phy_device *phydev) 886 { 887 struct bcm54xx_phy_priv *priv; 888 struct gpio_desc *wakeup_gpio; 889 int ret = 0; 890 891 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); 892 if (!priv) 893 return -ENOMEM; 894 895 priv->wake_irq = -ENXIO; 896 897 phydev->priv = priv; 898 899 priv->stats = devm_kcalloc(&phydev->mdio.dev, 900 bcm_phy_get_sset_count(phydev), sizeof(u64), 901 GFP_KERNEL); 902 if (!priv->stats) 903 return -ENOMEM; 904 905 priv->ptp = bcm_ptp_probe(phydev); 906 if (IS_ERR(priv->ptp)) 907 return PTR_ERR(priv->ptp); 908 909 /* We cannot utilize the _optional variant here since we want to know 910 * whether the GPIO descriptor exists or not to advertise Wake-on-LAN 911 * support or not. 912 */ 913 wakeup_gpio = devm_gpiod_get(&phydev->mdio.dev, "wakeup", GPIOD_IN); 914 if (PTR_ERR(wakeup_gpio) == -EPROBE_DEFER) 915 return PTR_ERR(wakeup_gpio); 916 917 if (!IS_ERR(wakeup_gpio)) { 918 priv->wake_irq = gpiod_to_irq(wakeup_gpio); 919 920 /* Dummy interrupt handler which is not enabled but is provided 921 * in order for the interrupt descriptor to be fully set-up. 922 */ 923 ret = devm_request_irq(&phydev->mdio.dev, priv->wake_irq, 924 bcm_phy_wol_isr, 925 IRQF_TRIGGER_LOW | IRQF_NO_AUTOEN, 926 dev_name(&phydev->mdio.dev), phydev); 927 if (ret) 928 return ret; 929 } 930 931 /* If we do not have a main interrupt or a side-band wake-up interrupt, 932 * then the device cannot be marked as wake-up capable. 933 */ 934 if (!bcm54xx_phy_can_wakeup(phydev)) 935 return 0; 936 937 return device_init_wakeup(&phydev->mdio.dev, true); 938 } 939 940 static void bcm54xx_get_stats(struct phy_device *phydev, 941 struct ethtool_stats *stats, u64 *data) 942 { 943 struct bcm54xx_phy_priv *priv = phydev->priv; 944 945 bcm_phy_get_stats(phydev, priv->stats, stats, data); 946 } 947 948 static void bcm54xx_link_change_notify(struct phy_device *phydev) 949 { 950 u16 mask = MII_BCM54XX_EXP_EXP08_EARLY_DAC_WAKE | 951 MII_BCM54XX_EXP_EXP08_FORCE_DAC_WAKE; 952 int ret; 953 954 if (phydev->state != PHY_RUNNING) 955 return; 956 957 /* Don't change the DAC wake settings if auto power down 958 * is not requested. 959 */ 960 if (!(phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE)) 961 return; 962 963 ret = bcm_phy_read_exp(phydev, MII_BCM54XX_EXP_EXP08); 964 if (ret < 0) 965 return; 966 967 /* Enable/disable 10BaseT auto and forced early DAC wake depending 968 * on the negotiated speed, those settings should only be done 969 * for 10Mbits/sec. 970 */ 971 if (phydev->speed == SPEED_10) 972 ret |= mask; 973 else 974 ret &= ~mask; 975 bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP08, ret); 976 } 977 978 static struct phy_driver broadcom_drivers[] = { 979 { 980 .phy_id = PHY_ID_BCM5411, 981 .phy_id_mask = 0xfffffff0, 982 .name = "Broadcom BCM5411", 983 /* PHY_GBIT_FEATURES */ 984 .get_sset_count = bcm_phy_get_sset_count, 985 .get_strings = bcm_phy_get_strings, 986 .get_stats = bcm54xx_get_stats, 987 .probe = bcm54xx_phy_probe, 988 .config_init = bcm54xx_config_init, 989 .config_intr = bcm_phy_config_intr, 990 .handle_interrupt = bcm_phy_handle_interrupt, 991 .link_change_notify = bcm54xx_link_change_notify, 992 }, { 993 .phy_id = PHY_ID_BCM5421, 994 .phy_id_mask = 0xfffffff0, 995 .name = "Broadcom BCM5421", 996 /* PHY_GBIT_FEATURES */ 997 .get_sset_count = bcm_phy_get_sset_count, 998 .get_strings = bcm_phy_get_strings, 999 .get_stats = bcm54xx_get_stats, 1000 .probe = bcm54xx_phy_probe, 1001 .config_init = bcm54xx_config_init, 1002 .config_intr = bcm_phy_config_intr, 1003 .handle_interrupt = bcm_phy_handle_interrupt, 1004 .link_change_notify = bcm54xx_link_change_notify, 1005 }, { 1006 .phy_id = PHY_ID_BCM54210E, 1007 .phy_id_mask = 0xfffffff0, 1008 .name = "Broadcom BCM54210E", 1009 /* PHY_GBIT_FEATURES */ 1010 .flags = PHY_ALWAYS_CALL_SUSPEND, 1011 .get_sset_count = bcm_phy_get_sset_count, 1012 .get_strings = bcm_phy_get_strings, 1013 .get_stats = bcm54xx_get_stats, 1014 .probe = bcm54xx_phy_probe, 1015 .config_init = bcm54xx_config_init, 1016 .config_intr = bcm_phy_config_intr, 1017 .handle_interrupt = bcm_phy_handle_interrupt, 1018 .link_change_notify = bcm54xx_link_change_notify, 1019 .suspend = bcm54xx_suspend, 1020 .resume = bcm54xx_resume, 1021 .get_wol = bcm54xx_phy_get_wol, 1022 .set_wol = bcm54xx_phy_set_wol, 1023 .led_brightness_set = bcm_phy_led_brightness_set, 1024 }, { 1025 .phy_id = PHY_ID_BCM5461, 1026 .phy_id_mask = 0xfffffff0, 1027 .name = "Broadcom BCM5461", 1028 /* PHY_GBIT_FEATURES */ 1029 .get_sset_count = bcm_phy_get_sset_count, 1030 .get_strings = bcm_phy_get_strings, 1031 .get_stats = bcm54xx_get_stats, 1032 .probe = bcm54xx_phy_probe, 1033 .config_init = bcm54xx_config_init, 1034 .config_intr = bcm_phy_config_intr, 1035 .handle_interrupt = bcm_phy_handle_interrupt, 1036 .link_change_notify = bcm54xx_link_change_notify, 1037 .led_brightness_set = bcm_phy_led_brightness_set, 1038 }, { 1039 .phy_id = PHY_ID_BCM54612E, 1040 .phy_id_mask = 0xfffffff0, 1041 .name = "Broadcom BCM54612E", 1042 /* PHY_GBIT_FEATURES */ 1043 .get_sset_count = bcm_phy_get_sset_count, 1044 .get_strings = bcm_phy_get_strings, 1045 .get_stats = bcm54xx_get_stats, 1046 .probe = bcm54xx_phy_probe, 1047 .config_init = bcm54xx_config_init, 1048 .config_intr = bcm_phy_config_intr, 1049 .handle_interrupt = bcm_phy_handle_interrupt, 1050 .link_change_notify = bcm54xx_link_change_notify, 1051 .led_brightness_set = bcm_phy_led_brightness_set, 1052 }, { 1053 .phy_id = PHY_ID_BCM54616S, 1054 .phy_id_mask = 0xfffffff0, 1055 .name = "Broadcom BCM54616S", 1056 /* PHY_GBIT_FEATURES */ 1057 .soft_reset = genphy_soft_reset, 1058 .config_init = bcm54xx_config_init, 1059 .config_aneg = bcm54616s_config_aneg, 1060 .config_intr = bcm_phy_config_intr, 1061 .handle_interrupt = bcm_phy_handle_interrupt, 1062 .read_status = bcm54616s_read_status, 1063 .probe = bcm54616s_probe, 1064 .link_change_notify = bcm54xx_link_change_notify, 1065 .led_brightness_set = bcm_phy_led_brightness_set, 1066 }, { 1067 .phy_id = PHY_ID_BCM5464, 1068 .phy_id_mask = 0xfffffff0, 1069 .name = "Broadcom BCM5464", 1070 /* PHY_GBIT_FEATURES */ 1071 .get_sset_count = bcm_phy_get_sset_count, 1072 .get_strings = bcm_phy_get_strings, 1073 .get_stats = bcm54xx_get_stats, 1074 .probe = bcm54xx_phy_probe, 1075 .config_init = bcm54xx_config_init, 1076 .config_intr = bcm_phy_config_intr, 1077 .handle_interrupt = bcm_phy_handle_interrupt, 1078 .suspend = genphy_suspend, 1079 .resume = genphy_resume, 1080 .link_change_notify = bcm54xx_link_change_notify, 1081 .led_brightness_set = bcm_phy_led_brightness_set, 1082 }, { 1083 .phy_id = PHY_ID_BCM5481, 1084 .phy_id_mask = 0xfffffff0, 1085 .name = "Broadcom BCM5481", 1086 /* PHY_GBIT_FEATURES */ 1087 .get_sset_count = bcm_phy_get_sset_count, 1088 .get_strings = bcm_phy_get_strings, 1089 .get_stats = bcm54xx_get_stats, 1090 .probe = bcm54xx_phy_probe, 1091 .config_init = bcm54xx_config_init, 1092 .config_aneg = bcm5481_config_aneg, 1093 .config_intr = bcm_phy_config_intr, 1094 .handle_interrupt = bcm_phy_handle_interrupt, 1095 .link_change_notify = bcm54xx_link_change_notify, 1096 .led_brightness_set = bcm_phy_led_brightness_set, 1097 }, { 1098 .phy_id = PHY_ID_BCM54810, 1099 .phy_id_mask = 0xfffffff0, 1100 .name = "Broadcom BCM54810", 1101 /* PHY_GBIT_FEATURES */ 1102 .get_sset_count = bcm_phy_get_sset_count, 1103 .get_strings = bcm_phy_get_strings, 1104 .get_stats = bcm54xx_get_stats, 1105 .probe = bcm54xx_phy_probe, 1106 .config_init = bcm54xx_config_init, 1107 .config_aneg = bcm5481_config_aneg, 1108 .config_intr = bcm_phy_config_intr, 1109 .handle_interrupt = bcm_phy_handle_interrupt, 1110 .suspend = bcm54xx_suspend, 1111 .resume = bcm54xx_resume, 1112 .link_change_notify = bcm54xx_link_change_notify, 1113 .led_brightness_set = bcm_phy_led_brightness_set, 1114 }, { 1115 .phy_id = PHY_ID_BCM54811, 1116 .phy_id_mask = 0xfffffff0, 1117 .name = "Broadcom BCM54811", 1118 /* PHY_GBIT_FEATURES */ 1119 .get_sset_count = bcm_phy_get_sset_count, 1120 .get_strings = bcm_phy_get_strings, 1121 .get_stats = bcm54xx_get_stats, 1122 .probe = bcm54xx_phy_probe, 1123 .config_init = bcm54811_config_init, 1124 .config_aneg = bcm5481_config_aneg, 1125 .config_intr = bcm_phy_config_intr, 1126 .handle_interrupt = bcm_phy_handle_interrupt, 1127 .suspend = bcm54xx_suspend, 1128 .resume = bcm54xx_resume, 1129 .link_change_notify = bcm54xx_link_change_notify, 1130 .led_brightness_set = bcm_phy_led_brightness_set, 1131 }, { 1132 .phy_id = PHY_ID_BCM5482, 1133 .phy_id_mask = 0xfffffff0, 1134 .name = "Broadcom BCM5482", 1135 /* PHY_GBIT_FEATURES */ 1136 .get_sset_count = bcm_phy_get_sset_count, 1137 .get_strings = bcm_phy_get_strings, 1138 .get_stats = bcm54xx_get_stats, 1139 .probe = bcm54xx_phy_probe, 1140 .config_init = bcm54xx_config_init, 1141 .config_intr = bcm_phy_config_intr, 1142 .handle_interrupt = bcm_phy_handle_interrupt, 1143 .link_change_notify = bcm54xx_link_change_notify, 1144 .led_brightness_set = bcm_phy_led_brightness_set, 1145 }, { 1146 .phy_id = PHY_ID_BCM50610, 1147 .phy_id_mask = 0xfffffff0, 1148 .name = "Broadcom BCM50610", 1149 /* PHY_GBIT_FEATURES */ 1150 .get_sset_count = bcm_phy_get_sset_count, 1151 .get_strings = bcm_phy_get_strings, 1152 .get_stats = bcm54xx_get_stats, 1153 .probe = bcm54xx_phy_probe, 1154 .config_init = bcm54xx_config_init, 1155 .config_intr = bcm_phy_config_intr, 1156 .handle_interrupt = bcm_phy_handle_interrupt, 1157 .link_change_notify = bcm54xx_link_change_notify, 1158 .suspend = bcm54xx_suspend, 1159 .resume = bcm54xx_resume, 1160 .led_brightness_set = bcm_phy_led_brightness_set, 1161 }, { 1162 .phy_id = PHY_ID_BCM50610M, 1163 .phy_id_mask = 0xfffffff0, 1164 .name = "Broadcom BCM50610M", 1165 /* PHY_GBIT_FEATURES */ 1166 .get_sset_count = bcm_phy_get_sset_count, 1167 .get_strings = bcm_phy_get_strings, 1168 .get_stats = bcm54xx_get_stats, 1169 .probe = bcm54xx_phy_probe, 1170 .config_init = bcm54xx_config_init, 1171 .config_intr = bcm_phy_config_intr, 1172 .handle_interrupt = bcm_phy_handle_interrupt, 1173 .link_change_notify = bcm54xx_link_change_notify, 1174 .suspend = bcm54xx_suspend, 1175 .resume = bcm54xx_resume, 1176 .led_brightness_set = bcm_phy_led_brightness_set, 1177 }, { 1178 .phy_id = PHY_ID_BCM57780, 1179 .phy_id_mask = 0xfffffff0, 1180 .name = "Broadcom BCM57780", 1181 /* PHY_GBIT_FEATURES */ 1182 .get_sset_count = bcm_phy_get_sset_count, 1183 .get_strings = bcm_phy_get_strings, 1184 .get_stats = bcm54xx_get_stats, 1185 .probe = bcm54xx_phy_probe, 1186 .config_init = bcm54xx_config_init, 1187 .config_intr = bcm_phy_config_intr, 1188 .handle_interrupt = bcm_phy_handle_interrupt, 1189 .link_change_notify = bcm54xx_link_change_notify, 1190 .led_brightness_set = bcm_phy_led_brightness_set, 1191 }, { 1192 .phy_id = PHY_ID_BCMAC131, 1193 .phy_id_mask = 0xfffffff0, 1194 .name = "Broadcom BCMAC131", 1195 /* PHY_BASIC_FEATURES */ 1196 .config_init = brcm_fet_config_init, 1197 .config_intr = brcm_fet_config_intr, 1198 .handle_interrupt = brcm_fet_handle_interrupt, 1199 .suspend = brcm_fet_suspend, 1200 .resume = brcm_fet_config_init, 1201 }, { 1202 .phy_id = PHY_ID_BCM5241, 1203 .phy_id_mask = 0xfffffff0, 1204 .name = "Broadcom BCM5241", 1205 /* PHY_BASIC_FEATURES */ 1206 .config_init = brcm_fet_config_init, 1207 .config_intr = brcm_fet_config_intr, 1208 .handle_interrupt = brcm_fet_handle_interrupt, 1209 .suspend = brcm_fet_suspend, 1210 .resume = brcm_fet_config_init, 1211 }, { 1212 .phy_id = PHY_ID_BCM5395, 1213 .phy_id_mask = 0xfffffff0, 1214 .name = "Broadcom BCM5395", 1215 .flags = PHY_IS_INTERNAL, 1216 /* PHY_GBIT_FEATURES */ 1217 .get_sset_count = bcm_phy_get_sset_count, 1218 .get_strings = bcm_phy_get_strings, 1219 .get_stats = bcm54xx_get_stats, 1220 .probe = bcm54xx_phy_probe, 1221 .link_change_notify = bcm54xx_link_change_notify, 1222 .led_brightness_set = bcm_phy_led_brightness_set, 1223 }, { 1224 .phy_id = PHY_ID_BCM53125, 1225 .phy_id_mask = 0xfffffff0, 1226 .name = "Broadcom BCM53125", 1227 .flags = PHY_IS_INTERNAL, 1228 /* PHY_GBIT_FEATURES */ 1229 .get_sset_count = bcm_phy_get_sset_count, 1230 .get_strings = bcm_phy_get_strings, 1231 .get_stats = bcm54xx_get_stats, 1232 .probe = bcm54xx_phy_probe, 1233 .config_init = bcm54xx_config_init, 1234 .config_intr = bcm_phy_config_intr, 1235 .handle_interrupt = bcm_phy_handle_interrupt, 1236 .link_change_notify = bcm54xx_link_change_notify, 1237 .led_brightness_set = bcm_phy_led_brightness_set, 1238 }, { 1239 .phy_id = PHY_ID_BCM53128, 1240 .phy_id_mask = 0xfffffff0, 1241 .name = "Broadcom BCM53128", 1242 .flags = PHY_IS_INTERNAL, 1243 /* PHY_GBIT_FEATURES */ 1244 .get_sset_count = bcm_phy_get_sset_count, 1245 .get_strings = bcm_phy_get_strings, 1246 .get_stats = bcm54xx_get_stats, 1247 .probe = bcm54xx_phy_probe, 1248 .config_init = bcm54xx_config_init, 1249 .config_intr = bcm_phy_config_intr, 1250 .handle_interrupt = bcm_phy_handle_interrupt, 1251 .link_change_notify = bcm54xx_link_change_notify, 1252 .led_brightness_set = bcm_phy_led_brightness_set, 1253 }, { 1254 .phy_id = PHY_ID_BCM89610, 1255 .phy_id_mask = 0xfffffff0, 1256 .name = "Broadcom BCM89610", 1257 /* PHY_GBIT_FEATURES */ 1258 .get_sset_count = bcm_phy_get_sset_count, 1259 .get_strings = bcm_phy_get_strings, 1260 .get_stats = bcm54xx_get_stats, 1261 .probe = bcm54xx_phy_probe, 1262 .config_init = bcm54xx_config_init, 1263 .config_intr = bcm_phy_config_intr, 1264 .handle_interrupt = bcm_phy_handle_interrupt, 1265 .link_change_notify = bcm54xx_link_change_notify, 1266 } }; 1267 1268 module_phy_driver(broadcom_drivers); 1269 1270 static struct mdio_device_id __maybe_unused broadcom_tbl[] = { 1271 { PHY_ID_BCM5411, 0xfffffff0 }, 1272 { PHY_ID_BCM5421, 0xfffffff0 }, 1273 { PHY_ID_BCM54210E, 0xfffffff0 }, 1274 { PHY_ID_BCM5461, 0xfffffff0 }, 1275 { PHY_ID_BCM54612E, 0xfffffff0 }, 1276 { PHY_ID_BCM54616S, 0xfffffff0 }, 1277 { PHY_ID_BCM5464, 0xfffffff0 }, 1278 { PHY_ID_BCM5481, 0xfffffff0 }, 1279 { PHY_ID_BCM54810, 0xfffffff0 }, 1280 { PHY_ID_BCM54811, 0xfffffff0 }, 1281 { PHY_ID_BCM5482, 0xfffffff0 }, 1282 { PHY_ID_BCM50610, 0xfffffff0 }, 1283 { PHY_ID_BCM50610M, 0xfffffff0 }, 1284 { PHY_ID_BCM57780, 0xfffffff0 }, 1285 { PHY_ID_BCMAC131, 0xfffffff0 }, 1286 { PHY_ID_BCM5241, 0xfffffff0 }, 1287 { PHY_ID_BCM5395, 0xfffffff0 }, 1288 { PHY_ID_BCM53125, 0xfffffff0 }, 1289 { PHY_ID_BCM53128, 0xfffffff0 }, 1290 { PHY_ID_BCM89610, 0xfffffff0 }, 1291 { } 1292 }; 1293 1294 MODULE_DEVICE_TABLE(mdio, broadcom_tbl); 1295