1 /* 2 * Broadcom BCM7xxx internal transceivers support. 3 * 4 * Copyright (C) 2014, Broadcom Corporation 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or (at your option) any later version. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/phy.h> 14 #include <linux/delay.h> 15 #include "bcm-phy-lib.h" 16 #include <linux/bitops.h> 17 #include <linux/brcmphy.h> 18 #include <linux/mdio.h> 19 20 /* Broadcom BCM7xxx internal PHY registers */ 21 22 /* 40nm only register definitions */ 23 #define MII_BCM7XXX_100TX_AUX_CTL 0x10 24 #define MII_BCM7XXX_100TX_FALSE_CAR 0x13 25 #define MII_BCM7XXX_100TX_DISC 0x14 26 #define MII_BCM7XXX_AUX_MODE 0x1d 27 #define MII_BCM7XX_64CLK_MDIO BIT(12) 28 #define MII_BCM7XXX_TEST 0x1f 29 #define MII_BCM7XXX_SHD_MODE_2 BIT(2) 30 31 /* 28nm only register definitions */ 32 #define MISC_ADDR(base, channel) base, channel 33 34 #define DSP_TAP10 MISC_ADDR(0x0a, 0) 35 #define PLL_PLLCTRL_1 MISC_ADDR(0x32, 1) 36 #define PLL_PLLCTRL_2 MISC_ADDR(0x32, 2) 37 #define PLL_PLLCTRL_4 MISC_ADDR(0x33, 0) 38 39 #define AFE_RXCONFIG_0 MISC_ADDR(0x38, 0) 40 #define AFE_RXCONFIG_1 MISC_ADDR(0x38, 1) 41 #define AFE_RXCONFIG_2 MISC_ADDR(0x38, 2) 42 #define AFE_RX_LP_COUNTER MISC_ADDR(0x38, 3) 43 #define AFE_TX_CONFIG MISC_ADDR(0x39, 0) 44 #define AFE_VDCA_ICTRL_0 MISC_ADDR(0x39, 1) 45 #define AFE_VDAC_OTHERS_0 MISC_ADDR(0x39, 3) 46 #define AFE_HPF_TRIM_OTHERS MISC_ADDR(0x3a, 0) 47 48 static void r_rc_cal_reset(struct phy_device *phydev) 49 { 50 /* Reset R_CAL/RC_CAL Engine */ 51 bcm_phy_write_exp(phydev, 0x00b0, 0x0010); 52 53 /* Disable Reset R_AL/RC_CAL Engine */ 54 bcm_phy_write_exp(phydev, 0x00b0, 0x0000); 55 } 56 57 static int bcm7xxx_28nm_b0_afe_config_init(struct phy_device *phydev) 58 { 59 /* Increase VCO range to prevent unlocking problem of PLL at low 60 * temp 61 */ 62 bcm_phy_write_misc(phydev, PLL_PLLCTRL_1, 0x0048); 63 64 /* Change Ki to 011 */ 65 bcm_phy_write_misc(phydev, PLL_PLLCTRL_2, 0x021b); 66 67 /* Disable loading of TVCO buffer to bandgap, set bandgap trim 68 * to 111 69 */ 70 bcm_phy_write_misc(phydev, PLL_PLLCTRL_4, 0x0e20); 71 72 /* Adjust bias current trim by -3 */ 73 bcm_phy_write_misc(phydev, DSP_TAP10, 0x690b); 74 75 /* Switch to CORE_BASE1E */ 76 phy_write(phydev, MII_BRCM_CORE_BASE1E, 0xd); 77 78 r_rc_cal_reset(phydev); 79 80 /* write AFE_RXCONFIG_0 */ 81 bcm_phy_write_misc(phydev, AFE_RXCONFIG_0, 0xeb19); 82 83 /* write AFE_RXCONFIG_1 */ 84 bcm_phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9a3f); 85 86 /* write AFE_RX_LP_COUNTER */ 87 bcm_phy_write_misc(phydev, AFE_RX_LP_COUNTER, 0x7fc0); 88 89 /* write AFE_HPF_TRIM_OTHERS */ 90 bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x000b); 91 92 /* write AFTE_TX_CONFIG */ 93 bcm_phy_write_misc(phydev, AFE_TX_CONFIG, 0x0800); 94 95 return 0; 96 } 97 98 static int bcm7xxx_28nm_d0_afe_config_init(struct phy_device *phydev) 99 { 100 /* AFE_RXCONFIG_0 */ 101 bcm_phy_write_misc(phydev, AFE_RXCONFIG_0, 0xeb15); 102 103 /* AFE_RXCONFIG_1 */ 104 bcm_phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9b2f); 105 106 /* AFE_RXCONFIG_2, set rCal offset for HT=0 code and LT=-2 code */ 107 bcm_phy_write_misc(phydev, AFE_RXCONFIG_2, 0x2003); 108 109 /* AFE_RX_LP_COUNTER, set RX bandwidth to maximum */ 110 bcm_phy_write_misc(phydev, AFE_RX_LP_COUNTER, 0x7fc0); 111 112 /* AFE_TX_CONFIG, set 100BT Cfeed=011 to improve rise/fall time */ 113 bcm_phy_write_misc(phydev, AFE_TX_CONFIG, 0x431); 114 115 /* AFE_VDCA_ICTRL_0, set Iq=1101 instead of 0111 for AB symmetry */ 116 bcm_phy_write_misc(phydev, AFE_VDCA_ICTRL_0, 0xa7da); 117 118 /* AFE_VDAC_OTHERS_0, set 1000BT Cidac=010 for all ports */ 119 bcm_phy_write_misc(phydev, AFE_VDAC_OTHERS_0, 0xa020); 120 121 /* AFE_HPF_TRIM_OTHERS, set 100Tx/10BT to -4.5% swing and set rCal 122 * offset for HT=0 code 123 */ 124 bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x00e3); 125 126 /* CORE_BASE1E, force trim to overwrite and set I_ext trim to 0000 */ 127 phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010); 128 129 /* DSP_TAP10, adjust bias current trim (+0% swing, +0 tick) */ 130 bcm_phy_write_misc(phydev, DSP_TAP10, 0x011b); 131 132 /* Reset R_CAL/RC_CAL engine */ 133 r_rc_cal_reset(phydev); 134 135 return 0; 136 } 137 138 static int bcm7xxx_28nm_e0_plus_afe_config_init(struct phy_device *phydev) 139 { 140 /* AFE_RXCONFIG_1, provide more margin for INL/DNL measurement */ 141 bcm_phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9b2f); 142 143 /* AFE_TX_CONFIG, set 100BT Cfeed=011 to improve rise/fall time */ 144 bcm_phy_write_misc(phydev, AFE_TX_CONFIG, 0x431); 145 146 /* AFE_VDCA_ICTRL_0, set Iq=1101 instead of 0111 for AB symmetry */ 147 bcm_phy_write_misc(phydev, AFE_VDCA_ICTRL_0, 0xa7da); 148 149 /* AFE_HPF_TRIM_OTHERS, set 100Tx/10BT to -4.5% swing and set rCal 150 * offset for HT=0 code 151 */ 152 bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x00e3); 153 154 /* CORE_BASE1E, force trim to overwrite and set I_ext trim to 0000 */ 155 phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010); 156 157 /* DSP_TAP10, adjust bias current trim (+0% swing, +0 tick) */ 158 bcm_phy_write_misc(phydev, DSP_TAP10, 0x011b); 159 160 /* Reset R_CAL/RC_CAL engine */ 161 r_rc_cal_reset(phydev); 162 163 return 0; 164 } 165 166 static int bcm7xxx_28nm_config_init(struct phy_device *phydev) 167 { 168 u8 rev = PHY_BRCM_7XXX_REV(phydev->dev_flags); 169 u8 patch = PHY_BRCM_7XXX_PATCH(phydev->dev_flags); 170 int ret = 0; 171 172 pr_info_once("%s: %s PHY revision: 0x%02x, patch: %d\n", 173 phydev_name(phydev), phydev->drv->name, rev, patch); 174 175 /* Dummy read to a register to workaround an issue upon reset where the 176 * internal inverter may not allow the first MDIO transaction to pass 177 * the MDIO management controller and make us return 0xffff for such 178 * reads. 179 */ 180 phy_read(phydev, MII_BMSR); 181 182 switch (rev) { 183 case 0xb0: 184 ret = bcm7xxx_28nm_b0_afe_config_init(phydev); 185 break; 186 case 0xd0: 187 ret = bcm7xxx_28nm_d0_afe_config_init(phydev); 188 break; 189 case 0xe0: 190 case 0xf0: 191 /* Rev G0 introduces a roll over */ 192 case 0x10: 193 ret = bcm7xxx_28nm_e0_plus_afe_config_init(phydev); 194 break; 195 default: 196 break; 197 } 198 199 if (ret) 200 return ret; 201 202 ret = bcm_phy_enable_eee(phydev); 203 if (ret) 204 return ret; 205 206 return bcm_phy_enable_apd(phydev, true); 207 } 208 209 static int bcm7xxx_28nm_resume(struct phy_device *phydev) 210 { 211 int ret; 212 213 /* Re-apply workarounds coming out suspend/resume */ 214 ret = bcm7xxx_28nm_config_init(phydev); 215 if (ret) 216 return ret; 217 218 /* 28nm Gigabit PHYs come out of reset without any half-duplex 219 * or "hub" compliant advertised mode, fix that. This does not 220 * cause any problems with the PHY library since genphy_config_aneg() 221 * gracefully handles auto-negotiated and forced modes. 222 */ 223 return genphy_config_aneg(phydev); 224 } 225 226 static int phy_set_clr_bits(struct phy_device *dev, int location, 227 int set_mask, int clr_mask) 228 { 229 int v, ret; 230 231 v = phy_read(dev, location); 232 if (v < 0) 233 return v; 234 235 v &= ~clr_mask; 236 v |= set_mask; 237 238 ret = phy_write(dev, location, v); 239 if (ret < 0) 240 return ret; 241 242 return v; 243 } 244 245 static int bcm7xxx_config_init(struct phy_device *phydev) 246 { 247 int ret; 248 249 /* Enable 64 clock MDIO */ 250 phy_write(phydev, MII_BCM7XXX_AUX_MODE, MII_BCM7XX_64CLK_MDIO); 251 phy_read(phydev, MII_BCM7XXX_AUX_MODE); 252 253 /* Workaround only required for 100Mbits/sec capable PHYs */ 254 if (phydev->supported & PHY_GBIT_FEATURES) 255 return 0; 256 257 /* set shadow mode 2 */ 258 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 259 MII_BCM7XXX_SHD_MODE_2, MII_BCM7XXX_SHD_MODE_2); 260 if (ret < 0) 261 return ret; 262 263 /* set iddq_clkbias */ 264 phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0F00); 265 udelay(10); 266 267 /* reset iddq_clkbias */ 268 phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0C00); 269 270 phy_write(phydev, MII_BCM7XXX_100TX_FALSE_CAR, 0x7555); 271 272 /* reset shadow mode 2 */ 273 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, MII_BCM7XXX_SHD_MODE_2, 0); 274 if (ret < 0) 275 return ret; 276 277 return 0; 278 } 279 280 /* Workaround for putting the PHY in IDDQ mode, required 281 * for all BCM7XXX 40nm and 65nm PHYs 282 */ 283 static int bcm7xxx_suspend(struct phy_device *phydev) 284 { 285 int ret; 286 const struct bcm7xxx_regs { 287 int reg; 288 u16 value; 289 } bcm7xxx_suspend_cfg[] = { 290 { MII_BCM7XXX_TEST, 0x008b }, 291 { MII_BCM7XXX_100TX_AUX_CTL, 0x01c0 }, 292 { MII_BCM7XXX_100TX_DISC, 0x7000 }, 293 { MII_BCM7XXX_TEST, 0x000f }, 294 { MII_BCM7XXX_100TX_AUX_CTL, 0x20d0 }, 295 { MII_BCM7XXX_TEST, 0x000b }, 296 }; 297 unsigned int i; 298 299 for (i = 0; i < ARRAY_SIZE(bcm7xxx_suspend_cfg); i++) { 300 ret = phy_write(phydev, 301 bcm7xxx_suspend_cfg[i].reg, 302 bcm7xxx_suspend_cfg[i].value); 303 if (ret) 304 return ret; 305 } 306 307 return 0; 308 } 309 310 static int bcm7xxx_dummy_config_init(struct phy_device *phydev) 311 { 312 return 0; 313 } 314 315 #define BCM7XXX_28NM_GPHY(_oui, _name) \ 316 { \ 317 .phy_id = (_oui), \ 318 .phy_id_mask = 0xfffffff0, \ 319 .name = _name, \ 320 .features = PHY_GBIT_FEATURES | \ 321 SUPPORTED_Pause | SUPPORTED_Asym_Pause, \ 322 .flags = PHY_IS_INTERNAL, \ 323 .config_init = bcm7xxx_28nm_config_init, \ 324 .config_aneg = genphy_config_aneg, \ 325 .read_status = genphy_read_status, \ 326 .resume = bcm7xxx_28nm_resume, \ 327 } 328 329 static struct phy_driver bcm7xxx_driver[] = { 330 BCM7XXX_28NM_GPHY(PHY_ID_BCM7250, "Broadcom BCM7250"), 331 BCM7XXX_28NM_GPHY(PHY_ID_BCM7364, "Broadcom BCM7364"), 332 BCM7XXX_28NM_GPHY(PHY_ID_BCM7366, "Broadcom BCM7366"), 333 BCM7XXX_28NM_GPHY(PHY_ID_BCM7439, "Broadcom BCM7439"), 334 BCM7XXX_28NM_GPHY(PHY_ID_BCM7439_2, "Broadcom BCM7439 (2)"), 335 BCM7XXX_28NM_GPHY(PHY_ID_BCM7445, "Broadcom BCM7445"), 336 { 337 .phy_id = PHY_ID_BCM7425, 338 .phy_id_mask = 0xfffffff0, 339 .name = "Broadcom BCM7425", 340 .features = PHY_GBIT_FEATURES | 341 SUPPORTED_Pause | SUPPORTED_Asym_Pause, 342 .flags = PHY_IS_INTERNAL, 343 .config_init = bcm7xxx_config_init, 344 .config_aneg = genphy_config_aneg, 345 .read_status = genphy_read_status, 346 .suspend = bcm7xxx_suspend, 347 .resume = bcm7xxx_config_init, 348 }, { 349 .phy_id = PHY_ID_BCM7429, 350 .phy_id_mask = 0xfffffff0, 351 .name = "Broadcom BCM7429", 352 .features = PHY_GBIT_FEATURES | 353 SUPPORTED_Pause | SUPPORTED_Asym_Pause, 354 .flags = PHY_IS_INTERNAL, 355 .config_init = bcm7xxx_config_init, 356 .config_aneg = genphy_config_aneg, 357 .read_status = genphy_read_status, 358 .suspend = bcm7xxx_suspend, 359 .resume = bcm7xxx_config_init, 360 }, { 361 .phy_id = PHY_ID_BCM7435, 362 .phy_id_mask = 0xfffffff0, 363 .name = "Broadcom BCM7435", 364 .features = PHY_GBIT_FEATURES | 365 SUPPORTED_Pause | SUPPORTED_Asym_Pause, 366 .flags = PHY_IS_INTERNAL, 367 .config_init = bcm7xxx_config_init, 368 .config_aneg = genphy_config_aneg, 369 .read_status = genphy_read_status, 370 .suspend = bcm7xxx_suspend, 371 .resume = bcm7xxx_config_init, 372 }, { 373 .phy_id = PHY_BCM_OUI_4, 374 .phy_id_mask = 0xffff0000, 375 .name = "Broadcom BCM7XXX 40nm", 376 .features = PHY_GBIT_FEATURES | 377 SUPPORTED_Pause | SUPPORTED_Asym_Pause, 378 .flags = PHY_IS_INTERNAL, 379 .config_init = bcm7xxx_config_init, 380 .config_aneg = genphy_config_aneg, 381 .read_status = genphy_read_status, 382 .suspend = bcm7xxx_suspend, 383 .resume = bcm7xxx_config_init, 384 }, { 385 .phy_id = PHY_BCM_OUI_5, 386 .phy_id_mask = 0xffffff00, 387 .name = "Broadcom BCM7XXX 65nm", 388 .features = PHY_BASIC_FEATURES | 389 SUPPORTED_Pause | SUPPORTED_Asym_Pause, 390 .flags = PHY_IS_INTERNAL, 391 .config_init = bcm7xxx_dummy_config_init, 392 .config_aneg = genphy_config_aneg, 393 .read_status = genphy_read_status, 394 .suspend = bcm7xxx_suspend, 395 .resume = bcm7xxx_config_init, 396 } }; 397 398 static struct mdio_device_id __maybe_unused bcm7xxx_tbl[] = { 399 { PHY_ID_BCM7250, 0xfffffff0, }, 400 { PHY_ID_BCM7364, 0xfffffff0, }, 401 { PHY_ID_BCM7366, 0xfffffff0, }, 402 { PHY_ID_BCM7425, 0xfffffff0, }, 403 { PHY_ID_BCM7429, 0xfffffff0, }, 404 { PHY_ID_BCM7439, 0xfffffff0, }, 405 { PHY_ID_BCM7435, 0xfffffff0, }, 406 { PHY_ID_BCM7445, 0xfffffff0, }, 407 { PHY_BCM_OUI_4, 0xffff0000 }, 408 { PHY_BCM_OUI_5, 0xffffff00 }, 409 { } 410 }; 411 412 module_phy_driver(bcm7xxx_driver); 413 414 MODULE_DEVICE_TABLE(mdio, bcm7xxx_tbl); 415 416 MODULE_DESCRIPTION("Broadcom BCM7xxx internal PHY driver"); 417 MODULE_LICENSE("GPL"); 418 MODULE_AUTHOR("Broadcom Corporation"); 419