16937602eSMichael Walle // SPDX-License-Identifier: GPL-2.0+ 26937602eSMichael Walle /* Broadcom BCM54140 Quad SGMII/QSGMII Copper/Fiber Gigabit PHY 36937602eSMichael Walle * 46937602eSMichael Walle * Copyright (c) 2020 Michael Walle <michael@walle.cc> 56937602eSMichael Walle */ 66937602eSMichael Walle 76937602eSMichael Walle #include <linux/bitfield.h> 86937602eSMichael Walle #include <linux/brcmphy.h> 94406d36dSMichael Walle #include <linux/hwmon.h> 106937602eSMichael Walle #include <linux/module.h> 116937602eSMichael Walle #include <linux/phy.h> 126937602eSMichael Walle 136937602eSMichael Walle #include "bcm-phy-lib.h" 146937602eSMichael Walle 156937602eSMichael Walle /* RDB per-port registers 166937602eSMichael Walle */ 176937602eSMichael Walle #define BCM54140_RDB_ISR 0x00a /* interrupt status */ 186937602eSMichael Walle #define BCM54140_RDB_IMR 0x00b /* interrupt mask */ 196937602eSMichael Walle #define BCM54140_RDB_INT_LINK BIT(1) /* link status changed */ 206937602eSMichael Walle #define BCM54140_RDB_INT_SPEED BIT(2) /* link speed change */ 216937602eSMichael Walle #define BCM54140_RDB_INT_DUPLEX BIT(3) /* duplex mode changed */ 226937602eSMichael Walle #define BCM54140_RDB_SPARE1 0x012 /* spare control 1 */ 236937602eSMichael Walle #define BCM54140_RDB_SPARE1_LSLM BIT(2) /* link speed LED mode */ 246937602eSMichael Walle #define BCM54140_RDB_SPARE2 0x014 /* spare control 2 */ 256937602eSMichael Walle #define BCM54140_RDB_SPARE2_WS_RTRY_DIS BIT(8) /* wirespeed retry disable */ 266937602eSMichael Walle #define BCM54140_RDB_SPARE2_WS_RTRY_LIMIT GENMASK(4, 2) /* retry limit */ 276937602eSMichael Walle #define BCM54140_RDB_SPARE3 0x015 /* spare control 3 */ 286937602eSMichael Walle #define BCM54140_RDB_SPARE3_BIT0 BIT(0) 296937602eSMichael Walle #define BCM54140_RDB_LED_CTRL 0x019 /* LED control */ 306937602eSMichael Walle #define BCM54140_RDB_LED_CTRL_ACTLINK0 BIT(4) 316937602eSMichael Walle #define BCM54140_RDB_LED_CTRL_ACTLINK1 BIT(8) 326937602eSMichael Walle #define BCM54140_RDB_C_APWR 0x01a /* auto power down control */ 336937602eSMichael Walle #define BCM54140_RDB_C_APWR_SINGLE_PULSE BIT(8) /* single pulse */ 346937602eSMichael Walle #define BCM54140_RDB_C_APWR_APD_MODE_DIS 0 /* ADP disable */ 356937602eSMichael Walle #define BCM54140_RDB_C_APWR_APD_MODE_EN 1 /* ADP enable */ 366937602eSMichael Walle #define BCM54140_RDB_C_APWR_APD_MODE_DIS2 2 /* ADP disable */ 376937602eSMichael Walle #define BCM54140_RDB_C_APWR_APD_MODE_EN_ANEG 3 /* ADP enable w/ aneg */ 386937602eSMichael Walle #define BCM54140_RDB_C_APWR_APD_MODE_MASK GENMASK(6, 5) 396937602eSMichael Walle #define BCM54140_RDB_C_APWR_SLP_TIM_MASK BIT(4)/* sleep timer */ 406937602eSMichael Walle #define BCM54140_RDB_C_APWR_SLP_TIM_2_7 0 /* 2.7s */ 416937602eSMichael Walle #define BCM54140_RDB_C_APWR_SLP_TIM_5_4 1 /* 5.4s */ 426937602eSMichael Walle #define BCM54140_RDB_C_PWR 0x02a /* copper power control */ 436937602eSMichael Walle #define BCM54140_RDB_C_PWR_ISOLATE BIT(5) /* super isolate mode */ 446937602eSMichael Walle #define BCM54140_RDB_C_MISC_CTRL 0x02f /* misc copper control */ 456937602eSMichael Walle #define BCM54140_RDB_C_MISC_CTRL_WS_EN BIT(4) /* wirespeed enable */ 466937602eSMichael Walle 476937602eSMichael Walle /* RDB global registers 486937602eSMichael Walle */ 496937602eSMichael Walle #define BCM54140_RDB_TOP_IMR 0x82d /* interrupt mask */ 506937602eSMichael Walle #define BCM54140_RDB_TOP_IMR_PORT0 BIT(4) 516937602eSMichael Walle #define BCM54140_RDB_TOP_IMR_PORT1 BIT(5) 526937602eSMichael Walle #define BCM54140_RDB_TOP_IMR_PORT2 BIT(6) 536937602eSMichael Walle #define BCM54140_RDB_TOP_IMR_PORT3 BIT(7) 544406d36dSMichael Walle #define BCM54140_RDB_MON_CTRL 0x831 /* monitor control */ 554406d36dSMichael Walle #define BCM54140_RDB_MON_CTRL_V_MODE BIT(3) /* voltage mode */ 564406d36dSMichael Walle #define BCM54140_RDB_MON_CTRL_SEL_MASK GENMASK(2, 1) 574406d36dSMichael Walle #define BCM54140_RDB_MON_CTRL_SEL_TEMP 0 /* meassure temperature */ 584406d36dSMichael Walle #define BCM54140_RDB_MON_CTRL_SEL_1V0 1 /* meassure AVDDL 1.0V */ 594406d36dSMichael Walle #define BCM54140_RDB_MON_CTRL_SEL_3V3 2 /* meassure AVDDH 3.3V */ 604406d36dSMichael Walle #define BCM54140_RDB_MON_CTRL_SEL_RR 3 /* meassure all round-robin */ 614406d36dSMichael Walle #define BCM54140_RDB_MON_CTRL_PWR_DOWN BIT(0) /* power-down monitor */ 624406d36dSMichael Walle #define BCM54140_RDB_MON_TEMP_VAL 0x832 /* temperature value */ 634406d36dSMichael Walle #define BCM54140_RDB_MON_TEMP_MAX 0x833 /* temperature high thresh */ 644406d36dSMichael Walle #define BCM54140_RDB_MON_TEMP_MIN 0x834 /* temperature low thresh */ 654406d36dSMichael Walle #define BCM54140_RDB_MON_TEMP_DATA_MASK GENMASK(9, 0) 664406d36dSMichael Walle #define BCM54140_RDB_MON_1V0_VAL 0x835 /* AVDDL 1.0V value */ 674406d36dSMichael Walle #define BCM54140_RDB_MON_1V0_MAX 0x836 /* AVDDL 1.0V high thresh */ 684406d36dSMichael Walle #define BCM54140_RDB_MON_1V0_MIN 0x837 /* AVDDL 1.0V low thresh */ 694406d36dSMichael Walle #define BCM54140_RDB_MON_1V0_DATA_MASK GENMASK(10, 0) 704406d36dSMichael Walle #define BCM54140_RDB_MON_3V3_VAL 0x838 /* AVDDH 3.3V value */ 714406d36dSMichael Walle #define BCM54140_RDB_MON_3V3_MAX 0x839 /* AVDDH 3.3V high thresh */ 724406d36dSMichael Walle #define BCM54140_RDB_MON_3V3_MIN 0x83a /* AVDDH 3.3V low thresh */ 734406d36dSMichael Walle #define BCM54140_RDB_MON_3V3_DATA_MASK GENMASK(11, 0) 744406d36dSMichael Walle #define BCM54140_RDB_MON_ISR 0x83b /* interrupt status */ 754406d36dSMichael Walle #define BCM54140_RDB_MON_ISR_3V3 BIT(2) /* AVDDH 3.3V alarm */ 764406d36dSMichael Walle #define BCM54140_RDB_MON_ISR_1V0 BIT(1) /* AVDDL 1.0V alarm */ 774406d36dSMichael Walle #define BCM54140_RDB_MON_ISR_TEMP BIT(0) /* temperature alarm */ 784406d36dSMichael Walle 794406d36dSMichael Walle /* According to the datasheet the formula is: 804406d36dSMichael Walle * T = 413.35 - (0.49055 * bits[9:0]) 814406d36dSMichael Walle */ 824406d36dSMichael Walle #define BCM54140_HWMON_TO_TEMP(v) (413350L - (v) * 491) 834406d36dSMichael Walle #define BCM54140_HWMON_FROM_TEMP(v) DIV_ROUND_CLOSEST_ULL(413350L - (v), 491) 844406d36dSMichael Walle 854406d36dSMichael Walle /* According to the datasheet the formula is: 864406d36dSMichael Walle * U = bits[11:0] / 1024 * 220 / 0.2 874406d36dSMichael Walle * 884406d36dSMichael Walle * Normalized: 894406d36dSMichael Walle * U = bits[11:0] / 4096 * 2514 904406d36dSMichael Walle */ 914406d36dSMichael Walle #define BCM54140_HWMON_TO_IN_1V0(v) ((v) * 2514 >> 11) 924406d36dSMichael Walle #define BCM54140_HWMON_FROM_IN_1V0(v) DIV_ROUND_CLOSEST_ULL(((v) << 11), 2514) 934406d36dSMichael Walle 944406d36dSMichael Walle /* According to the datasheet the formula is: 954406d36dSMichael Walle * U = bits[10:0] / 1024 * 880 / 0.7 964406d36dSMichael Walle * 974406d36dSMichael Walle * Normalized: 984406d36dSMichael Walle * U = bits[10:0] / 2048 * 4400 994406d36dSMichael Walle */ 1004406d36dSMichael Walle #define BCM54140_HWMON_TO_IN_3V3(v) ((v) * 4400 >> 12) 1014406d36dSMichael Walle #define BCM54140_HWMON_FROM_IN_3V3(v) DIV_ROUND_CLOSEST_ULL(((v) << 12), 4400) 1024406d36dSMichael Walle 1034406d36dSMichael Walle #define BCM54140_HWMON_TO_IN(ch, v) ((ch) ? BCM54140_HWMON_TO_IN_3V3(v) \ 1044406d36dSMichael Walle : BCM54140_HWMON_TO_IN_1V0(v)) 1054406d36dSMichael Walle #define BCM54140_HWMON_FROM_IN(ch, v) ((ch) ? BCM54140_HWMON_FROM_IN_3V3(v) \ 1064406d36dSMichael Walle : BCM54140_HWMON_FROM_IN_1V0(v)) 1074406d36dSMichael Walle #define BCM54140_HWMON_IN_MASK(ch) ((ch) ? BCM54140_RDB_MON_3V3_DATA_MASK \ 1084406d36dSMichael Walle : BCM54140_RDB_MON_1V0_DATA_MASK) 1094406d36dSMichael Walle #define BCM54140_HWMON_IN_VAL_REG(ch) ((ch) ? BCM54140_RDB_MON_3V3_VAL \ 1104406d36dSMichael Walle : BCM54140_RDB_MON_1V0_VAL) 1114406d36dSMichael Walle #define BCM54140_HWMON_IN_MIN_REG(ch) ((ch) ? BCM54140_RDB_MON_3V3_MIN \ 1124406d36dSMichael Walle : BCM54140_RDB_MON_1V0_MIN) 1134406d36dSMichael Walle #define BCM54140_HWMON_IN_MAX_REG(ch) ((ch) ? BCM54140_RDB_MON_3V3_MAX \ 1144406d36dSMichael Walle : BCM54140_RDB_MON_1V0_MAX) 1154406d36dSMichael Walle #define BCM54140_HWMON_IN_ALARM_BIT(ch) ((ch) ? BCM54140_RDB_MON_ISR_3V3 \ 1164406d36dSMichael Walle : BCM54140_RDB_MON_ISR_1V0) 1176937602eSMichael Walle 1186937602eSMichael Walle #define BCM54140_DEFAULT_DOWNSHIFT 5 1196937602eSMichael Walle #define BCM54140_MAX_DOWNSHIFT 9 1206937602eSMichael Walle 1216937602eSMichael Walle struct bcm54140_priv { 1226937602eSMichael Walle int port; 1236937602eSMichael Walle int base_addr; 1244406d36dSMichael Walle #if IS_ENABLED(CONFIG_HWMON) 1254406d36dSMichael Walle bool pkg_init; 1264406d36dSMichael Walle /* protect the alarm bits */ 1274406d36dSMichael Walle struct mutex alarm_lock; 1284406d36dSMichael Walle u16 alarm; 1294406d36dSMichael Walle #endif 1306937602eSMichael Walle }; 1316937602eSMichael Walle 1324406d36dSMichael Walle #if IS_ENABLED(CONFIG_HWMON) 1334406d36dSMichael Walle static umode_t bcm54140_hwmon_is_visible(const void *data, 1344406d36dSMichael Walle enum hwmon_sensor_types type, 1354406d36dSMichael Walle u32 attr, int channel) 1364406d36dSMichael Walle { 1374406d36dSMichael Walle switch (type) { 1384406d36dSMichael Walle case hwmon_in: 1394406d36dSMichael Walle switch (attr) { 1404406d36dSMichael Walle case hwmon_in_min: 1414406d36dSMichael Walle case hwmon_in_max: 1424406d36dSMichael Walle return 0644; 1434406d36dSMichael Walle case hwmon_in_label: 1444406d36dSMichael Walle case hwmon_in_input: 1454406d36dSMichael Walle case hwmon_in_alarm: 1464406d36dSMichael Walle return 0444; 1474406d36dSMichael Walle default: 1484406d36dSMichael Walle return 0; 1494406d36dSMichael Walle } 1504406d36dSMichael Walle case hwmon_temp: 1514406d36dSMichael Walle switch (attr) { 1524406d36dSMichael Walle case hwmon_temp_min: 1534406d36dSMichael Walle case hwmon_temp_max: 1544406d36dSMichael Walle return 0644; 1554406d36dSMichael Walle case hwmon_temp_input: 1564406d36dSMichael Walle case hwmon_temp_alarm: 1574406d36dSMichael Walle return 0444; 1584406d36dSMichael Walle default: 1594406d36dSMichael Walle return 0; 1604406d36dSMichael Walle } 1614406d36dSMichael Walle default: 1624406d36dSMichael Walle return 0; 1634406d36dSMichael Walle } 1644406d36dSMichael Walle } 1654406d36dSMichael Walle 1664406d36dSMichael Walle static int bcm54140_hwmon_read_alarm(struct device *dev, unsigned int bit, 1674406d36dSMichael Walle long *val) 1684406d36dSMichael Walle { 1694406d36dSMichael Walle struct phy_device *phydev = dev_get_drvdata(dev); 1704406d36dSMichael Walle struct bcm54140_priv *priv = phydev->priv; 1714406d36dSMichael Walle int tmp, ret = 0; 1724406d36dSMichael Walle 1734406d36dSMichael Walle mutex_lock(&priv->alarm_lock); 1744406d36dSMichael Walle 1754406d36dSMichael Walle /* latch any alarm bits */ 1764406d36dSMichael Walle tmp = bcm_phy_read_rdb(phydev, BCM54140_RDB_MON_ISR); 1774406d36dSMichael Walle if (tmp < 0) { 1784406d36dSMichael Walle ret = tmp; 1794406d36dSMichael Walle goto out; 1804406d36dSMichael Walle } 1814406d36dSMichael Walle priv->alarm |= tmp; 1824406d36dSMichael Walle 1834406d36dSMichael Walle *val = !!(priv->alarm & bit); 1844406d36dSMichael Walle priv->alarm &= ~bit; 1854406d36dSMichael Walle 1864406d36dSMichael Walle out: 1874406d36dSMichael Walle mutex_unlock(&priv->alarm_lock); 1884406d36dSMichael Walle return ret; 1894406d36dSMichael Walle } 1904406d36dSMichael Walle 1914406d36dSMichael Walle static int bcm54140_hwmon_read_temp(struct device *dev, u32 attr, long *val) 1924406d36dSMichael Walle { 1934406d36dSMichael Walle struct phy_device *phydev = dev_get_drvdata(dev); 1944406d36dSMichael Walle u16 reg, tmp; 1954406d36dSMichael Walle 1964406d36dSMichael Walle switch (attr) { 1974406d36dSMichael Walle case hwmon_temp_input: 1984406d36dSMichael Walle reg = BCM54140_RDB_MON_TEMP_VAL; 1994406d36dSMichael Walle break; 2004406d36dSMichael Walle case hwmon_temp_min: 2014406d36dSMichael Walle reg = BCM54140_RDB_MON_TEMP_MIN; 2024406d36dSMichael Walle break; 2034406d36dSMichael Walle case hwmon_temp_max: 2044406d36dSMichael Walle reg = BCM54140_RDB_MON_TEMP_MAX; 2054406d36dSMichael Walle break; 2064406d36dSMichael Walle case hwmon_temp_alarm: 2074406d36dSMichael Walle return bcm54140_hwmon_read_alarm(dev, 2084406d36dSMichael Walle BCM54140_RDB_MON_ISR_TEMP, 2094406d36dSMichael Walle val); 2104406d36dSMichael Walle default: 2114406d36dSMichael Walle return -EOPNOTSUPP; 2124406d36dSMichael Walle } 2134406d36dSMichael Walle 2144406d36dSMichael Walle tmp = bcm_phy_read_rdb(phydev, reg); 2154406d36dSMichael Walle if (tmp < 0) 2164406d36dSMichael Walle return tmp; 2174406d36dSMichael Walle 2184406d36dSMichael Walle *val = BCM54140_HWMON_TO_TEMP(tmp & BCM54140_RDB_MON_TEMP_DATA_MASK); 2194406d36dSMichael Walle 2204406d36dSMichael Walle return 0; 2214406d36dSMichael Walle } 2224406d36dSMichael Walle 2234406d36dSMichael Walle static int bcm54140_hwmon_read_in(struct device *dev, u32 attr, 2244406d36dSMichael Walle int channel, long *val) 2254406d36dSMichael Walle { 2264406d36dSMichael Walle struct phy_device *phydev = dev_get_drvdata(dev); 2274406d36dSMichael Walle u16 bit, reg, tmp; 2284406d36dSMichael Walle 2294406d36dSMichael Walle switch (attr) { 2304406d36dSMichael Walle case hwmon_in_input: 2314406d36dSMichael Walle reg = BCM54140_HWMON_IN_VAL_REG(channel); 2324406d36dSMichael Walle break; 2334406d36dSMichael Walle case hwmon_in_min: 2344406d36dSMichael Walle reg = BCM54140_HWMON_IN_MIN_REG(channel); 2354406d36dSMichael Walle break; 2364406d36dSMichael Walle case hwmon_in_max: 2374406d36dSMichael Walle reg = BCM54140_HWMON_IN_MAX_REG(channel); 2384406d36dSMichael Walle break; 2394406d36dSMichael Walle case hwmon_in_alarm: 2404406d36dSMichael Walle bit = BCM54140_HWMON_IN_ALARM_BIT(channel); 2414406d36dSMichael Walle return bcm54140_hwmon_read_alarm(dev, bit, val); 2424406d36dSMichael Walle default: 2434406d36dSMichael Walle return -EOPNOTSUPP; 2444406d36dSMichael Walle } 2454406d36dSMichael Walle 2464406d36dSMichael Walle tmp = bcm_phy_read_rdb(phydev, reg); 2474406d36dSMichael Walle if (tmp < 0) 2484406d36dSMichael Walle return tmp; 2494406d36dSMichael Walle 2504406d36dSMichael Walle tmp &= BCM54140_HWMON_IN_MASK(channel); 2514406d36dSMichael Walle *val = BCM54140_HWMON_TO_IN(channel, tmp); 2524406d36dSMichael Walle 2534406d36dSMichael Walle return 0; 2544406d36dSMichael Walle } 2554406d36dSMichael Walle 2564406d36dSMichael Walle static int bcm54140_hwmon_read(struct device *dev, 2574406d36dSMichael Walle enum hwmon_sensor_types type, u32 attr, 2584406d36dSMichael Walle int channel, long *val) 2594406d36dSMichael Walle { 2604406d36dSMichael Walle switch (type) { 2614406d36dSMichael Walle case hwmon_temp: 2624406d36dSMichael Walle return bcm54140_hwmon_read_temp(dev, attr, val); 2634406d36dSMichael Walle case hwmon_in: 2644406d36dSMichael Walle return bcm54140_hwmon_read_in(dev, attr, channel, val); 2654406d36dSMichael Walle default: 2664406d36dSMichael Walle return -EOPNOTSUPP; 2674406d36dSMichael Walle } 2684406d36dSMichael Walle } 2694406d36dSMichael Walle 2704406d36dSMichael Walle static const char *const bcm54140_hwmon_in_labels[] = { 2714406d36dSMichael Walle "AVDDL", 2724406d36dSMichael Walle "AVDDH", 2734406d36dSMichael Walle }; 2744406d36dSMichael Walle 2754406d36dSMichael Walle static int bcm54140_hwmon_read_string(struct device *dev, 2764406d36dSMichael Walle enum hwmon_sensor_types type, u32 attr, 2774406d36dSMichael Walle int channel, const char **str) 2784406d36dSMichael Walle { 2794406d36dSMichael Walle switch (type) { 2804406d36dSMichael Walle case hwmon_in: 2814406d36dSMichael Walle switch (attr) { 2824406d36dSMichael Walle case hwmon_in_label: 2834406d36dSMichael Walle *str = bcm54140_hwmon_in_labels[channel]; 2844406d36dSMichael Walle return 0; 2854406d36dSMichael Walle default: 2864406d36dSMichael Walle return -EOPNOTSUPP; 2874406d36dSMichael Walle } 2884406d36dSMichael Walle default: 2894406d36dSMichael Walle return -EOPNOTSUPP; 2904406d36dSMichael Walle } 2914406d36dSMichael Walle } 2924406d36dSMichael Walle 2934406d36dSMichael Walle static int bcm54140_hwmon_write_temp(struct device *dev, u32 attr, 2944406d36dSMichael Walle int channel, long val) 2954406d36dSMichael Walle { 2964406d36dSMichael Walle struct phy_device *phydev = dev_get_drvdata(dev); 2974406d36dSMichael Walle u16 mask = BCM54140_RDB_MON_TEMP_DATA_MASK; 2984406d36dSMichael Walle u16 reg; 2994406d36dSMichael Walle 3004406d36dSMichael Walle val = clamp_val(val, BCM54140_HWMON_TO_TEMP(mask), 3014406d36dSMichael Walle BCM54140_HWMON_TO_TEMP(0)); 3024406d36dSMichael Walle 3034406d36dSMichael Walle switch (attr) { 3044406d36dSMichael Walle case hwmon_temp_min: 3054406d36dSMichael Walle reg = BCM54140_RDB_MON_TEMP_MIN; 3064406d36dSMichael Walle break; 3074406d36dSMichael Walle case hwmon_temp_max: 3084406d36dSMichael Walle reg = BCM54140_RDB_MON_TEMP_MAX; 3094406d36dSMichael Walle break; 3104406d36dSMichael Walle default: 3114406d36dSMichael Walle return -EOPNOTSUPP; 3124406d36dSMichael Walle } 3134406d36dSMichael Walle 3144406d36dSMichael Walle return bcm_phy_modify_rdb(phydev, reg, mask, 3154406d36dSMichael Walle BCM54140_HWMON_FROM_TEMP(val)); 3164406d36dSMichael Walle } 3174406d36dSMichael Walle 3184406d36dSMichael Walle static int bcm54140_hwmon_write_in(struct device *dev, u32 attr, 3194406d36dSMichael Walle int channel, long val) 3204406d36dSMichael Walle { 3214406d36dSMichael Walle struct phy_device *phydev = dev_get_drvdata(dev); 3224406d36dSMichael Walle u16 mask = BCM54140_HWMON_IN_MASK(channel); 3234406d36dSMichael Walle u16 reg; 3244406d36dSMichael Walle 3254406d36dSMichael Walle val = clamp_val(val, 0, BCM54140_HWMON_TO_IN(channel, mask)); 3264406d36dSMichael Walle 3274406d36dSMichael Walle switch (attr) { 3284406d36dSMichael Walle case hwmon_in_min: 3294406d36dSMichael Walle reg = BCM54140_HWMON_IN_MIN_REG(channel); 3304406d36dSMichael Walle break; 3314406d36dSMichael Walle case hwmon_in_max: 3324406d36dSMichael Walle reg = BCM54140_HWMON_IN_MAX_REG(channel); 3334406d36dSMichael Walle break; 3344406d36dSMichael Walle default: 3354406d36dSMichael Walle return -EOPNOTSUPP; 3364406d36dSMichael Walle } 3374406d36dSMichael Walle 3384406d36dSMichael Walle return bcm_phy_modify_rdb(phydev, reg, mask, 3394406d36dSMichael Walle BCM54140_HWMON_FROM_IN(channel, val)); 3404406d36dSMichael Walle } 3414406d36dSMichael Walle 3424406d36dSMichael Walle static int bcm54140_hwmon_write(struct device *dev, 3434406d36dSMichael Walle enum hwmon_sensor_types type, u32 attr, 3444406d36dSMichael Walle int channel, long val) 3454406d36dSMichael Walle { 3464406d36dSMichael Walle switch (type) { 3474406d36dSMichael Walle case hwmon_temp: 3484406d36dSMichael Walle return bcm54140_hwmon_write_temp(dev, attr, channel, val); 3494406d36dSMichael Walle case hwmon_in: 3504406d36dSMichael Walle return bcm54140_hwmon_write_in(dev, attr, channel, val); 3514406d36dSMichael Walle default: 3524406d36dSMichael Walle return -EOPNOTSUPP; 3534406d36dSMichael Walle } 3544406d36dSMichael Walle } 3554406d36dSMichael Walle 3564406d36dSMichael Walle static const struct hwmon_channel_info *bcm54140_hwmon_info[] = { 3574406d36dSMichael Walle HWMON_CHANNEL_INFO(temp, 3584406d36dSMichael Walle HWMON_T_INPUT | HWMON_T_MIN | HWMON_T_MAX | 3594406d36dSMichael Walle HWMON_T_ALARM), 3604406d36dSMichael Walle HWMON_CHANNEL_INFO(in, 3614406d36dSMichael Walle HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | 3624406d36dSMichael Walle HWMON_I_ALARM | HWMON_I_LABEL, 3634406d36dSMichael Walle HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX | 3644406d36dSMichael Walle HWMON_I_ALARM | HWMON_I_LABEL), 3654406d36dSMichael Walle NULL 3664406d36dSMichael Walle }; 3674406d36dSMichael Walle 3684406d36dSMichael Walle static const struct hwmon_ops bcm54140_hwmon_ops = { 3694406d36dSMichael Walle .is_visible = bcm54140_hwmon_is_visible, 3704406d36dSMichael Walle .read = bcm54140_hwmon_read, 3714406d36dSMichael Walle .read_string = bcm54140_hwmon_read_string, 3724406d36dSMichael Walle .write = bcm54140_hwmon_write, 3734406d36dSMichael Walle }; 3744406d36dSMichael Walle 3754406d36dSMichael Walle static const struct hwmon_chip_info bcm54140_chip_info = { 3764406d36dSMichael Walle .ops = &bcm54140_hwmon_ops, 3774406d36dSMichael Walle .info = bcm54140_hwmon_info, 3784406d36dSMichael Walle }; 3794406d36dSMichael Walle 3804406d36dSMichael Walle static int bcm54140_enable_monitoring(struct phy_device *phydev) 3814406d36dSMichael Walle { 3824406d36dSMichael Walle u16 mask, set; 3834406d36dSMichael Walle 3844406d36dSMichael Walle /* 3.3V voltage mode */ 3854406d36dSMichael Walle set = BCM54140_RDB_MON_CTRL_V_MODE; 3864406d36dSMichael Walle 3874406d36dSMichael Walle /* select round-robin */ 3884406d36dSMichael Walle mask = BCM54140_RDB_MON_CTRL_SEL_MASK; 3894406d36dSMichael Walle set |= FIELD_PREP(BCM54140_RDB_MON_CTRL_SEL_MASK, 3904406d36dSMichael Walle BCM54140_RDB_MON_CTRL_SEL_RR); 3914406d36dSMichael Walle 3924406d36dSMichael Walle /* remove power-down bit */ 3934406d36dSMichael Walle mask |= BCM54140_RDB_MON_CTRL_PWR_DOWN; 3944406d36dSMichael Walle 3954406d36dSMichael Walle return bcm_phy_modify_rdb(phydev, BCM54140_RDB_MON_CTRL, mask, set); 3964406d36dSMichael Walle } 3974406d36dSMichael Walle 3984406d36dSMichael Walle /* Check if one PHY has already done the init of the parts common to all PHYs 3994406d36dSMichael Walle * in the Quad PHY package. 4004406d36dSMichael Walle */ 4014406d36dSMichael Walle static bool bcm54140_is_pkg_init(struct phy_device *phydev) 4024406d36dSMichael Walle { 4034406d36dSMichael Walle struct bcm54140_priv *priv = phydev->priv; 4044406d36dSMichael Walle struct mii_bus *bus = phydev->mdio.bus; 4054406d36dSMichael Walle int base_addr = priv->base_addr; 4064406d36dSMichael Walle struct phy_device *phy; 4074406d36dSMichael Walle int i; 4084406d36dSMichael Walle 4094406d36dSMichael Walle /* Quad PHY */ 4104406d36dSMichael Walle for (i = 0; i < 4; i++) { 4114406d36dSMichael Walle phy = mdiobus_get_phy(bus, base_addr + i); 4124406d36dSMichael Walle if (!phy) 4134406d36dSMichael Walle continue; 4144406d36dSMichael Walle 4154406d36dSMichael Walle if ((phy->phy_id & phydev->drv->phy_id_mask) != 4164406d36dSMichael Walle (phydev->drv->phy_id & phydev->drv->phy_id_mask)) 4174406d36dSMichael Walle continue; 4184406d36dSMichael Walle 4194406d36dSMichael Walle priv = phy->priv; 4204406d36dSMichael Walle 4214406d36dSMichael Walle if (priv && priv->pkg_init) 4224406d36dSMichael Walle return true; 4234406d36dSMichael Walle } 4244406d36dSMichael Walle 4254406d36dSMichael Walle return false; 4264406d36dSMichael Walle } 4274406d36dSMichael Walle 4284406d36dSMichael Walle static int bcm54140_probe_once(struct phy_device *phydev) 4294406d36dSMichael Walle { 4304406d36dSMichael Walle struct device *hwmon; 4314406d36dSMichael Walle int ret; 4324406d36dSMichael Walle 4334406d36dSMichael Walle /* enable hardware monitoring */ 4344406d36dSMichael Walle ret = bcm54140_enable_monitoring(phydev); 4354406d36dSMichael Walle if (ret) 4364406d36dSMichael Walle return ret; 4374406d36dSMichael Walle 4384406d36dSMichael Walle hwmon = devm_hwmon_device_register_with_info(&phydev->mdio.dev, 4394406d36dSMichael Walle "BCM54140", phydev, 4404406d36dSMichael Walle &bcm54140_chip_info, 4414406d36dSMichael Walle NULL); 4424406d36dSMichael Walle return PTR_ERR_OR_ZERO(hwmon); 4434406d36dSMichael Walle } 4444406d36dSMichael Walle #endif 4454406d36dSMichael Walle 4466937602eSMichael Walle static int bcm54140_base_read_rdb(struct phy_device *phydev, u16 rdb) 4476937602eSMichael Walle { 4486937602eSMichael Walle struct bcm54140_priv *priv = phydev->priv; 4496937602eSMichael Walle struct mii_bus *bus = phydev->mdio.bus; 4506937602eSMichael Walle int ret; 4516937602eSMichael Walle 4526937602eSMichael Walle mutex_lock(&bus->mdio_lock); 4536937602eSMichael Walle ret = __mdiobus_write(bus, priv->base_addr, MII_BCM54XX_RDB_ADDR, rdb); 4546937602eSMichael Walle if (ret < 0) 4556937602eSMichael Walle goto out; 4566937602eSMichael Walle 4576937602eSMichael Walle ret = __mdiobus_read(bus, priv->base_addr, MII_BCM54XX_RDB_DATA); 4586937602eSMichael Walle 4596937602eSMichael Walle out: 4606937602eSMichael Walle mutex_unlock(&bus->mdio_lock); 4616937602eSMichael Walle return ret; 4626937602eSMichael Walle } 4636937602eSMichael Walle 4646937602eSMichael Walle static int bcm54140_base_write_rdb(struct phy_device *phydev, 4656937602eSMichael Walle u16 rdb, u16 val) 4666937602eSMichael Walle { 4676937602eSMichael Walle struct bcm54140_priv *priv = phydev->priv; 4686937602eSMichael Walle struct mii_bus *bus = phydev->mdio.bus; 4696937602eSMichael Walle int ret; 4706937602eSMichael Walle 4716937602eSMichael Walle mutex_lock(&bus->mdio_lock); 4726937602eSMichael Walle ret = __mdiobus_write(bus, priv->base_addr, MII_BCM54XX_RDB_ADDR, rdb); 4736937602eSMichael Walle if (ret < 0) 4746937602eSMichael Walle goto out; 4756937602eSMichael Walle 4766937602eSMichael Walle ret = __mdiobus_write(bus, priv->base_addr, MII_BCM54XX_RDB_DATA, val); 4776937602eSMichael Walle 4786937602eSMichael Walle out: 4796937602eSMichael Walle mutex_unlock(&bus->mdio_lock); 4806937602eSMichael Walle return ret; 4816937602eSMichael Walle } 4826937602eSMichael Walle 4836937602eSMichael Walle /* Under some circumstances a core PLL may not lock, this will then prevent 4846937602eSMichael Walle * a successful link establishment. Restart the PLL after the voltages are 4856937602eSMichael Walle * stable to workaround this issue. 4866937602eSMichael Walle */ 4876937602eSMichael Walle static int bcm54140_b0_workaround(struct phy_device *phydev) 4886937602eSMichael Walle { 4896937602eSMichael Walle int spare3; 4906937602eSMichael Walle int ret; 4916937602eSMichael Walle 4926937602eSMichael Walle spare3 = bcm_phy_read_rdb(phydev, BCM54140_RDB_SPARE3); 4936937602eSMichael Walle if (spare3 < 0) 4946937602eSMichael Walle return spare3; 4956937602eSMichael Walle 4966937602eSMichael Walle spare3 &= ~BCM54140_RDB_SPARE3_BIT0; 4976937602eSMichael Walle 4986937602eSMichael Walle ret = bcm_phy_write_rdb(phydev, BCM54140_RDB_SPARE3, spare3); 4996937602eSMichael Walle if (ret) 5006937602eSMichael Walle return ret; 5016937602eSMichael Walle 5026937602eSMichael Walle ret = phy_modify(phydev, MII_BMCR, 0, BMCR_PDOWN); 5036937602eSMichael Walle if (ret) 5046937602eSMichael Walle return ret; 5056937602eSMichael Walle 5066937602eSMichael Walle ret = phy_modify(phydev, MII_BMCR, BMCR_PDOWN, 0); 5076937602eSMichael Walle if (ret) 5086937602eSMichael Walle return ret; 5096937602eSMichael Walle 5106937602eSMichael Walle spare3 |= BCM54140_RDB_SPARE3_BIT0; 5116937602eSMichael Walle 5126937602eSMichael Walle return bcm_phy_write_rdb(phydev, BCM54140_RDB_SPARE3, spare3); 5136937602eSMichael Walle } 5146937602eSMichael Walle 5156937602eSMichael Walle /* The BCM54140 is a quad PHY where only the first port has access to the 5166937602eSMichael Walle * global register. Thus we need to find out its PHY address. 5176937602eSMichael Walle * 5186937602eSMichael Walle */ 5196937602eSMichael Walle static int bcm54140_get_base_addr_and_port(struct phy_device *phydev) 5206937602eSMichael Walle { 5216937602eSMichael Walle struct bcm54140_priv *priv = phydev->priv; 5226937602eSMichael Walle struct mii_bus *bus = phydev->mdio.bus; 5236937602eSMichael Walle int addr, min_addr, max_addr; 5246937602eSMichael Walle int step = 1; 5256937602eSMichael Walle u32 phy_id; 5266937602eSMichael Walle int tmp; 5276937602eSMichael Walle 5286937602eSMichael Walle min_addr = phydev->mdio.addr; 5296937602eSMichael Walle max_addr = phydev->mdio.addr; 5306937602eSMichael Walle addr = phydev->mdio.addr; 5316937602eSMichael Walle 5326937602eSMichael Walle /* We scan forward and backwards and look for PHYs which have the 5336937602eSMichael Walle * same phy_id like we do. Step 1 will scan forward, step 2 5346937602eSMichael Walle * backwards. Once we are finished, we have a min_addr and 5356937602eSMichael Walle * max_addr which resembles the range of PHY addresses of the same 5366937602eSMichael Walle * type of PHY. There is one caveat; there may be many PHYs of 5376937602eSMichael Walle * the same type, but we know that each PHY takes exactly 4 5386937602eSMichael Walle * consecutive addresses. Therefore we can deduce our offset 5396937602eSMichael Walle * to the base address of this quad PHY. 5406937602eSMichael Walle */ 5416937602eSMichael Walle 5426937602eSMichael Walle while (1) { 5436937602eSMichael Walle if (step == 3) { 5446937602eSMichael Walle break; 5456937602eSMichael Walle } else if (step == 1) { 5466937602eSMichael Walle max_addr = addr; 5476937602eSMichael Walle addr++; 5486937602eSMichael Walle } else { 5496937602eSMichael Walle min_addr = addr; 5506937602eSMichael Walle addr--; 5516937602eSMichael Walle } 5526937602eSMichael Walle 5536937602eSMichael Walle if (addr < 0 || addr >= PHY_MAX_ADDR) { 5546937602eSMichael Walle addr = phydev->mdio.addr; 5556937602eSMichael Walle step++; 5566937602eSMichael Walle continue; 5576937602eSMichael Walle } 5586937602eSMichael Walle 5596937602eSMichael Walle /* read the PHY id */ 5606937602eSMichael Walle tmp = mdiobus_read(bus, addr, MII_PHYSID1); 5616937602eSMichael Walle if (tmp < 0) 5626937602eSMichael Walle return tmp; 5636937602eSMichael Walle phy_id = tmp << 16; 5646937602eSMichael Walle tmp = mdiobus_read(bus, addr, MII_PHYSID2); 5656937602eSMichael Walle if (tmp < 0) 5666937602eSMichael Walle return tmp; 5676937602eSMichael Walle phy_id |= tmp; 5686937602eSMichael Walle 5696937602eSMichael Walle /* see if it is still the same PHY */ 5706937602eSMichael Walle if ((phy_id & phydev->drv->phy_id_mask) != 5716937602eSMichael Walle (phydev->drv->phy_id & phydev->drv->phy_id_mask)) { 5726937602eSMichael Walle addr = phydev->mdio.addr; 5736937602eSMichael Walle step++; 5746937602eSMichael Walle } 5756937602eSMichael Walle } 5766937602eSMichael Walle 5776937602eSMichael Walle /* The range we get should be a multiple of four. Please note that both 5786937602eSMichael Walle * the min_addr and max_addr are inclusive. So we have to add one if we 5796937602eSMichael Walle * subtract them. 5806937602eSMichael Walle */ 5816937602eSMichael Walle if ((max_addr - min_addr + 1) % 4) { 5826937602eSMichael Walle dev_err(&phydev->mdio.dev, 5836937602eSMichael Walle "Detected Quad PHY IDs %d..%d doesn't make sense.\n", 5846937602eSMichael Walle min_addr, max_addr); 5856937602eSMichael Walle return -EINVAL; 5866937602eSMichael Walle } 5876937602eSMichael Walle 5886937602eSMichael Walle priv->port = (phydev->mdio.addr - min_addr) % 4; 5896937602eSMichael Walle priv->base_addr = phydev->mdio.addr - priv->port; 5906937602eSMichael Walle 5916937602eSMichael Walle return 0; 5926937602eSMichael Walle } 5936937602eSMichael Walle 5946937602eSMichael Walle static int bcm54140_probe(struct phy_device *phydev) 5956937602eSMichael Walle { 5966937602eSMichael Walle struct bcm54140_priv *priv; 5976937602eSMichael Walle int ret; 5986937602eSMichael Walle 5996937602eSMichael Walle priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); 6006937602eSMichael Walle if (!priv) 6016937602eSMichael Walle return -ENOMEM; 6026937602eSMichael Walle 6036937602eSMichael Walle phydev->priv = priv; 6046937602eSMichael Walle 6056937602eSMichael Walle ret = bcm54140_get_base_addr_and_port(phydev); 6066937602eSMichael Walle if (ret) 6076937602eSMichael Walle return ret; 6086937602eSMichael Walle 6094406d36dSMichael Walle #if IS_ENABLED(CONFIG_HWMON) 6104406d36dSMichael Walle mutex_init(&priv->alarm_lock); 6114406d36dSMichael Walle 6124406d36dSMichael Walle if (!bcm54140_is_pkg_init(phydev)) { 6134406d36dSMichael Walle ret = bcm54140_probe_once(phydev); 6144406d36dSMichael Walle if (ret) 6154406d36dSMichael Walle return ret; 6164406d36dSMichael Walle } 6174406d36dSMichael Walle 6184406d36dSMichael Walle priv->pkg_init = true; 6194406d36dSMichael Walle #endif 6204406d36dSMichael Walle 6216937602eSMichael Walle phydev_dbg(phydev, "probed (port %d, base PHY address %d)\n", 6226937602eSMichael Walle priv->port, priv->base_addr); 6236937602eSMichael Walle 6246937602eSMichael Walle return 0; 6256937602eSMichael Walle } 6266937602eSMichael Walle 6276937602eSMichael Walle static int bcm54140_config_init(struct phy_device *phydev) 6286937602eSMichael Walle { 6296937602eSMichael Walle u16 reg = 0xffff; 6306937602eSMichael Walle int ret; 6316937602eSMichael Walle 6326937602eSMichael Walle /* Apply hardware errata */ 6336937602eSMichael Walle ret = bcm54140_b0_workaround(phydev); 6346937602eSMichael Walle if (ret) 6356937602eSMichael Walle return ret; 6366937602eSMichael Walle 6376937602eSMichael Walle /* Unmask events we are interested in. */ 6386937602eSMichael Walle reg &= ~(BCM54140_RDB_INT_DUPLEX | 6396937602eSMichael Walle BCM54140_RDB_INT_SPEED | 6406937602eSMichael Walle BCM54140_RDB_INT_LINK); 6416937602eSMichael Walle ret = bcm_phy_write_rdb(phydev, BCM54140_RDB_IMR, reg); 6426937602eSMichael Walle if (ret) 6436937602eSMichael Walle return ret; 6446937602eSMichael Walle 6456937602eSMichael Walle /* LED1=LINKSPD[1], LED2=LINKSPD[2], LED3=LINK/ACTIVITY */ 6466937602eSMichael Walle ret = bcm_phy_modify_rdb(phydev, BCM54140_RDB_SPARE1, 6476937602eSMichael Walle 0, BCM54140_RDB_SPARE1_LSLM); 6486937602eSMichael Walle if (ret) 6496937602eSMichael Walle return ret; 6506937602eSMichael Walle 6516937602eSMichael Walle ret = bcm_phy_modify_rdb(phydev, BCM54140_RDB_LED_CTRL, 6526937602eSMichael Walle 0, BCM54140_RDB_LED_CTRL_ACTLINK0); 6536937602eSMichael Walle if (ret) 6546937602eSMichael Walle return ret; 6556937602eSMichael Walle 6566937602eSMichael Walle /* disable super isolate mode */ 6576937602eSMichael Walle return bcm_phy_modify_rdb(phydev, BCM54140_RDB_C_PWR, 6586937602eSMichael Walle BCM54140_RDB_C_PWR_ISOLATE, 0); 6596937602eSMichael Walle } 6606937602eSMichael Walle 6616937602eSMichael Walle int bcm54140_did_interrupt(struct phy_device *phydev) 6626937602eSMichael Walle { 6636937602eSMichael Walle int ret; 6646937602eSMichael Walle 6656937602eSMichael Walle ret = bcm_phy_read_rdb(phydev, BCM54140_RDB_ISR); 6666937602eSMichael Walle 6676937602eSMichael Walle return (ret < 0) ? 0 : ret; 6686937602eSMichael Walle } 6696937602eSMichael Walle 6706937602eSMichael Walle int bcm54140_ack_intr(struct phy_device *phydev) 6716937602eSMichael Walle { 6726937602eSMichael Walle int reg; 6736937602eSMichael Walle 6746937602eSMichael Walle /* clear pending interrupts */ 6756937602eSMichael Walle reg = bcm_phy_read_rdb(phydev, BCM54140_RDB_ISR); 6766937602eSMichael Walle if (reg < 0) 6776937602eSMichael Walle return reg; 6786937602eSMichael Walle 6796937602eSMichael Walle return 0; 6806937602eSMichael Walle } 6816937602eSMichael Walle 6826937602eSMichael Walle int bcm54140_config_intr(struct phy_device *phydev) 6836937602eSMichael Walle { 6846937602eSMichael Walle struct bcm54140_priv *priv = phydev->priv; 6856937602eSMichael Walle static const u16 port_to_imr_bit[] = { 6866937602eSMichael Walle BCM54140_RDB_TOP_IMR_PORT0, BCM54140_RDB_TOP_IMR_PORT1, 6876937602eSMichael Walle BCM54140_RDB_TOP_IMR_PORT2, BCM54140_RDB_TOP_IMR_PORT3, 6886937602eSMichael Walle }; 6896937602eSMichael Walle int reg; 6906937602eSMichael Walle 6916937602eSMichael Walle if (priv->port >= ARRAY_SIZE(port_to_imr_bit)) 6926937602eSMichael Walle return -EINVAL; 6936937602eSMichael Walle 6946937602eSMichael Walle reg = bcm54140_base_read_rdb(phydev, BCM54140_RDB_TOP_IMR); 6956937602eSMichael Walle if (reg < 0) 6966937602eSMichael Walle return reg; 6976937602eSMichael Walle 6986937602eSMichael Walle if (phydev->interrupts == PHY_INTERRUPT_ENABLED) 6996937602eSMichael Walle reg &= ~port_to_imr_bit[priv->port]; 7006937602eSMichael Walle else 7016937602eSMichael Walle reg |= port_to_imr_bit[priv->port]; 7026937602eSMichael Walle 7036937602eSMichael Walle return bcm54140_base_write_rdb(phydev, BCM54140_RDB_TOP_IMR, reg); 7046937602eSMichael Walle } 7056937602eSMichael Walle 7066937602eSMichael Walle static int bcm54140_get_downshift(struct phy_device *phydev, u8 *data) 7076937602eSMichael Walle { 7086937602eSMichael Walle int val; 7096937602eSMichael Walle 7106937602eSMichael Walle val = bcm_phy_read_rdb(phydev, BCM54140_RDB_C_MISC_CTRL); 7116937602eSMichael Walle if (val < 0) 7126937602eSMichael Walle return val; 7136937602eSMichael Walle 7146937602eSMichael Walle if (!(val & BCM54140_RDB_C_MISC_CTRL_WS_EN)) { 7156937602eSMichael Walle *data = DOWNSHIFT_DEV_DISABLE; 7166937602eSMichael Walle return 0; 7176937602eSMichael Walle } 7186937602eSMichael Walle 7196937602eSMichael Walle val = bcm_phy_read_rdb(phydev, BCM54140_RDB_SPARE2); 7206937602eSMichael Walle if (val < 0) 7216937602eSMichael Walle return val; 7226937602eSMichael Walle 7236937602eSMichael Walle if (val & BCM54140_RDB_SPARE2_WS_RTRY_DIS) 7246937602eSMichael Walle *data = 1; 7256937602eSMichael Walle else 7266937602eSMichael Walle *data = FIELD_GET(BCM54140_RDB_SPARE2_WS_RTRY_LIMIT, val) + 2; 7276937602eSMichael Walle 7286937602eSMichael Walle return 0; 7296937602eSMichael Walle } 7306937602eSMichael Walle 7316937602eSMichael Walle static int bcm54140_set_downshift(struct phy_device *phydev, u8 cnt) 7326937602eSMichael Walle { 7336937602eSMichael Walle u16 mask, set; 7346937602eSMichael Walle int ret; 7356937602eSMichael Walle 7366937602eSMichael Walle if (cnt > BCM54140_MAX_DOWNSHIFT && cnt != DOWNSHIFT_DEV_DEFAULT_COUNT) 7376937602eSMichael Walle return -EINVAL; 7386937602eSMichael Walle 7396937602eSMichael Walle if (!cnt) 7406937602eSMichael Walle return bcm_phy_modify_rdb(phydev, BCM54140_RDB_C_MISC_CTRL, 7416937602eSMichael Walle BCM54140_RDB_C_MISC_CTRL_WS_EN, 0); 7426937602eSMichael Walle 7436937602eSMichael Walle if (cnt == DOWNSHIFT_DEV_DEFAULT_COUNT) 7446937602eSMichael Walle cnt = BCM54140_DEFAULT_DOWNSHIFT; 7456937602eSMichael Walle 7466937602eSMichael Walle if (cnt == 1) { 7476937602eSMichael Walle mask = 0; 7486937602eSMichael Walle set = BCM54140_RDB_SPARE2_WS_RTRY_DIS; 7496937602eSMichael Walle } else { 7506937602eSMichael Walle mask = BCM54140_RDB_SPARE2_WS_RTRY_DIS; 7516937602eSMichael Walle mask |= BCM54140_RDB_SPARE2_WS_RTRY_LIMIT; 7526937602eSMichael Walle set = FIELD_PREP(BCM54140_RDB_SPARE2_WS_RTRY_LIMIT, cnt - 2); 7536937602eSMichael Walle } 7546937602eSMichael Walle ret = bcm_phy_modify_rdb(phydev, BCM54140_RDB_SPARE2, 7556937602eSMichael Walle mask, set); 7566937602eSMichael Walle if (ret) 7576937602eSMichael Walle return ret; 7586937602eSMichael Walle 7596937602eSMichael Walle return bcm_phy_modify_rdb(phydev, BCM54140_RDB_C_MISC_CTRL, 7606937602eSMichael Walle 0, BCM54140_RDB_C_MISC_CTRL_WS_EN); 7616937602eSMichael Walle } 7626937602eSMichael Walle 7636937602eSMichael Walle static int bcm54140_get_edpd(struct phy_device *phydev, u16 *tx_interval) 7646937602eSMichael Walle { 7656937602eSMichael Walle int val; 7666937602eSMichael Walle 7676937602eSMichael Walle val = bcm_phy_read_rdb(phydev, BCM54140_RDB_C_APWR); 7686937602eSMichael Walle if (val < 0) 7696937602eSMichael Walle return val; 7706937602eSMichael Walle 7716937602eSMichael Walle switch (FIELD_GET(BCM54140_RDB_C_APWR_APD_MODE_MASK, val)) { 7726937602eSMichael Walle case BCM54140_RDB_C_APWR_APD_MODE_DIS: 7736937602eSMichael Walle case BCM54140_RDB_C_APWR_APD_MODE_DIS2: 7746937602eSMichael Walle *tx_interval = ETHTOOL_PHY_EDPD_DISABLE; 7756937602eSMichael Walle break; 7766937602eSMichael Walle case BCM54140_RDB_C_APWR_APD_MODE_EN: 7776937602eSMichael Walle case BCM54140_RDB_C_APWR_APD_MODE_EN_ANEG: 7786937602eSMichael Walle switch (FIELD_GET(BCM54140_RDB_C_APWR_SLP_TIM_MASK, val)) { 7796937602eSMichael Walle case BCM54140_RDB_C_APWR_SLP_TIM_2_7: 7806937602eSMichael Walle *tx_interval = 2700; 7816937602eSMichael Walle break; 7826937602eSMichael Walle case BCM54140_RDB_C_APWR_SLP_TIM_5_4: 7836937602eSMichael Walle *tx_interval = 5400; 7846937602eSMichael Walle break; 7856937602eSMichael Walle } 7866937602eSMichael Walle } 7876937602eSMichael Walle 7886937602eSMichael Walle return 0; 7896937602eSMichael Walle } 7906937602eSMichael Walle 7916937602eSMichael Walle static int bcm54140_set_edpd(struct phy_device *phydev, u16 tx_interval) 7926937602eSMichael Walle { 7936937602eSMichael Walle u16 mask, set; 7946937602eSMichael Walle 7956937602eSMichael Walle mask = BCM54140_RDB_C_APWR_APD_MODE_MASK; 7966937602eSMichael Walle if (tx_interval == ETHTOOL_PHY_EDPD_DISABLE) 7976937602eSMichael Walle set = FIELD_PREP(BCM54140_RDB_C_APWR_APD_MODE_MASK, 7986937602eSMichael Walle BCM54140_RDB_C_APWR_APD_MODE_DIS); 7996937602eSMichael Walle else 8006937602eSMichael Walle set = FIELD_PREP(BCM54140_RDB_C_APWR_APD_MODE_MASK, 8016937602eSMichael Walle BCM54140_RDB_C_APWR_APD_MODE_EN_ANEG); 8026937602eSMichael Walle 8036937602eSMichael Walle /* enable single pulse mode */ 8046937602eSMichael Walle set |= BCM54140_RDB_C_APWR_SINGLE_PULSE; 8056937602eSMichael Walle 8066937602eSMichael Walle /* set sleep timer */ 8076937602eSMichael Walle mask |= BCM54140_RDB_C_APWR_SLP_TIM_MASK; 8086937602eSMichael Walle switch (tx_interval) { 8096937602eSMichael Walle case ETHTOOL_PHY_EDPD_DFLT_TX_MSECS: 8106937602eSMichael Walle case ETHTOOL_PHY_EDPD_DISABLE: 8116937602eSMichael Walle case 2700: 8126937602eSMichael Walle set |= BCM54140_RDB_C_APWR_SLP_TIM_2_7; 8136937602eSMichael Walle break; 8146937602eSMichael Walle case 5400: 8156937602eSMichael Walle set |= BCM54140_RDB_C_APWR_SLP_TIM_5_4; 8166937602eSMichael Walle break; 8176937602eSMichael Walle default: 8186937602eSMichael Walle return -EINVAL; 8196937602eSMichael Walle } 8206937602eSMichael Walle 8216937602eSMichael Walle return bcm_phy_modify_rdb(phydev, BCM54140_RDB_C_APWR, mask, set); 8226937602eSMichael Walle } 8236937602eSMichael Walle 8246937602eSMichael Walle static int bcm54140_get_tunable(struct phy_device *phydev, 8256937602eSMichael Walle struct ethtool_tunable *tuna, void *data) 8266937602eSMichael Walle { 8276937602eSMichael Walle switch (tuna->id) { 8286937602eSMichael Walle case ETHTOOL_PHY_DOWNSHIFT: 8296937602eSMichael Walle return bcm54140_get_downshift(phydev, data); 8306937602eSMichael Walle case ETHTOOL_PHY_EDPD: 8316937602eSMichael Walle return bcm54140_get_edpd(phydev, data); 8326937602eSMichael Walle default: 8336937602eSMichael Walle return -EOPNOTSUPP; 8346937602eSMichael Walle } 8356937602eSMichael Walle } 8366937602eSMichael Walle 8376937602eSMichael Walle static int bcm54140_set_tunable(struct phy_device *phydev, 8386937602eSMichael Walle struct ethtool_tunable *tuna, const void *data) 8396937602eSMichael Walle { 8406937602eSMichael Walle switch (tuna->id) { 8416937602eSMichael Walle case ETHTOOL_PHY_DOWNSHIFT: 8426937602eSMichael Walle return bcm54140_set_downshift(phydev, *(const u8 *)data); 8436937602eSMichael Walle case ETHTOOL_PHY_EDPD: 8446937602eSMichael Walle return bcm54140_set_edpd(phydev, *(const u16 *)data); 8456937602eSMichael Walle default: 8466937602eSMichael Walle return -EOPNOTSUPP; 8476937602eSMichael Walle } 8486937602eSMichael Walle } 8496937602eSMichael Walle 8506937602eSMichael Walle static struct phy_driver bcm54140_drivers[] = { 8516937602eSMichael Walle { 8526937602eSMichael Walle .phy_id = PHY_ID_BCM54140, 8536937602eSMichael Walle .phy_id_mask = 0xfffffff0, 8546937602eSMichael Walle .name = "Broadcom BCM54140", 8556937602eSMichael Walle .features = PHY_GBIT_FEATURES, 8566937602eSMichael Walle .config_init = bcm54140_config_init, 8576937602eSMichael Walle .did_interrupt = bcm54140_did_interrupt, 8586937602eSMichael Walle .ack_interrupt = bcm54140_ack_intr, 8596937602eSMichael Walle .config_intr = bcm54140_config_intr, 8606937602eSMichael Walle .probe = bcm54140_probe, 8616937602eSMichael Walle .suspend = genphy_suspend, 8626937602eSMichael Walle .resume = genphy_resume, 8636937602eSMichael Walle .get_tunable = bcm54140_get_tunable, 8646937602eSMichael Walle .set_tunable = bcm54140_set_tunable, 8656937602eSMichael Walle }, 8666937602eSMichael Walle }; 8676937602eSMichael Walle module_phy_driver(bcm54140_drivers); 8686937602eSMichael Walle 8696937602eSMichael Walle static struct mdio_device_id __maybe_unused bcm54140_tbl[] = { 8706937602eSMichael Walle { PHY_ID_BCM54140, 0xfffffff0 }, 8716937602eSMichael Walle { } 8726937602eSMichael Walle }; 8736937602eSMichael Walle 8746937602eSMichael Walle MODULE_AUTHOR("Michael Walle"); 8756937602eSMichael Walle MODULE_DESCRIPTION("Broadcom BCM54140 PHY driver"); 8766937602eSMichael Walle MODULE_DEVICE_TABLE(mdio, bcm54140_tbl); 8776937602eSMichael Walle MODULE_LICENSE("GPL"); 878