1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * drivers/net/phy/at803x.c 4 * 5 * Driver for Qualcomm Atheros AR803x PHY 6 * 7 * Author: Matus Ujhelyi <ujhelyi.m@gmail.com> 8 */ 9 10 #include <linux/phy.h> 11 #include <linux/module.h> 12 #include <linux/string.h> 13 #include <linux/netdevice.h> 14 #include <linux/etherdevice.h> 15 #include <linux/ethtool_netlink.h> 16 #include <linux/bitfield.h> 17 #include <linux/regulator/of_regulator.h> 18 #include <linux/regulator/driver.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/of.h> 21 #include <linux/phylink.h> 22 #include <linux/sfp.h> 23 #include <dt-bindings/net/qca-ar803x.h> 24 25 #define AT803X_SPECIFIC_FUNCTION_CONTROL 0x10 26 #define AT803X_SFC_ASSERT_CRS BIT(11) 27 #define AT803X_SFC_FORCE_LINK BIT(10) 28 #define AT803X_SFC_MDI_CROSSOVER_MODE_M GENMASK(6, 5) 29 #define AT803X_SFC_AUTOMATIC_CROSSOVER 0x3 30 #define AT803X_SFC_MANUAL_MDIX 0x1 31 #define AT803X_SFC_MANUAL_MDI 0x0 32 #define AT803X_SFC_SQE_TEST BIT(2) 33 #define AT803X_SFC_POLARITY_REVERSAL BIT(1) 34 #define AT803X_SFC_DISABLE_JABBER BIT(0) 35 36 #define AT803X_SPECIFIC_STATUS 0x11 37 #define AT803X_SS_SPEED_MASK GENMASK(15, 14) 38 #define AT803X_SS_SPEED_1000 2 39 #define AT803X_SS_SPEED_100 1 40 #define AT803X_SS_SPEED_10 0 41 #define AT803X_SS_DUPLEX BIT(13) 42 #define AT803X_SS_SPEED_DUPLEX_RESOLVED BIT(11) 43 #define AT803X_SS_MDIX BIT(6) 44 45 #define QCA808X_SS_SPEED_MASK GENMASK(9, 7) 46 #define QCA808X_SS_SPEED_2500 4 47 48 #define AT803X_INTR_ENABLE 0x12 49 #define AT803X_INTR_ENABLE_AUTONEG_ERR BIT(15) 50 #define AT803X_INTR_ENABLE_SPEED_CHANGED BIT(14) 51 #define AT803X_INTR_ENABLE_DUPLEX_CHANGED BIT(13) 52 #define AT803X_INTR_ENABLE_PAGE_RECEIVED BIT(12) 53 #define AT803X_INTR_ENABLE_LINK_FAIL BIT(11) 54 #define AT803X_INTR_ENABLE_LINK_SUCCESS BIT(10) 55 #define AT803X_INTR_ENABLE_LINK_FAIL_BX BIT(8) 56 #define AT803X_INTR_ENABLE_LINK_SUCCESS_BX BIT(7) 57 #define AT803X_INTR_ENABLE_WIRESPEED_DOWNGRADE BIT(5) 58 #define AT803X_INTR_ENABLE_POLARITY_CHANGED BIT(1) 59 #define AT803X_INTR_ENABLE_WOL BIT(0) 60 61 #define AT803X_INTR_STATUS 0x13 62 63 #define AT803X_SMART_SPEED 0x14 64 #define AT803X_SMART_SPEED_ENABLE BIT(5) 65 #define AT803X_SMART_SPEED_RETRY_LIMIT_MASK GENMASK(4, 2) 66 #define AT803X_SMART_SPEED_BYPASS_TIMER BIT(1) 67 #define AT803X_CDT 0x16 68 #define AT803X_CDT_MDI_PAIR_MASK GENMASK(9, 8) 69 #define AT803X_CDT_ENABLE_TEST BIT(0) 70 #define AT803X_CDT_STATUS 0x1c 71 #define AT803X_CDT_STATUS_STAT_NORMAL 0 72 #define AT803X_CDT_STATUS_STAT_SHORT 1 73 #define AT803X_CDT_STATUS_STAT_OPEN 2 74 #define AT803X_CDT_STATUS_STAT_FAIL 3 75 #define AT803X_CDT_STATUS_STAT_MASK GENMASK(9, 8) 76 #define AT803X_CDT_STATUS_DELTA_TIME_MASK GENMASK(7, 0) 77 #define AT803X_LED_CONTROL 0x18 78 79 #define AT803X_PHY_MMD3_WOL_CTRL 0x8012 80 #define AT803X_WOL_EN BIT(5) 81 #define AT803X_LOC_MAC_ADDR_0_15_OFFSET 0x804C 82 #define AT803X_LOC_MAC_ADDR_16_31_OFFSET 0x804B 83 #define AT803X_LOC_MAC_ADDR_32_47_OFFSET 0x804A 84 #define AT803X_REG_CHIP_CONFIG 0x1f 85 #define AT803X_BT_BX_REG_SEL 0x8000 86 87 #define AT803X_DEBUG_ADDR 0x1D 88 #define AT803X_DEBUG_DATA 0x1E 89 90 #define AT803X_MODE_CFG_MASK 0x0F 91 #define AT803X_MODE_CFG_BASET_RGMII 0x00 92 #define AT803X_MODE_CFG_BASET_SGMII 0x01 93 #define AT803X_MODE_CFG_BX1000_RGMII_50OHM 0x02 94 #define AT803X_MODE_CFG_BX1000_RGMII_75OHM 0x03 95 #define AT803X_MODE_CFG_BX1000_CONV_50OHM 0x04 96 #define AT803X_MODE_CFG_BX1000_CONV_75OHM 0x05 97 #define AT803X_MODE_CFG_FX100_RGMII_50OHM 0x06 98 #define AT803X_MODE_CFG_FX100_CONV_50OHM 0x07 99 #define AT803X_MODE_CFG_RGMII_AUTO_MDET 0x0B 100 #define AT803X_MODE_CFG_FX100_RGMII_75OHM 0x0E 101 #define AT803X_MODE_CFG_FX100_CONV_75OHM 0x0F 102 103 #define AT803X_PSSR 0x11 /*PHY-Specific Status Register*/ 104 #define AT803X_PSSR_MR_AN_COMPLETE 0x0200 105 106 #define AT803X_DEBUG_ANALOG_TEST_CTRL 0x00 107 #define QCA8327_DEBUG_MANU_CTRL_EN BIT(2) 108 #define QCA8337_DEBUG_MANU_CTRL_EN GENMASK(3, 2) 109 #define AT803X_DEBUG_RX_CLK_DLY_EN BIT(15) 110 111 #define AT803X_DEBUG_SYSTEM_CTRL_MODE 0x05 112 #define AT803X_DEBUG_TX_CLK_DLY_EN BIT(8) 113 114 #define AT803X_DEBUG_REG_HIB_CTRL 0x0b 115 #define AT803X_DEBUG_HIB_CTRL_SEL_RST_80U BIT(10) 116 #define AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE BIT(13) 117 #define AT803X_DEBUG_HIB_CTRL_PS_HIB_EN BIT(15) 118 119 #define AT803X_DEBUG_REG_3C 0x3C 120 121 #define AT803X_DEBUG_REG_GREEN 0x3D 122 #define AT803X_DEBUG_GATE_CLK_IN1000 BIT(6) 123 124 #define AT803X_DEBUG_REG_1F 0x1F 125 #define AT803X_DEBUG_PLL_ON BIT(2) 126 #define AT803X_DEBUG_RGMII_1V8 BIT(3) 127 128 #define MDIO_AZ_DEBUG 0x800D 129 130 /* AT803x supports either the XTAL input pad, an internal PLL or the 131 * DSP as clock reference for the clock output pad. The XTAL reference 132 * is only used for 25 MHz output, all other frequencies need the PLL. 133 * The DSP as a clock reference is used in synchronous ethernet 134 * applications. 135 * 136 * By default the PLL is only enabled if there is a link. Otherwise 137 * the PHY will go into low power state and disabled the PLL. You can 138 * set the PLL_ON bit (see debug register 0x1f) to keep the PLL always 139 * enabled. 140 */ 141 #define AT803X_MMD7_CLK25M 0x8016 142 #define AT803X_CLK_OUT_MASK GENMASK(4, 2) 143 #define AT803X_CLK_OUT_25MHZ_XTAL 0 144 #define AT803X_CLK_OUT_25MHZ_DSP 1 145 #define AT803X_CLK_OUT_50MHZ_PLL 2 146 #define AT803X_CLK_OUT_50MHZ_DSP 3 147 #define AT803X_CLK_OUT_62_5MHZ_PLL 4 148 #define AT803X_CLK_OUT_62_5MHZ_DSP 5 149 #define AT803X_CLK_OUT_125MHZ_PLL 6 150 #define AT803X_CLK_OUT_125MHZ_DSP 7 151 152 /* The AR8035 has another mask which is compatible with the AR8031/AR8033 mask 153 * but doesn't support choosing between XTAL/PLL and DSP. 154 */ 155 #define AT8035_CLK_OUT_MASK GENMASK(4, 3) 156 157 #define AT803X_CLK_OUT_STRENGTH_MASK GENMASK(8, 7) 158 #define AT803X_CLK_OUT_STRENGTH_FULL 0 159 #define AT803X_CLK_OUT_STRENGTH_HALF 1 160 #define AT803X_CLK_OUT_STRENGTH_QUARTER 2 161 162 #define AT803X_DEFAULT_DOWNSHIFT 5 163 #define AT803X_MIN_DOWNSHIFT 2 164 #define AT803X_MAX_DOWNSHIFT 9 165 166 #define AT803X_MMD3_SMARTEEE_CTL1 0x805b 167 #define AT803X_MMD3_SMARTEEE_CTL2 0x805c 168 #define AT803X_MMD3_SMARTEEE_CTL3 0x805d 169 #define AT803X_MMD3_SMARTEEE_CTL3_LPI_EN BIT(8) 170 171 #define ATH9331_PHY_ID 0x004dd041 172 #define ATH8030_PHY_ID 0x004dd076 173 #define ATH8031_PHY_ID 0x004dd074 174 #define ATH8032_PHY_ID 0x004dd023 175 #define ATH8035_PHY_ID 0x004dd072 176 #define AT8030_PHY_ID_MASK 0xffffffef 177 178 #define QCA8081_PHY_ID 0x004dd101 179 180 #define QCA8327_A_PHY_ID 0x004dd033 181 #define QCA8327_B_PHY_ID 0x004dd034 182 #define QCA8337_PHY_ID 0x004dd036 183 #define QCA9561_PHY_ID 0x004dd042 184 #define QCA8K_PHY_ID_MASK 0xffffffff 185 186 #define QCA8K_DEVFLAGS_REVISION_MASK GENMASK(2, 0) 187 188 #define AT803X_PAGE_FIBER 0 189 #define AT803X_PAGE_COPPER 1 190 191 /* don't turn off internal PLL */ 192 #define AT803X_KEEP_PLL_ENABLED BIT(0) 193 #define AT803X_DISABLE_SMARTEEE BIT(1) 194 195 /* disable hibernation mode */ 196 #define AT803X_DISABLE_HIBERNATION_MODE BIT(2) 197 198 /* ADC threshold */ 199 #define QCA808X_PHY_DEBUG_ADC_THRESHOLD 0x2c80 200 #define QCA808X_ADC_THRESHOLD_MASK GENMASK(7, 0) 201 #define QCA808X_ADC_THRESHOLD_80MV 0 202 #define QCA808X_ADC_THRESHOLD_100MV 0xf0 203 #define QCA808X_ADC_THRESHOLD_200MV 0x0f 204 #define QCA808X_ADC_THRESHOLD_300MV 0xff 205 206 /* CLD control */ 207 #define QCA808X_PHY_MMD3_ADDR_CLD_CTRL7 0x8007 208 #define QCA808X_8023AZ_AFE_CTRL_MASK GENMASK(8, 4) 209 #define QCA808X_8023AZ_AFE_EN 0x90 210 211 /* AZ control */ 212 #define QCA808X_PHY_MMD3_AZ_TRAINING_CTRL 0x8008 213 #define QCA808X_MMD3_AZ_TRAINING_VAL 0x1c32 214 215 #define QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB 0x8014 216 #define QCA808X_MSE_THRESHOLD_20DB_VALUE 0x529 217 218 #define QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB 0x800E 219 #define QCA808X_MSE_THRESHOLD_17DB_VALUE 0x341 220 221 #define QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB 0x801E 222 #define QCA808X_MSE_THRESHOLD_27DB_VALUE 0x419 223 224 #define QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB 0x8020 225 #define QCA808X_MSE_THRESHOLD_28DB_VALUE 0x341 226 227 #define QCA808X_PHY_MMD7_TOP_OPTION1 0x901c 228 #define QCA808X_TOP_OPTION1_DATA 0x0 229 230 #define QCA808X_PHY_MMD3_DEBUG_1 0xa100 231 #define QCA808X_MMD3_DEBUG_1_VALUE 0x9203 232 #define QCA808X_PHY_MMD3_DEBUG_2 0xa101 233 #define QCA808X_MMD3_DEBUG_2_VALUE 0x48ad 234 #define QCA808X_PHY_MMD3_DEBUG_3 0xa103 235 #define QCA808X_MMD3_DEBUG_3_VALUE 0x1698 236 #define QCA808X_PHY_MMD3_DEBUG_4 0xa105 237 #define QCA808X_MMD3_DEBUG_4_VALUE 0x8001 238 #define QCA808X_PHY_MMD3_DEBUG_5 0xa106 239 #define QCA808X_MMD3_DEBUG_5_VALUE 0x1111 240 #define QCA808X_PHY_MMD3_DEBUG_6 0xa011 241 #define QCA808X_MMD3_DEBUG_6_VALUE 0x5f85 242 243 /* master/slave seed config */ 244 #define QCA808X_PHY_DEBUG_LOCAL_SEED 9 245 #define QCA808X_MASTER_SLAVE_SEED_ENABLE BIT(1) 246 #define QCA808X_MASTER_SLAVE_SEED_CFG GENMASK(12, 2) 247 #define QCA808X_MASTER_SLAVE_SEED_RANGE 0x32 248 249 /* Hibernation yields lower power consumpiton in contrast with normal operation mode. 250 * when the copper cable is unplugged, the PHY enters into hibernation mode in about 10s. 251 */ 252 #define QCA808X_DBG_AN_TEST 0xb 253 #define QCA808X_HIBERNATION_EN BIT(15) 254 255 #define QCA808X_CDT_ENABLE_TEST BIT(15) 256 #define QCA808X_CDT_INTER_CHECK_DIS BIT(13) 257 #define QCA808X_CDT_LENGTH_UNIT BIT(10) 258 259 #define QCA808X_MMD3_CDT_STATUS 0x8064 260 #define QCA808X_MMD3_CDT_DIAG_PAIR_A 0x8065 261 #define QCA808X_MMD3_CDT_DIAG_PAIR_B 0x8066 262 #define QCA808X_MMD3_CDT_DIAG_PAIR_C 0x8067 263 #define QCA808X_MMD3_CDT_DIAG_PAIR_D 0x8068 264 #define QCA808X_CDT_DIAG_LENGTH GENMASK(7, 0) 265 266 #define QCA808X_CDT_CODE_PAIR_A GENMASK(15, 12) 267 #define QCA808X_CDT_CODE_PAIR_B GENMASK(11, 8) 268 #define QCA808X_CDT_CODE_PAIR_C GENMASK(7, 4) 269 #define QCA808X_CDT_CODE_PAIR_D GENMASK(3, 0) 270 #define QCA808X_CDT_STATUS_STAT_FAIL 0 271 #define QCA808X_CDT_STATUS_STAT_NORMAL 1 272 #define QCA808X_CDT_STATUS_STAT_OPEN 2 273 #define QCA808X_CDT_STATUS_STAT_SHORT 3 274 275 MODULE_DESCRIPTION("Qualcomm Atheros AR803x and QCA808X PHY driver"); 276 MODULE_AUTHOR("Matus Ujhelyi"); 277 MODULE_LICENSE("GPL"); 278 279 enum stat_access_type { 280 PHY, 281 MMD 282 }; 283 284 struct at803x_hw_stat { 285 const char *string; 286 u8 reg; 287 u32 mask; 288 enum stat_access_type access_type; 289 }; 290 291 static struct at803x_hw_stat at803x_hw_stats[] = { 292 { "phy_idle_errors", 0xa, GENMASK(7, 0), PHY}, 293 { "phy_receive_errors", 0x15, GENMASK(15, 0), PHY}, 294 { "eee_wake_errors", 0x16, GENMASK(15, 0), MMD}, 295 }; 296 297 struct at803x_priv { 298 int flags; 299 u16 clk_25m_reg; 300 u16 clk_25m_mask; 301 u8 smarteee_lpi_tw_1g; 302 u8 smarteee_lpi_tw_100m; 303 bool is_fiber; 304 bool is_1000basex; 305 struct regulator_dev *vddio_rdev; 306 struct regulator_dev *vddh_rdev; 307 u64 stats[ARRAY_SIZE(at803x_hw_stats)]; 308 }; 309 310 struct at803x_context { 311 u16 bmcr; 312 u16 advertise; 313 u16 control1000; 314 u16 int_enable; 315 u16 smart_speed; 316 u16 led_control; 317 }; 318 319 static int at803x_debug_reg_write(struct phy_device *phydev, u16 reg, u16 data) 320 { 321 int ret; 322 323 ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg); 324 if (ret < 0) 325 return ret; 326 327 return phy_write(phydev, AT803X_DEBUG_DATA, data); 328 } 329 330 static int at803x_debug_reg_read(struct phy_device *phydev, u16 reg) 331 { 332 int ret; 333 334 ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg); 335 if (ret < 0) 336 return ret; 337 338 return phy_read(phydev, AT803X_DEBUG_DATA); 339 } 340 341 static int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg, 342 u16 clear, u16 set) 343 { 344 u16 val; 345 int ret; 346 347 ret = at803x_debug_reg_read(phydev, reg); 348 if (ret < 0) 349 return ret; 350 351 val = ret & 0xffff; 352 val &= ~clear; 353 val |= set; 354 355 return phy_write(phydev, AT803X_DEBUG_DATA, val); 356 } 357 358 static int at803x_write_page(struct phy_device *phydev, int page) 359 { 360 int mask; 361 int set; 362 363 if (page == AT803X_PAGE_COPPER) { 364 set = AT803X_BT_BX_REG_SEL; 365 mask = 0; 366 } else { 367 set = 0; 368 mask = AT803X_BT_BX_REG_SEL; 369 } 370 371 return __phy_modify(phydev, AT803X_REG_CHIP_CONFIG, mask, set); 372 } 373 374 static int at803x_read_page(struct phy_device *phydev) 375 { 376 int ccr = __phy_read(phydev, AT803X_REG_CHIP_CONFIG); 377 378 if (ccr < 0) 379 return ccr; 380 381 if (ccr & AT803X_BT_BX_REG_SEL) 382 return AT803X_PAGE_COPPER; 383 384 return AT803X_PAGE_FIBER; 385 } 386 387 static int at803x_enable_rx_delay(struct phy_device *phydev) 388 { 389 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0, 390 AT803X_DEBUG_RX_CLK_DLY_EN); 391 } 392 393 static int at803x_enable_tx_delay(struct phy_device *phydev) 394 { 395 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0, 396 AT803X_DEBUG_TX_CLK_DLY_EN); 397 } 398 399 static int at803x_disable_rx_delay(struct phy_device *phydev) 400 { 401 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 402 AT803X_DEBUG_RX_CLK_DLY_EN, 0); 403 } 404 405 static int at803x_disable_tx_delay(struct phy_device *phydev) 406 { 407 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 408 AT803X_DEBUG_TX_CLK_DLY_EN, 0); 409 } 410 411 /* save relevant PHY registers to private copy */ 412 static void at803x_context_save(struct phy_device *phydev, 413 struct at803x_context *context) 414 { 415 context->bmcr = phy_read(phydev, MII_BMCR); 416 context->advertise = phy_read(phydev, MII_ADVERTISE); 417 context->control1000 = phy_read(phydev, MII_CTRL1000); 418 context->int_enable = phy_read(phydev, AT803X_INTR_ENABLE); 419 context->smart_speed = phy_read(phydev, AT803X_SMART_SPEED); 420 context->led_control = phy_read(phydev, AT803X_LED_CONTROL); 421 } 422 423 /* restore relevant PHY registers from private copy */ 424 static void at803x_context_restore(struct phy_device *phydev, 425 const struct at803x_context *context) 426 { 427 phy_write(phydev, MII_BMCR, context->bmcr); 428 phy_write(phydev, MII_ADVERTISE, context->advertise); 429 phy_write(phydev, MII_CTRL1000, context->control1000); 430 phy_write(phydev, AT803X_INTR_ENABLE, context->int_enable); 431 phy_write(phydev, AT803X_SMART_SPEED, context->smart_speed); 432 phy_write(phydev, AT803X_LED_CONTROL, context->led_control); 433 } 434 435 static int at803x_set_wol(struct phy_device *phydev, 436 struct ethtool_wolinfo *wol) 437 { 438 int ret, irq_enabled; 439 440 if (wol->wolopts & WAKE_MAGIC) { 441 struct net_device *ndev = phydev->attached_dev; 442 const u8 *mac; 443 unsigned int i; 444 static const unsigned int offsets[] = { 445 AT803X_LOC_MAC_ADDR_32_47_OFFSET, 446 AT803X_LOC_MAC_ADDR_16_31_OFFSET, 447 AT803X_LOC_MAC_ADDR_0_15_OFFSET, 448 }; 449 450 if (!ndev) 451 return -ENODEV; 452 453 mac = (const u8 *) ndev->dev_addr; 454 455 if (!is_valid_ether_addr(mac)) 456 return -EINVAL; 457 458 for (i = 0; i < 3; i++) 459 phy_write_mmd(phydev, MDIO_MMD_PCS, offsets[i], 460 mac[(i * 2) + 1] | (mac[(i * 2)] << 8)); 461 462 /* Enable WOL function */ 463 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_PHY_MMD3_WOL_CTRL, 464 0, AT803X_WOL_EN); 465 if (ret) 466 return ret; 467 /* Enable WOL interrupt */ 468 ret = phy_modify(phydev, AT803X_INTR_ENABLE, 0, AT803X_INTR_ENABLE_WOL); 469 if (ret) 470 return ret; 471 } else { 472 /* Disable WoL function */ 473 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_PHY_MMD3_WOL_CTRL, 474 AT803X_WOL_EN, 0); 475 if (ret) 476 return ret; 477 /* Disable WOL interrupt */ 478 ret = phy_modify(phydev, AT803X_INTR_ENABLE, AT803X_INTR_ENABLE_WOL, 0); 479 if (ret) 480 return ret; 481 } 482 483 /* Clear WOL status */ 484 ret = phy_read(phydev, AT803X_INTR_STATUS); 485 if (ret < 0) 486 return ret; 487 488 /* Check if there are other interrupts except for WOL triggered when PHY is 489 * in interrupt mode, only the interrupts enabled by AT803X_INTR_ENABLE can 490 * be passed up to the interrupt PIN. 491 */ 492 irq_enabled = phy_read(phydev, AT803X_INTR_ENABLE); 493 if (irq_enabled < 0) 494 return irq_enabled; 495 496 irq_enabled &= ~AT803X_INTR_ENABLE_WOL; 497 if (ret & irq_enabled && !phy_polling_mode(phydev)) 498 phy_trigger_machine(phydev); 499 500 return 0; 501 } 502 503 static void at803x_get_wol(struct phy_device *phydev, 504 struct ethtool_wolinfo *wol) 505 { 506 int value; 507 508 wol->supported = WAKE_MAGIC; 509 wol->wolopts = 0; 510 511 value = phy_read_mmd(phydev, MDIO_MMD_PCS, AT803X_PHY_MMD3_WOL_CTRL); 512 if (value < 0) 513 return; 514 515 if (value & AT803X_WOL_EN) 516 wol->wolopts |= WAKE_MAGIC; 517 } 518 519 static int at803x_get_sset_count(struct phy_device *phydev) 520 { 521 return ARRAY_SIZE(at803x_hw_stats); 522 } 523 524 static void at803x_get_strings(struct phy_device *phydev, u8 *data) 525 { 526 int i; 527 528 for (i = 0; i < ARRAY_SIZE(at803x_hw_stats); i++) { 529 strscpy(data + i * ETH_GSTRING_LEN, 530 at803x_hw_stats[i].string, ETH_GSTRING_LEN); 531 } 532 } 533 534 static u64 at803x_get_stat(struct phy_device *phydev, int i) 535 { 536 struct at803x_hw_stat stat = at803x_hw_stats[i]; 537 struct at803x_priv *priv = phydev->priv; 538 int val; 539 u64 ret; 540 541 if (stat.access_type == MMD) 542 val = phy_read_mmd(phydev, MDIO_MMD_PCS, stat.reg); 543 else 544 val = phy_read(phydev, stat.reg); 545 546 if (val < 0) { 547 ret = U64_MAX; 548 } else { 549 val = val & stat.mask; 550 priv->stats[i] += val; 551 ret = priv->stats[i]; 552 } 553 554 return ret; 555 } 556 557 static void at803x_get_stats(struct phy_device *phydev, 558 struct ethtool_stats *stats, u64 *data) 559 { 560 int i; 561 562 for (i = 0; i < ARRAY_SIZE(at803x_hw_stats); i++) 563 data[i] = at803x_get_stat(phydev, i); 564 } 565 566 static int at803x_suspend(struct phy_device *phydev) 567 { 568 int value; 569 int wol_enabled; 570 571 value = phy_read(phydev, AT803X_INTR_ENABLE); 572 wol_enabled = value & AT803X_INTR_ENABLE_WOL; 573 574 if (wol_enabled) 575 value = BMCR_ISOLATE; 576 else 577 value = BMCR_PDOWN; 578 579 phy_modify(phydev, MII_BMCR, 0, value); 580 581 return 0; 582 } 583 584 static int at803x_resume(struct phy_device *phydev) 585 { 586 return phy_modify(phydev, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE, 0); 587 } 588 589 static int at803x_rgmii_reg_set_voltage_sel(struct regulator_dev *rdev, 590 unsigned int selector) 591 { 592 struct phy_device *phydev = rdev_get_drvdata(rdev); 593 594 if (selector) 595 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 596 0, AT803X_DEBUG_RGMII_1V8); 597 else 598 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 599 AT803X_DEBUG_RGMII_1V8, 0); 600 } 601 602 static int at803x_rgmii_reg_get_voltage_sel(struct regulator_dev *rdev) 603 { 604 struct phy_device *phydev = rdev_get_drvdata(rdev); 605 int val; 606 607 val = at803x_debug_reg_read(phydev, AT803X_DEBUG_REG_1F); 608 if (val < 0) 609 return val; 610 611 return (val & AT803X_DEBUG_RGMII_1V8) ? 1 : 0; 612 } 613 614 static const struct regulator_ops vddio_regulator_ops = { 615 .list_voltage = regulator_list_voltage_table, 616 .set_voltage_sel = at803x_rgmii_reg_set_voltage_sel, 617 .get_voltage_sel = at803x_rgmii_reg_get_voltage_sel, 618 }; 619 620 static const unsigned int vddio_voltage_table[] = { 621 1500000, 622 1800000, 623 }; 624 625 static const struct regulator_desc vddio_desc = { 626 .name = "vddio", 627 .of_match = of_match_ptr("vddio-regulator"), 628 .n_voltages = ARRAY_SIZE(vddio_voltage_table), 629 .volt_table = vddio_voltage_table, 630 .ops = &vddio_regulator_ops, 631 .type = REGULATOR_VOLTAGE, 632 .owner = THIS_MODULE, 633 }; 634 635 static const struct regulator_ops vddh_regulator_ops = { 636 }; 637 638 static const struct regulator_desc vddh_desc = { 639 .name = "vddh", 640 .of_match = of_match_ptr("vddh-regulator"), 641 .n_voltages = 1, 642 .fixed_uV = 2500000, 643 .ops = &vddh_regulator_ops, 644 .type = REGULATOR_VOLTAGE, 645 .owner = THIS_MODULE, 646 }; 647 648 static int at8031_register_regulators(struct phy_device *phydev) 649 { 650 struct at803x_priv *priv = phydev->priv; 651 struct device *dev = &phydev->mdio.dev; 652 struct regulator_config config = { }; 653 654 config.dev = dev; 655 config.driver_data = phydev; 656 657 priv->vddio_rdev = devm_regulator_register(dev, &vddio_desc, &config); 658 if (IS_ERR(priv->vddio_rdev)) { 659 phydev_err(phydev, "failed to register VDDIO regulator\n"); 660 return PTR_ERR(priv->vddio_rdev); 661 } 662 663 priv->vddh_rdev = devm_regulator_register(dev, &vddh_desc, &config); 664 if (IS_ERR(priv->vddh_rdev)) { 665 phydev_err(phydev, "failed to register VDDH regulator\n"); 666 return PTR_ERR(priv->vddh_rdev); 667 } 668 669 return 0; 670 } 671 672 static int at803x_sfp_insert(void *upstream, const struct sfp_eeprom_id *id) 673 { 674 struct phy_device *phydev = upstream; 675 __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_support); 676 __ETHTOOL_DECLARE_LINK_MODE_MASK(sfp_support); 677 DECLARE_PHY_INTERFACE_MASK(interfaces); 678 phy_interface_t iface; 679 680 linkmode_zero(phy_support); 681 phylink_set(phy_support, 1000baseX_Full); 682 phylink_set(phy_support, 1000baseT_Full); 683 phylink_set(phy_support, Autoneg); 684 phylink_set(phy_support, Pause); 685 phylink_set(phy_support, Asym_Pause); 686 687 linkmode_zero(sfp_support); 688 sfp_parse_support(phydev->sfp_bus, id, sfp_support, interfaces); 689 /* Some modules support 10G modes as well as others we support. 690 * Mask out non-supported modes so the correct interface is picked. 691 */ 692 linkmode_and(sfp_support, phy_support, sfp_support); 693 694 if (linkmode_empty(sfp_support)) { 695 dev_err(&phydev->mdio.dev, "incompatible SFP module inserted\n"); 696 return -EINVAL; 697 } 698 699 iface = sfp_select_interface(phydev->sfp_bus, sfp_support); 700 701 /* Only 1000Base-X is supported by AR8031/8033 as the downstream SerDes 702 * interface for use with SFP modules. 703 * However, some copper modules detected as having a preferred SGMII 704 * interface do default to and function in 1000Base-X mode, so just 705 * print a warning and allow such modules, as they may have some chance 706 * of working. 707 */ 708 if (iface == PHY_INTERFACE_MODE_SGMII) 709 dev_warn(&phydev->mdio.dev, "module may not function if 1000Base-X not supported\n"); 710 else if (iface != PHY_INTERFACE_MODE_1000BASEX) 711 return -EINVAL; 712 713 return 0; 714 } 715 716 static const struct sfp_upstream_ops at803x_sfp_ops = { 717 .attach = phy_sfp_attach, 718 .detach = phy_sfp_detach, 719 .module_insert = at803x_sfp_insert, 720 }; 721 722 static int at803x_parse_dt(struct phy_device *phydev) 723 { 724 struct device_node *node = phydev->mdio.dev.of_node; 725 struct at803x_priv *priv = phydev->priv; 726 u32 freq, strength, tw; 727 unsigned int sel; 728 int ret; 729 730 if (!IS_ENABLED(CONFIG_OF_MDIO)) 731 return 0; 732 733 if (of_property_read_bool(node, "qca,disable-smarteee")) 734 priv->flags |= AT803X_DISABLE_SMARTEEE; 735 736 if (of_property_read_bool(node, "qca,disable-hibernation-mode")) 737 priv->flags |= AT803X_DISABLE_HIBERNATION_MODE; 738 739 if (!of_property_read_u32(node, "qca,smarteee-tw-us-1g", &tw)) { 740 if (!tw || tw > 255) { 741 phydev_err(phydev, "invalid qca,smarteee-tw-us-1g\n"); 742 return -EINVAL; 743 } 744 priv->smarteee_lpi_tw_1g = tw; 745 } 746 747 if (!of_property_read_u32(node, "qca,smarteee-tw-us-100m", &tw)) { 748 if (!tw || tw > 255) { 749 phydev_err(phydev, "invalid qca,smarteee-tw-us-100m\n"); 750 return -EINVAL; 751 } 752 priv->smarteee_lpi_tw_100m = tw; 753 } 754 755 ret = of_property_read_u32(node, "qca,clk-out-frequency", &freq); 756 if (!ret) { 757 switch (freq) { 758 case 25000000: 759 sel = AT803X_CLK_OUT_25MHZ_XTAL; 760 break; 761 case 50000000: 762 sel = AT803X_CLK_OUT_50MHZ_PLL; 763 break; 764 case 62500000: 765 sel = AT803X_CLK_OUT_62_5MHZ_PLL; 766 break; 767 case 125000000: 768 sel = AT803X_CLK_OUT_125MHZ_PLL; 769 break; 770 default: 771 phydev_err(phydev, "invalid qca,clk-out-frequency\n"); 772 return -EINVAL; 773 } 774 775 priv->clk_25m_reg |= FIELD_PREP(AT803X_CLK_OUT_MASK, sel); 776 priv->clk_25m_mask |= AT803X_CLK_OUT_MASK; 777 778 /* Fixup for the AR8030/AR8035. This chip has another mask and 779 * doesn't support the DSP reference. Eg. the lowest bit of the 780 * mask. The upper two bits select the same frequencies. Mask 781 * the lowest bit here. 782 * 783 * Warning: 784 * There was no datasheet for the AR8030 available so this is 785 * just a guess. But the AR8035 is listed as pin compatible 786 * to the AR8030 so there might be a good chance it works on 787 * the AR8030 too. 788 */ 789 if (phydev->drv->phy_id == ATH8030_PHY_ID || 790 phydev->drv->phy_id == ATH8035_PHY_ID) { 791 priv->clk_25m_reg &= AT8035_CLK_OUT_MASK; 792 priv->clk_25m_mask &= AT8035_CLK_OUT_MASK; 793 } 794 } 795 796 ret = of_property_read_u32(node, "qca,clk-out-strength", &strength); 797 if (!ret) { 798 priv->clk_25m_mask |= AT803X_CLK_OUT_STRENGTH_MASK; 799 switch (strength) { 800 case AR803X_STRENGTH_FULL: 801 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_FULL; 802 break; 803 case AR803X_STRENGTH_HALF: 804 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_HALF; 805 break; 806 case AR803X_STRENGTH_QUARTER: 807 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_QUARTER; 808 break; 809 default: 810 phydev_err(phydev, "invalid qca,clk-out-strength\n"); 811 return -EINVAL; 812 } 813 } 814 815 /* Only supported on AR8031/AR8033, the AR8030/AR8035 use strapping 816 * options. 817 */ 818 if (phydev->drv->phy_id == ATH8031_PHY_ID) { 819 if (of_property_read_bool(node, "qca,keep-pll-enabled")) 820 priv->flags |= AT803X_KEEP_PLL_ENABLED; 821 822 ret = at8031_register_regulators(phydev); 823 if (ret < 0) 824 return ret; 825 826 ret = devm_regulator_get_enable_optional(&phydev->mdio.dev, 827 "vddio"); 828 if (ret) { 829 phydev_err(phydev, "failed to get VDDIO regulator\n"); 830 return ret; 831 } 832 833 /* Only AR8031/8033 support 1000Base-X for SFP modules */ 834 ret = phy_sfp_probe(phydev, &at803x_sfp_ops); 835 if (ret < 0) 836 return ret; 837 } 838 839 return 0; 840 } 841 842 static int at803x_probe(struct phy_device *phydev) 843 { 844 struct device *dev = &phydev->mdio.dev; 845 struct at803x_priv *priv; 846 int ret; 847 848 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 849 if (!priv) 850 return -ENOMEM; 851 852 phydev->priv = priv; 853 854 ret = at803x_parse_dt(phydev); 855 if (ret) 856 return ret; 857 858 if (phydev->drv->phy_id == ATH8031_PHY_ID) { 859 int ccr = phy_read(phydev, AT803X_REG_CHIP_CONFIG); 860 int mode_cfg; 861 struct ethtool_wolinfo wol = { 862 .wolopts = 0, 863 }; 864 865 if (ccr < 0) 866 return ccr; 867 mode_cfg = ccr & AT803X_MODE_CFG_MASK; 868 869 switch (mode_cfg) { 870 case AT803X_MODE_CFG_BX1000_RGMII_50OHM: 871 case AT803X_MODE_CFG_BX1000_RGMII_75OHM: 872 priv->is_1000basex = true; 873 fallthrough; 874 case AT803X_MODE_CFG_FX100_RGMII_50OHM: 875 case AT803X_MODE_CFG_FX100_RGMII_75OHM: 876 priv->is_fiber = true; 877 break; 878 } 879 880 /* Disable WOL by default */ 881 ret = at803x_set_wol(phydev, &wol); 882 if (ret < 0) { 883 phydev_err(phydev, "failed to disable WOL on probe: %d\n", ret); 884 return ret; 885 } 886 } 887 888 return 0; 889 } 890 891 static int at803x_get_features(struct phy_device *phydev) 892 { 893 struct at803x_priv *priv = phydev->priv; 894 int err; 895 896 err = genphy_read_abilities(phydev); 897 if (err) 898 return err; 899 900 if (phydev->drv->phy_id == QCA8081_PHY_ID) { 901 err = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_NG_EXTABLE); 902 if (err < 0) 903 return err; 904 905 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported, 906 err & MDIO_PMA_NG_EXTABLE_2_5GBT); 907 } 908 909 if (phydev->drv->phy_id != ATH8031_PHY_ID) 910 return 0; 911 912 /* AR8031/AR8033 have different status registers 913 * for copper and fiber operation. However, the 914 * extended status register is the same for both 915 * operation modes. 916 * 917 * As a result of that, ESTATUS_1000_XFULL is set 918 * to 1 even when operating in copper TP mode. 919 * 920 * Remove this mode from the supported link modes 921 * when not operating in 1000BaseX mode. 922 */ 923 if (!priv->is_1000basex) 924 linkmode_clear_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 925 phydev->supported); 926 927 return 0; 928 } 929 930 static int at803x_smarteee_config(struct phy_device *phydev) 931 { 932 struct at803x_priv *priv = phydev->priv; 933 u16 mask = 0, val = 0; 934 int ret; 935 936 if (priv->flags & AT803X_DISABLE_SMARTEEE) 937 return phy_modify_mmd(phydev, MDIO_MMD_PCS, 938 AT803X_MMD3_SMARTEEE_CTL3, 939 AT803X_MMD3_SMARTEEE_CTL3_LPI_EN, 0); 940 941 if (priv->smarteee_lpi_tw_1g) { 942 mask |= 0xff00; 943 val |= priv->smarteee_lpi_tw_1g << 8; 944 } 945 if (priv->smarteee_lpi_tw_100m) { 946 mask |= 0x00ff; 947 val |= priv->smarteee_lpi_tw_100m; 948 } 949 if (!mask) 950 return 0; 951 952 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL1, 953 mask, val); 954 if (ret) 955 return ret; 956 957 return phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL3, 958 AT803X_MMD3_SMARTEEE_CTL3_LPI_EN, 959 AT803X_MMD3_SMARTEEE_CTL3_LPI_EN); 960 } 961 962 static int at803x_clk_out_config(struct phy_device *phydev) 963 { 964 struct at803x_priv *priv = phydev->priv; 965 966 if (!priv->clk_25m_mask) 967 return 0; 968 969 return phy_modify_mmd(phydev, MDIO_MMD_AN, AT803X_MMD7_CLK25M, 970 priv->clk_25m_mask, priv->clk_25m_reg); 971 } 972 973 static int at8031_pll_config(struct phy_device *phydev) 974 { 975 struct at803x_priv *priv = phydev->priv; 976 977 /* The default after hardware reset is PLL OFF. After a soft reset, the 978 * values are retained. 979 */ 980 if (priv->flags & AT803X_KEEP_PLL_ENABLED) 981 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 982 0, AT803X_DEBUG_PLL_ON); 983 else 984 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 985 AT803X_DEBUG_PLL_ON, 0); 986 } 987 988 static int at803x_hibernation_mode_config(struct phy_device *phydev) 989 { 990 struct at803x_priv *priv = phydev->priv; 991 992 /* The default after hardware reset is hibernation mode enabled. After 993 * software reset, the value is retained. 994 */ 995 if (!(priv->flags & AT803X_DISABLE_HIBERNATION_MODE)) 996 return 0; 997 998 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL, 999 AT803X_DEBUG_HIB_CTRL_PS_HIB_EN, 0); 1000 } 1001 1002 static int at803x_config_init(struct phy_device *phydev) 1003 { 1004 struct at803x_priv *priv = phydev->priv; 1005 int ret; 1006 1007 if (phydev->drv->phy_id == ATH8031_PHY_ID) { 1008 /* Some bootloaders leave the fiber page selected. 1009 * Switch to the appropriate page (fiber or copper), as otherwise we 1010 * read the PHY capabilities from the wrong page. 1011 */ 1012 phy_lock_mdio_bus(phydev); 1013 ret = at803x_write_page(phydev, 1014 priv->is_fiber ? AT803X_PAGE_FIBER : 1015 AT803X_PAGE_COPPER); 1016 phy_unlock_mdio_bus(phydev); 1017 if (ret) 1018 return ret; 1019 1020 ret = at8031_pll_config(phydev); 1021 if (ret < 0) 1022 return ret; 1023 } 1024 1025 /* The RX and TX delay default is: 1026 * after HW reset: RX delay enabled and TX delay disabled 1027 * after SW reset: RX delay enabled, while TX delay retains the 1028 * value before reset. 1029 */ 1030 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 1031 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) 1032 ret = at803x_enable_rx_delay(phydev); 1033 else 1034 ret = at803x_disable_rx_delay(phydev); 1035 if (ret < 0) 1036 return ret; 1037 1038 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 1039 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) 1040 ret = at803x_enable_tx_delay(phydev); 1041 else 1042 ret = at803x_disable_tx_delay(phydev); 1043 if (ret < 0) 1044 return ret; 1045 1046 ret = at803x_smarteee_config(phydev); 1047 if (ret < 0) 1048 return ret; 1049 1050 ret = at803x_clk_out_config(phydev); 1051 if (ret < 0) 1052 return ret; 1053 1054 ret = at803x_hibernation_mode_config(phydev); 1055 if (ret < 0) 1056 return ret; 1057 1058 /* Ar803x extended next page bit is enabled by default. Cisco 1059 * multigig switches read this bit and attempt to negotiate 10Gbps 1060 * rates even if the next page bit is disabled. This is incorrect 1061 * behaviour but we still need to accommodate it. XNP is only needed 1062 * for 10Gbps support, so disable XNP. 1063 */ 1064 return phy_modify(phydev, MII_ADVERTISE, MDIO_AN_CTRL1_XNP, 0); 1065 } 1066 1067 static int at803x_ack_interrupt(struct phy_device *phydev) 1068 { 1069 int err; 1070 1071 err = phy_read(phydev, AT803X_INTR_STATUS); 1072 1073 return (err < 0) ? err : 0; 1074 } 1075 1076 static int at803x_config_intr(struct phy_device *phydev) 1077 { 1078 struct at803x_priv *priv = phydev->priv; 1079 int err; 1080 int value; 1081 1082 value = phy_read(phydev, AT803X_INTR_ENABLE); 1083 1084 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 1085 /* Clear any pending interrupts */ 1086 err = at803x_ack_interrupt(phydev); 1087 if (err) 1088 return err; 1089 1090 value |= AT803X_INTR_ENABLE_AUTONEG_ERR; 1091 value |= AT803X_INTR_ENABLE_SPEED_CHANGED; 1092 value |= AT803X_INTR_ENABLE_DUPLEX_CHANGED; 1093 value |= AT803X_INTR_ENABLE_LINK_FAIL; 1094 value |= AT803X_INTR_ENABLE_LINK_SUCCESS; 1095 if (priv->is_fiber) { 1096 value |= AT803X_INTR_ENABLE_LINK_FAIL_BX; 1097 value |= AT803X_INTR_ENABLE_LINK_SUCCESS_BX; 1098 } 1099 1100 err = phy_write(phydev, AT803X_INTR_ENABLE, value); 1101 } else { 1102 err = phy_write(phydev, AT803X_INTR_ENABLE, 0); 1103 if (err) 1104 return err; 1105 1106 /* Clear any pending interrupts */ 1107 err = at803x_ack_interrupt(phydev); 1108 } 1109 1110 return err; 1111 } 1112 1113 static irqreturn_t at803x_handle_interrupt(struct phy_device *phydev) 1114 { 1115 int irq_status, int_enabled; 1116 1117 irq_status = phy_read(phydev, AT803X_INTR_STATUS); 1118 if (irq_status < 0) { 1119 phy_error(phydev); 1120 return IRQ_NONE; 1121 } 1122 1123 /* Read the current enabled interrupts */ 1124 int_enabled = phy_read(phydev, AT803X_INTR_ENABLE); 1125 if (int_enabled < 0) { 1126 phy_error(phydev); 1127 return IRQ_NONE; 1128 } 1129 1130 /* See if this was one of our enabled interrupts */ 1131 if (!(irq_status & int_enabled)) 1132 return IRQ_NONE; 1133 1134 phy_trigger_machine(phydev); 1135 1136 return IRQ_HANDLED; 1137 } 1138 1139 static void at803x_link_change_notify(struct phy_device *phydev) 1140 { 1141 /* 1142 * Conduct a hardware reset for AT8030 every time a link loss is 1143 * signalled. This is necessary to circumvent a hardware bug that 1144 * occurs when the cable is unplugged while TX packets are pending 1145 * in the FIFO. In such cases, the FIFO enters an error mode it 1146 * cannot recover from by software. 1147 */ 1148 if (phydev->state == PHY_NOLINK && phydev->mdio.reset_gpio) { 1149 struct at803x_context context; 1150 1151 at803x_context_save(phydev, &context); 1152 1153 phy_device_reset(phydev, 1); 1154 msleep(1); 1155 phy_device_reset(phydev, 0); 1156 msleep(1); 1157 1158 at803x_context_restore(phydev, &context); 1159 1160 phydev_dbg(phydev, "%s(): phy was reset\n", __func__); 1161 } 1162 } 1163 1164 static int at803x_read_specific_status(struct phy_device *phydev) 1165 { 1166 int ss; 1167 1168 /* Read the AT8035 PHY-Specific Status register, which indicates the 1169 * speed and duplex that the PHY is actually using, irrespective of 1170 * whether we are in autoneg mode or not. 1171 */ 1172 ss = phy_read(phydev, AT803X_SPECIFIC_STATUS); 1173 if (ss < 0) 1174 return ss; 1175 1176 if (ss & AT803X_SS_SPEED_DUPLEX_RESOLVED) { 1177 int sfc, speed; 1178 1179 sfc = phy_read(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL); 1180 if (sfc < 0) 1181 return sfc; 1182 1183 /* qca8081 takes the different bits for speed value from at803x */ 1184 if (phydev->drv->phy_id == QCA8081_PHY_ID) 1185 speed = FIELD_GET(QCA808X_SS_SPEED_MASK, ss); 1186 else 1187 speed = FIELD_GET(AT803X_SS_SPEED_MASK, ss); 1188 1189 switch (speed) { 1190 case AT803X_SS_SPEED_10: 1191 phydev->speed = SPEED_10; 1192 break; 1193 case AT803X_SS_SPEED_100: 1194 phydev->speed = SPEED_100; 1195 break; 1196 case AT803X_SS_SPEED_1000: 1197 phydev->speed = SPEED_1000; 1198 break; 1199 case QCA808X_SS_SPEED_2500: 1200 phydev->speed = SPEED_2500; 1201 break; 1202 } 1203 if (ss & AT803X_SS_DUPLEX) 1204 phydev->duplex = DUPLEX_FULL; 1205 else 1206 phydev->duplex = DUPLEX_HALF; 1207 1208 if (ss & AT803X_SS_MDIX) 1209 phydev->mdix = ETH_TP_MDI_X; 1210 else 1211 phydev->mdix = ETH_TP_MDI; 1212 1213 switch (FIELD_GET(AT803X_SFC_MDI_CROSSOVER_MODE_M, sfc)) { 1214 case AT803X_SFC_MANUAL_MDI: 1215 phydev->mdix_ctrl = ETH_TP_MDI; 1216 break; 1217 case AT803X_SFC_MANUAL_MDIX: 1218 phydev->mdix_ctrl = ETH_TP_MDI_X; 1219 break; 1220 case AT803X_SFC_AUTOMATIC_CROSSOVER: 1221 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; 1222 break; 1223 } 1224 } 1225 1226 return 0; 1227 } 1228 1229 static int at803x_read_status(struct phy_device *phydev) 1230 { 1231 struct at803x_priv *priv = phydev->priv; 1232 int err, old_link = phydev->link; 1233 1234 if (priv->is_1000basex) 1235 return genphy_c37_read_status(phydev); 1236 1237 /* Update the link, but return if there was an error */ 1238 err = genphy_update_link(phydev); 1239 if (err) 1240 return err; 1241 1242 /* why bother the PHY if nothing can have changed */ 1243 if (phydev->autoneg == AUTONEG_ENABLE && old_link && phydev->link) 1244 return 0; 1245 1246 phydev->speed = SPEED_UNKNOWN; 1247 phydev->duplex = DUPLEX_UNKNOWN; 1248 phydev->pause = 0; 1249 phydev->asym_pause = 0; 1250 1251 err = genphy_read_lpa(phydev); 1252 if (err < 0) 1253 return err; 1254 1255 err = at803x_read_specific_status(phydev); 1256 if (err < 0) 1257 return err; 1258 1259 if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) 1260 phy_resolve_aneg_pause(phydev); 1261 1262 return 0; 1263 } 1264 1265 static int at803x_config_mdix(struct phy_device *phydev, u8 ctrl) 1266 { 1267 u16 val; 1268 1269 switch (ctrl) { 1270 case ETH_TP_MDI: 1271 val = AT803X_SFC_MANUAL_MDI; 1272 break; 1273 case ETH_TP_MDI_X: 1274 val = AT803X_SFC_MANUAL_MDIX; 1275 break; 1276 case ETH_TP_MDI_AUTO: 1277 val = AT803X_SFC_AUTOMATIC_CROSSOVER; 1278 break; 1279 default: 1280 return 0; 1281 } 1282 1283 return phy_modify_changed(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL, 1284 AT803X_SFC_MDI_CROSSOVER_MODE_M, 1285 FIELD_PREP(AT803X_SFC_MDI_CROSSOVER_MODE_M, val)); 1286 } 1287 1288 static int at803x_config_aneg(struct phy_device *phydev) 1289 { 1290 struct at803x_priv *priv = phydev->priv; 1291 int ret; 1292 1293 ret = at803x_config_mdix(phydev, phydev->mdix_ctrl); 1294 if (ret < 0) 1295 return ret; 1296 1297 /* Changes of the midx bits are disruptive to the normal operation; 1298 * therefore any changes to these registers must be followed by a 1299 * software reset to take effect. 1300 */ 1301 if (ret == 1) { 1302 ret = genphy_soft_reset(phydev); 1303 if (ret < 0) 1304 return ret; 1305 } 1306 1307 if (priv->is_1000basex) 1308 return genphy_c37_config_aneg(phydev); 1309 1310 /* Do not restart auto-negotiation by setting ret to 0 defautly, 1311 * when calling __genphy_config_aneg later. 1312 */ 1313 ret = 0; 1314 1315 if (phydev->drv->phy_id == QCA8081_PHY_ID) { 1316 int phy_ctrl = 0; 1317 1318 /* The reg MII_BMCR also needs to be configured for force mode, the 1319 * genphy_config_aneg is also needed. 1320 */ 1321 if (phydev->autoneg == AUTONEG_DISABLE) 1322 genphy_c45_pma_setup_forced(phydev); 1323 1324 if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->advertising)) 1325 phy_ctrl = MDIO_AN_10GBT_CTRL_ADV2_5G; 1326 1327 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, 1328 MDIO_AN_10GBT_CTRL_ADV2_5G, phy_ctrl); 1329 if (ret < 0) 1330 return ret; 1331 } 1332 1333 return __genphy_config_aneg(phydev, ret); 1334 } 1335 1336 static int at803x_get_downshift(struct phy_device *phydev, u8 *d) 1337 { 1338 int val; 1339 1340 val = phy_read(phydev, AT803X_SMART_SPEED); 1341 if (val < 0) 1342 return val; 1343 1344 if (val & AT803X_SMART_SPEED_ENABLE) 1345 *d = FIELD_GET(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, val) + 2; 1346 else 1347 *d = DOWNSHIFT_DEV_DISABLE; 1348 1349 return 0; 1350 } 1351 1352 static int at803x_set_downshift(struct phy_device *phydev, u8 cnt) 1353 { 1354 u16 mask, set; 1355 int ret; 1356 1357 switch (cnt) { 1358 case DOWNSHIFT_DEV_DEFAULT_COUNT: 1359 cnt = AT803X_DEFAULT_DOWNSHIFT; 1360 fallthrough; 1361 case AT803X_MIN_DOWNSHIFT ... AT803X_MAX_DOWNSHIFT: 1362 set = AT803X_SMART_SPEED_ENABLE | 1363 AT803X_SMART_SPEED_BYPASS_TIMER | 1364 FIELD_PREP(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, cnt - 2); 1365 mask = AT803X_SMART_SPEED_RETRY_LIMIT_MASK; 1366 break; 1367 case DOWNSHIFT_DEV_DISABLE: 1368 set = 0; 1369 mask = AT803X_SMART_SPEED_ENABLE | 1370 AT803X_SMART_SPEED_BYPASS_TIMER; 1371 break; 1372 default: 1373 return -EINVAL; 1374 } 1375 1376 ret = phy_modify_changed(phydev, AT803X_SMART_SPEED, mask, set); 1377 1378 /* After changing the smart speed settings, we need to perform a 1379 * software reset, use phy_init_hw() to make sure we set the 1380 * reapply any values which might got lost during software reset. 1381 */ 1382 if (ret == 1) 1383 ret = phy_init_hw(phydev); 1384 1385 return ret; 1386 } 1387 1388 static int at803x_get_tunable(struct phy_device *phydev, 1389 struct ethtool_tunable *tuna, void *data) 1390 { 1391 switch (tuna->id) { 1392 case ETHTOOL_PHY_DOWNSHIFT: 1393 return at803x_get_downshift(phydev, data); 1394 default: 1395 return -EOPNOTSUPP; 1396 } 1397 } 1398 1399 static int at803x_set_tunable(struct phy_device *phydev, 1400 struct ethtool_tunable *tuna, const void *data) 1401 { 1402 switch (tuna->id) { 1403 case ETHTOOL_PHY_DOWNSHIFT: 1404 return at803x_set_downshift(phydev, *(const u8 *)data); 1405 default: 1406 return -EOPNOTSUPP; 1407 } 1408 } 1409 1410 static int at803x_cable_test_result_trans(u16 status) 1411 { 1412 switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) { 1413 case AT803X_CDT_STATUS_STAT_NORMAL: 1414 return ETHTOOL_A_CABLE_RESULT_CODE_OK; 1415 case AT803X_CDT_STATUS_STAT_SHORT: 1416 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT; 1417 case AT803X_CDT_STATUS_STAT_OPEN: 1418 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN; 1419 case AT803X_CDT_STATUS_STAT_FAIL: 1420 default: 1421 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC; 1422 } 1423 } 1424 1425 static bool at803x_cdt_test_failed(u16 status) 1426 { 1427 return FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status) == 1428 AT803X_CDT_STATUS_STAT_FAIL; 1429 } 1430 1431 static bool at803x_cdt_fault_length_valid(u16 status) 1432 { 1433 switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) { 1434 case AT803X_CDT_STATUS_STAT_OPEN: 1435 case AT803X_CDT_STATUS_STAT_SHORT: 1436 return true; 1437 } 1438 return false; 1439 } 1440 1441 static int at803x_cdt_fault_length(u16 status) 1442 { 1443 int dt; 1444 1445 /* According to the datasheet the distance to the fault is 1446 * DELTA_TIME * 0.824 meters. 1447 * 1448 * The author suspect the correct formula is: 1449 * 1450 * fault_distance = DELTA_TIME * (c * VF) / 125MHz / 2 1451 * 1452 * where c is the speed of light, VF is the velocity factor of 1453 * the twisted pair cable, 125MHz the counter frequency and 1454 * we need to divide by 2 because the hardware will measure the 1455 * round trip time to the fault and back to the PHY. 1456 * 1457 * With a VF of 0.69 we get the factor 0.824 mentioned in the 1458 * datasheet. 1459 */ 1460 dt = FIELD_GET(AT803X_CDT_STATUS_DELTA_TIME_MASK, status); 1461 1462 return (dt * 824) / 10; 1463 } 1464 1465 static int at803x_cdt_start(struct phy_device *phydev, int pair) 1466 { 1467 u16 cdt; 1468 1469 /* qca8081 takes the different bit 15 to enable CDT test */ 1470 if (phydev->drv->phy_id == QCA8081_PHY_ID) 1471 cdt = QCA808X_CDT_ENABLE_TEST | 1472 QCA808X_CDT_LENGTH_UNIT | 1473 QCA808X_CDT_INTER_CHECK_DIS; 1474 else 1475 cdt = FIELD_PREP(AT803X_CDT_MDI_PAIR_MASK, pair) | 1476 AT803X_CDT_ENABLE_TEST; 1477 1478 return phy_write(phydev, AT803X_CDT, cdt); 1479 } 1480 1481 static int at803x_cdt_wait_for_completion(struct phy_device *phydev) 1482 { 1483 int val, ret; 1484 u16 cdt_en; 1485 1486 if (phydev->drv->phy_id == QCA8081_PHY_ID) 1487 cdt_en = QCA808X_CDT_ENABLE_TEST; 1488 else 1489 cdt_en = AT803X_CDT_ENABLE_TEST; 1490 1491 /* One test run takes about 25ms */ 1492 ret = phy_read_poll_timeout(phydev, AT803X_CDT, val, 1493 !(val & cdt_en), 1494 30000, 100000, true); 1495 1496 return ret < 0 ? ret : 0; 1497 } 1498 1499 static int at803x_cable_test_one_pair(struct phy_device *phydev, int pair) 1500 { 1501 static const int ethtool_pair[] = { 1502 ETHTOOL_A_CABLE_PAIR_A, 1503 ETHTOOL_A_CABLE_PAIR_B, 1504 ETHTOOL_A_CABLE_PAIR_C, 1505 ETHTOOL_A_CABLE_PAIR_D, 1506 }; 1507 int ret, val; 1508 1509 ret = at803x_cdt_start(phydev, pair); 1510 if (ret) 1511 return ret; 1512 1513 ret = at803x_cdt_wait_for_completion(phydev); 1514 if (ret) 1515 return ret; 1516 1517 val = phy_read(phydev, AT803X_CDT_STATUS); 1518 if (val < 0) 1519 return val; 1520 1521 if (at803x_cdt_test_failed(val)) 1522 return 0; 1523 1524 ethnl_cable_test_result(phydev, ethtool_pair[pair], 1525 at803x_cable_test_result_trans(val)); 1526 1527 if (at803x_cdt_fault_length_valid(val)) 1528 ethnl_cable_test_fault_length(phydev, ethtool_pair[pair], 1529 at803x_cdt_fault_length(val)); 1530 1531 return 1; 1532 } 1533 1534 static int at803x_cable_test_get_status(struct phy_device *phydev, 1535 bool *finished) 1536 { 1537 unsigned long pair_mask; 1538 int retries = 20; 1539 int pair, ret; 1540 1541 if (phydev->phy_id == ATH9331_PHY_ID || 1542 phydev->phy_id == ATH8032_PHY_ID || 1543 phydev->phy_id == QCA9561_PHY_ID) 1544 pair_mask = 0x3; 1545 else 1546 pair_mask = 0xf; 1547 1548 *finished = false; 1549 1550 /* According to the datasheet the CDT can be performed when 1551 * there is no link partner or when the link partner is 1552 * auto-negotiating. Starting the test will restart the AN 1553 * automatically. It seems that doing this repeatedly we will 1554 * get a slot where our link partner won't disturb our 1555 * measurement. 1556 */ 1557 while (pair_mask && retries--) { 1558 for_each_set_bit(pair, &pair_mask, 4) { 1559 ret = at803x_cable_test_one_pair(phydev, pair); 1560 if (ret < 0) 1561 return ret; 1562 if (ret) 1563 clear_bit(pair, &pair_mask); 1564 } 1565 if (pair_mask) 1566 msleep(250); 1567 } 1568 1569 *finished = true; 1570 1571 return 0; 1572 } 1573 1574 static int at803x_cable_test_start(struct phy_device *phydev) 1575 { 1576 /* Enable auto-negotiation, but advertise no capabilities, no link 1577 * will be established. A restart of the auto-negotiation is not 1578 * required, because the cable test will automatically break the link. 1579 */ 1580 phy_write(phydev, MII_BMCR, BMCR_ANENABLE); 1581 phy_write(phydev, MII_ADVERTISE, ADVERTISE_CSMA); 1582 if (phydev->phy_id != ATH9331_PHY_ID && 1583 phydev->phy_id != ATH8032_PHY_ID && 1584 phydev->phy_id != QCA9561_PHY_ID) 1585 phy_write(phydev, MII_CTRL1000, 0); 1586 1587 /* we do all the (time consuming) work later */ 1588 return 0; 1589 } 1590 1591 static int qca83xx_config_init(struct phy_device *phydev) 1592 { 1593 u8 switch_revision; 1594 1595 switch_revision = phydev->dev_flags & QCA8K_DEVFLAGS_REVISION_MASK; 1596 1597 switch (switch_revision) { 1598 case 1: 1599 /* For 100M waveform */ 1600 at803x_debug_reg_write(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0x02ea); 1601 /* Turn on Gigabit clock */ 1602 at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x68a0); 1603 break; 1604 1605 case 2: 1606 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0x0); 1607 fallthrough; 1608 case 4: 1609 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_AZ_DEBUG, 0x803f); 1610 at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x6860); 1611 at803x_debug_reg_write(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0x2c46); 1612 at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3C, 0x6000); 1613 break; 1614 } 1615 1616 /* QCA8327 require DAC amplitude adjustment for 100m set to +6%. 1617 * Disable on init and enable only with 100m speed following 1618 * qca original source code. 1619 */ 1620 if (phydev->drv->phy_id == QCA8327_A_PHY_ID || 1621 phydev->drv->phy_id == QCA8327_B_PHY_ID) 1622 at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 1623 QCA8327_DEBUG_MANU_CTRL_EN, 0); 1624 1625 /* Following original QCA sourcecode set port to prefer master */ 1626 phy_set_bits(phydev, MII_CTRL1000, CTL1000_PREFER_MASTER); 1627 1628 return 0; 1629 } 1630 1631 static void qca83xx_link_change_notify(struct phy_device *phydev) 1632 { 1633 /* QCA8337 doesn't require DAC Amplitude adjustement */ 1634 if (phydev->drv->phy_id == QCA8337_PHY_ID) 1635 return; 1636 1637 /* Set DAC Amplitude adjustment to +6% for 100m on link running */ 1638 if (phydev->state == PHY_RUNNING) { 1639 if (phydev->speed == SPEED_100) 1640 at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 1641 QCA8327_DEBUG_MANU_CTRL_EN, 1642 QCA8327_DEBUG_MANU_CTRL_EN); 1643 } else { 1644 /* Reset DAC Amplitude adjustment */ 1645 at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 1646 QCA8327_DEBUG_MANU_CTRL_EN, 0); 1647 } 1648 } 1649 1650 static int qca83xx_resume(struct phy_device *phydev) 1651 { 1652 int ret, val; 1653 1654 /* Skip reset if not suspended */ 1655 if (!phydev->suspended) 1656 return 0; 1657 1658 /* Reinit the port, reset values set by suspend */ 1659 qca83xx_config_init(phydev); 1660 1661 /* Reset the port on port resume */ 1662 phy_set_bits(phydev, MII_BMCR, BMCR_RESET | BMCR_ANENABLE); 1663 1664 /* On resume from suspend the switch execute a reset and 1665 * restart auto-negotiation. Wait for reset to complete. 1666 */ 1667 ret = phy_read_poll_timeout(phydev, MII_BMCR, val, !(val & BMCR_RESET), 1668 50000, 600000, true); 1669 if (ret) 1670 return ret; 1671 1672 msleep(1); 1673 1674 return 0; 1675 } 1676 1677 static int qca83xx_suspend(struct phy_device *phydev) 1678 { 1679 u16 mask = 0; 1680 1681 /* Only QCA8337 support actual suspend. 1682 * QCA8327 cause port unreliability when phy suspend 1683 * is set. 1684 */ 1685 if (phydev->drv->phy_id == QCA8337_PHY_ID) { 1686 genphy_suspend(phydev); 1687 } else { 1688 mask |= ~(BMCR_SPEED1000 | BMCR_FULLDPLX); 1689 phy_modify(phydev, MII_BMCR, mask, 0); 1690 } 1691 1692 at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_GREEN, 1693 AT803X_DEBUG_GATE_CLK_IN1000, 0); 1694 1695 at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL, 1696 AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE | 1697 AT803X_DEBUG_HIB_CTRL_SEL_RST_80U, 0); 1698 1699 return 0; 1700 } 1701 1702 static int qca808x_phy_fast_retrain_config(struct phy_device *phydev) 1703 { 1704 int ret; 1705 1706 /* Enable fast retrain */ 1707 ret = genphy_c45_fast_retrain(phydev, true); 1708 if (ret) 1709 return ret; 1710 1711 phy_write_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_TOP_OPTION1, 1712 QCA808X_TOP_OPTION1_DATA); 1713 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB, 1714 QCA808X_MSE_THRESHOLD_20DB_VALUE); 1715 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB, 1716 QCA808X_MSE_THRESHOLD_17DB_VALUE); 1717 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB, 1718 QCA808X_MSE_THRESHOLD_27DB_VALUE); 1719 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB, 1720 QCA808X_MSE_THRESHOLD_28DB_VALUE); 1721 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_1, 1722 QCA808X_MMD3_DEBUG_1_VALUE); 1723 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_4, 1724 QCA808X_MMD3_DEBUG_4_VALUE); 1725 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_5, 1726 QCA808X_MMD3_DEBUG_5_VALUE); 1727 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_3, 1728 QCA808X_MMD3_DEBUG_3_VALUE); 1729 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_6, 1730 QCA808X_MMD3_DEBUG_6_VALUE); 1731 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_2, 1732 QCA808X_MMD3_DEBUG_2_VALUE); 1733 1734 return 0; 1735 } 1736 1737 static int qca808x_phy_ms_random_seed_set(struct phy_device *phydev) 1738 { 1739 u16 seed_value = get_random_u32_below(QCA808X_MASTER_SLAVE_SEED_RANGE); 1740 1741 return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED, 1742 QCA808X_MASTER_SLAVE_SEED_CFG, 1743 FIELD_PREP(QCA808X_MASTER_SLAVE_SEED_CFG, seed_value)); 1744 } 1745 1746 static int qca808x_phy_ms_seed_enable(struct phy_device *phydev, bool enable) 1747 { 1748 u16 seed_enable = 0; 1749 1750 if (enable) 1751 seed_enable = QCA808X_MASTER_SLAVE_SEED_ENABLE; 1752 1753 return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED, 1754 QCA808X_MASTER_SLAVE_SEED_ENABLE, seed_enable); 1755 } 1756 1757 static int qca808x_config_init(struct phy_device *phydev) 1758 { 1759 int ret; 1760 1761 /* Active adc&vga on 802.3az for the link 1000M and 100M */ 1762 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_ADDR_CLD_CTRL7, 1763 QCA808X_8023AZ_AFE_CTRL_MASK, QCA808X_8023AZ_AFE_EN); 1764 if (ret) 1765 return ret; 1766 1767 /* Adjust the threshold on 802.3az for the link 1000M */ 1768 ret = phy_write_mmd(phydev, MDIO_MMD_PCS, 1769 QCA808X_PHY_MMD3_AZ_TRAINING_CTRL, QCA808X_MMD3_AZ_TRAINING_VAL); 1770 if (ret) 1771 return ret; 1772 1773 /* Config the fast retrain for the link 2500M */ 1774 ret = qca808x_phy_fast_retrain_config(phydev); 1775 if (ret) 1776 return ret; 1777 1778 /* Configure lower ramdom seed to make phy linked as slave mode */ 1779 ret = qca808x_phy_ms_random_seed_set(phydev); 1780 if (ret) 1781 return ret; 1782 1783 /* Enable seed */ 1784 ret = qca808x_phy_ms_seed_enable(phydev, true); 1785 if (ret) 1786 return ret; 1787 1788 /* Configure adc threshold as 100mv for the link 10M */ 1789 return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_ADC_THRESHOLD, 1790 QCA808X_ADC_THRESHOLD_MASK, QCA808X_ADC_THRESHOLD_100MV); 1791 } 1792 1793 static int qca808x_read_status(struct phy_device *phydev) 1794 { 1795 int ret; 1796 1797 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT); 1798 if (ret < 0) 1799 return ret; 1800 1801 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->lp_advertising, 1802 ret & MDIO_AN_10GBT_STAT_LP2_5G); 1803 1804 ret = genphy_read_status(phydev); 1805 if (ret) 1806 return ret; 1807 1808 ret = at803x_read_specific_status(phydev); 1809 if (ret < 0) 1810 return ret; 1811 1812 if (phydev->link) { 1813 if (phydev->speed == SPEED_2500) 1814 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 1815 else 1816 phydev->interface = PHY_INTERFACE_MODE_SGMII; 1817 } else { 1818 /* generate seed as a lower random value to make PHY linked as SLAVE easily, 1819 * except for master/slave configuration fault detected. 1820 * the reason for not putting this code into the function link_change_notify is 1821 * the corner case where the link partner is also the qca8081 PHY and the seed 1822 * value is configured as the same value, the link can't be up and no link change 1823 * occurs. 1824 */ 1825 if (phydev->master_slave_state == MASTER_SLAVE_STATE_ERR) { 1826 qca808x_phy_ms_seed_enable(phydev, false); 1827 } else { 1828 qca808x_phy_ms_random_seed_set(phydev); 1829 qca808x_phy_ms_seed_enable(phydev, true); 1830 } 1831 } 1832 1833 return 0; 1834 } 1835 1836 static int qca808x_soft_reset(struct phy_device *phydev) 1837 { 1838 int ret; 1839 1840 ret = genphy_soft_reset(phydev); 1841 if (ret < 0) 1842 return ret; 1843 1844 return qca808x_phy_ms_seed_enable(phydev, true); 1845 } 1846 1847 static bool qca808x_cdt_fault_length_valid(int cdt_code) 1848 { 1849 switch (cdt_code) { 1850 case QCA808X_CDT_STATUS_STAT_SHORT: 1851 case QCA808X_CDT_STATUS_STAT_OPEN: 1852 return true; 1853 default: 1854 return false; 1855 } 1856 } 1857 1858 static int qca808x_cable_test_result_trans(int cdt_code) 1859 { 1860 switch (cdt_code) { 1861 case QCA808X_CDT_STATUS_STAT_NORMAL: 1862 return ETHTOOL_A_CABLE_RESULT_CODE_OK; 1863 case QCA808X_CDT_STATUS_STAT_SHORT: 1864 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT; 1865 case QCA808X_CDT_STATUS_STAT_OPEN: 1866 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN; 1867 case QCA808X_CDT_STATUS_STAT_FAIL: 1868 default: 1869 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC; 1870 } 1871 } 1872 1873 static int qca808x_cdt_fault_length(struct phy_device *phydev, int pair) 1874 { 1875 int val; 1876 u32 cdt_length_reg = 0; 1877 1878 switch (pair) { 1879 case ETHTOOL_A_CABLE_PAIR_A: 1880 cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_A; 1881 break; 1882 case ETHTOOL_A_CABLE_PAIR_B: 1883 cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_B; 1884 break; 1885 case ETHTOOL_A_CABLE_PAIR_C: 1886 cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_C; 1887 break; 1888 case ETHTOOL_A_CABLE_PAIR_D: 1889 cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_D; 1890 break; 1891 default: 1892 return -EINVAL; 1893 } 1894 1895 val = phy_read_mmd(phydev, MDIO_MMD_PCS, cdt_length_reg); 1896 if (val < 0) 1897 return val; 1898 1899 return (FIELD_GET(QCA808X_CDT_DIAG_LENGTH, val) * 824) / 10; 1900 } 1901 1902 static int qca808x_cable_test_start(struct phy_device *phydev) 1903 { 1904 int ret; 1905 1906 /* perform CDT with the following configs: 1907 * 1. disable hibernation. 1908 * 2. force PHY working in MDI mode. 1909 * 3. for PHY working in 1000BaseT. 1910 * 4. configure the threshold. 1911 */ 1912 1913 ret = at803x_debug_reg_mask(phydev, QCA808X_DBG_AN_TEST, QCA808X_HIBERNATION_EN, 0); 1914 if (ret < 0) 1915 return ret; 1916 1917 ret = at803x_config_mdix(phydev, ETH_TP_MDI); 1918 if (ret < 0) 1919 return ret; 1920 1921 /* Force 1000base-T needs to configure PMA/PMD and MII_BMCR */ 1922 phydev->duplex = DUPLEX_FULL; 1923 phydev->speed = SPEED_1000; 1924 ret = genphy_c45_pma_setup_forced(phydev); 1925 if (ret < 0) 1926 return ret; 1927 1928 ret = genphy_setup_forced(phydev); 1929 if (ret < 0) 1930 return ret; 1931 1932 /* configure the thresholds for open, short, pair ok test */ 1933 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8074, 0xc040); 1934 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8076, 0xc040); 1935 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8077, 0xa060); 1936 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8078, 0xc050); 1937 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807a, 0xc060); 1938 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807e, 0xb060); 1939 1940 return 0; 1941 } 1942 1943 static int qca808x_cable_test_get_status(struct phy_device *phydev, bool *finished) 1944 { 1945 int ret, val; 1946 int pair_a, pair_b, pair_c, pair_d; 1947 1948 *finished = false; 1949 1950 ret = at803x_cdt_start(phydev, 0); 1951 if (ret) 1952 return ret; 1953 1954 ret = at803x_cdt_wait_for_completion(phydev); 1955 if (ret) 1956 return ret; 1957 1958 val = phy_read_mmd(phydev, MDIO_MMD_PCS, QCA808X_MMD3_CDT_STATUS); 1959 if (val < 0) 1960 return val; 1961 1962 pair_a = FIELD_GET(QCA808X_CDT_CODE_PAIR_A, val); 1963 pair_b = FIELD_GET(QCA808X_CDT_CODE_PAIR_B, val); 1964 pair_c = FIELD_GET(QCA808X_CDT_CODE_PAIR_C, val); 1965 pair_d = FIELD_GET(QCA808X_CDT_CODE_PAIR_D, val); 1966 1967 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A, 1968 qca808x_cable_test_result_trans(pair_a)); 1969 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_B, 1970 qca808x_cable_test_result_trans(pair_b)); 1971 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_C, 1972 qca808x_cable_test_result_trans(pair_c)); 1973 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_D, 1974 qca808x_cable_test_result_trans(pair_d)); 1975 1976 if (qca808x_cdt_fault_length_valid(pair_a)) 1977 ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_A, 1978 qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_A)); 1979 if (qca808x_cdt_fault_length_valid(pair_b)) 1980 ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_B, 1981 qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_B)); 1982 if (qca808x_cdt_fault_length_valid(pair_c)) 1983 ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_C, 1984 qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_C)); 1985 if (qca808x_cdt_fault_length_valid(pair_d)) 1986 ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_D, 1987 qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_D)); 1988 1989 *finished = true; 1990 1991 return 0; 1992 } 1993 1994 static struct phy_driver at803x_driver[] = { 1995 { 1996 /* Qualcomm Atheros AR8035 */ 1997 PHY_ID_MATCH_EXACT(ATH8035_PHY_ID), 1998 .name = "Qualcomm Atheros AR8035", 1999 .flags = PHY_POLL_CABLE_TEST, 2000 .probe = at803x_probe, 2001 .config_aneg = at803x_config_aneg, 2002 .config_init = at803x_config_init, 2003 .soft_reset = genphy_soft_reset, 2004 .set_wol = at803x_set_wol, 2005 .get_wol = at803x_get_wol, 2006 .suspend = at803x_suspend, 2007 .resume = at803x_resume, 2008 /* PHY_GBIT_FEATURES */ 2009 .read_status = at803x_read_status, 2010 .config_intr = at803x_config_intr, 2011 .handle_interrupt = at803x_handle_interrupt, 2012 .get_tunable = at803x_get_tunable, 2013 .set_tunable = at803x_set_tunable, 2014 .cable_test_start = at803x_cable_test_start, 2015 .cable_test_get_status = at803x_cable_test_get_status, 2016 }, { 2017 /* Qualcomm Atheros AR8030 */ 2018 .phy_id = ATH8030_PHY_ID, 2019 .name = "Qualcomm Atheros AR8030", 2020 .phy_id_mask = AT8030_PHY_ID_MASK, 2021 .probe = at803x_probe, 2022 .config_init = at803x_config_init, 2023 .link_change_notify = at803x_link_change_notify, 2024 .set_wol = at803x_set_wol, 2025 .get_wol = at803x_get_wol, 2026 .suspend = at803x_suspend, 2027 .resume = at803x_resume, 2028 /* PHY_BASIC_FEATURES */ 2029 .config_intr = at803x_config_intr, 2030 .handle_interrupt = at803x_handle_interrupt, 2031 }, { 2032 /* Qualcomm Atheros AR8031/AR8033 */ 2033 PHY_ID_MATCH_EXACT(ATH8031_PHY_ID), 2034 .name = "Qualcomm Atheros AR8031/AR8033", 2035 .flags = PHY_POLL_CABLE_TEST, 2036 .probe = at803x_probe, 2037 .config_init = at803x_config_init, 2038 .config_aneg = at803x_config_aneg, 2039 .soft_reset = genphy_soft_reset, 2040 .set_wol = at803x_set_wol, 2041 .get_wol = at803x_get_wol, 2042 .suspend = at803x_suspend, 2043 .resume = at803x_resume, 2044 .read_page = at803x_read_page, 2045 .write_page = at803x_write_page, 2046 .get_features = at803x_get_features, 2047 .read_status = at803x_read_status, 2048 .config_intr = &at803x_config_intr, 2049 .handle_interrupt = at803x_handle_interrupt, 2050 .get_tunable = at803x_get_tunable, 2051 .set_tunable = at803x_set_tunable, 2052 .cable_test_start = at803x_cable_test_start, 2053 .cable_test_get_status = at803x_cable_test_get_status, 2054 }, { 2055 /* Qualcomm Atheros AR8032 */ 2056 PHY_ID_MATCH_EXACT(ATH8032_PHY_ID), 2057 .name = "Qualcomm Atheros AR8032", 2058 .probe = at803x_probe, 2059 .flags = PHY_POLL_CABLE_TEST, 2060 .config_init = at803x_config_init, 2061 .link_change_notify = at803x_link_change_notify, 2062 .set_wol = at803x_set_wol, 2063 .get_wol = at803x_get_wol, 2064 .suspend = at803x_suspend, 2065 .resume = at803x_resume, 2066 /* PHY_BASIC_FEATURES */ 2067 .config_intr = at803x_config_intr, 2068 .handle_interrupt = at803x_handle_interrupt, 2069 .cable_test_start = at803x_cable_test_start, 2070 .cable_test_get_status = at803x_cable_test_get_status, 2071 }, { 2072 /* ATHEROS AR9331 */ 2073 PHY_ID_MATCH_EXACT(ATH9331_PHY_ID), 2074 .name = "Qualcomm Atheros AR9331 built-in PHY", 2075 .probe = at803x_probe, 2076 .suspend = at803x_suspend, 2077 .resume = at803x_resume, 2078 .flags = PHY_POLL_CABLE_TEST, 2079 /* PHY_BASIC_FEATURES */ 2080 .config_intr = &at803x_config_intr, 2081 .handle_interrupt = at803x_handle_interrupt, 2082 .cable_test_start = at803x_cable_test_start, 2083 .cable_test_get_status = at803x_cable_test_get_status, 2084 .read_status = at803x_read_status, 2085 .soft_reset = genphy_soft_reset, 2086 .config_aneg = at803x_config_aneg, 2087 }, { 2088 /* Qualcomm Atheros QCA9561 */ 2089 PHY_ID_MATCH_EXACT(QCA9561_PHY_ID), 2090 .name = "Qualcomm Atheros QCA9561 built-in PHY", 2091 .probe = at803x_probe, 2092 .suspend = at803x_suspend, 2093 .resume = at803x_resume, 2094 .flags = PHY_POLL_CABLE_TEST, 2095 /* PHY_BASIC_FEATURES */ 2096 .config_intr = &at803x_config_intr, 2097 .handle_interrupt = at803x_handle_interrupt, 2098 .cable_test_start = at803x_cable_test_start, 2099 .cable_test_get_status = at803x_cable_test_get_status, 2100 .read_status = at803x_read_status, 2101 .soft_reset = genphy_soft_reset, 2102 .config_aneg = at803x_config_aneg, 2103 }, { 2104 /* QCA8337 */ 2105 .phy_id = QCA8337_PHY_ID, 2106 .phy_id_mask = QCA8K_PHY_ID_MASK, 2107 .name = "Qualcomm Atheros 8337 internal PHY", 2108 /* PHY_GBIT_FEATURES */ 2109 .link_change_notify = qca83xx_link_change_notify, 2110 .probe = at803x_probe, 2111 .flags = PHY_IS_INTERNAL, 2112 .config_init = qca83xx_config_init, 2113 .soft_reset = genphy_soft_reset, 2114 .get_sset_count = at803x_get_sset_count, 2115 .get_strings = at803x_get_strings, 2116 .get_stats = at803x_get_stats, 2117 .suspend = qca83xx_suspend, 2118 .resume = qca83xx_resume, 2119 }, { 2120 /* QCA8327-A from switch QCA8327-AL1A */ 2121 .phy_id = QCA8327_A_PHY_ID, 2122 .phy_id_mask = QCA8K_PHY_ID_MASK, 2123 .name = "Qualcomm Atheros 8327-A internal PHY", 2124 /* PHY_GBIT_FEATURES */ 2125 .link_change_notify = qca83xx_link_change_notify, 2126 .probe = at803x_probe, 2127 .flags = PHY_IS_INTERNAL, 2128 .config_init = qca83xx_config_init, 2129 .soft_reset = genphy_soft_reset, 2130 .get_sset_count = at803x_get_sset_count, 2131 .get_strings = at803x_get_strings, 2132 .get_stats = at803x_get_stats, 2133 .suspend = qca83xx_suspend, 2134 .resume = qca83xx_resume, 2135 }, { 2136 /* QCA8327-B from switch QCA8327-BL1A */ 2137 .phy_id = QCA8327_B_PHY_ID, 2138 .phy_id_mask = QCA8K_PHY_ID_MASK, 2139 .name = "Qualcomm Atheros 8327-B internal PHY", 2140 /* PHY_GBIT_FEATURES */ 2141 .link_change_notify = qca83xx_link_change_notify, 2142 .probe = at803x_probe, 2143 .flags = PHY_IS_INTERNAL, 2144 .config_init = qca83xx_config_init, 2145 .soft_reset = genphy_soft_reset, 2146 .get_sset_count = at803x_get_sset_count, 2147 .get_strings = at803x_get_strings, 2148 .get_stats = at803x_get_stats, 2149 .suspend = qca83xx_suspend, 2150 .resume = qca83xx_resume, 2151 }, { 2152 /* Qualcomm QCA8081 */ 2153 PHY_ID_MATCH_EXACT(QCA8081_PHY_ID), 2154 .name = "Qualcomm QCA8081", 2155 .flags = PHY_POLL_CABLE_TEST, 2156 .probe = at803x_probe, 2157 .config_intr = at803x_config_intr, 2158 .handle_interrupt = at803x_handle_interrupt, 2159 .get_tunable = at803x_get_tunable, 2160 .set_tunable = at803x_set_tunable, 2161 .set_wol = at803x_set_wol, 2162 .get_wol = at803x_get_wol, 2163 .get_features = at803x_get_features, 2164 .config_aneg = at803x_config_aneg, 2165 .suspend = genphy_suspend, 2166 .resume = genphy_resume, 2167 .read_status = qca808x_read_status, 2168 .config_init = qca808x_config_init, 2169 .soft_reset = qca808x_soft_reset, 2170 .cable_test_start = qca808x_cable_test_start, 2171 .cable_test_get_status = qca808x_cable_test_get_status, 2172 }, }; 2173 2174 module_phy_driver(at803x_driver); 2175 2176 static struct mdio_device_id __maybe_unused atheros_tbl[] = { 2177 { ATH8030_PHY_ID, AT8030_PHY_ID_MASK }, 2178 { PHY_ID_MATCH_EXACT(ATH8031_PHY_ID) }, 2179 { PHY_ID_MATCH_EXACT(ATH8032_PHY_ID) }, 2180 { PHY_ID_MATCH_EXACT(ATH8035_PHY_ID) }, 2181 { PHY_ID_MATCH_EXACT(ATH9331_PHY_ID) }, 2182 { PHY_ID_MATCH_EXACT(QCA8337_PHY_ID) }, 2183 { PHY_ID_MATCH_EXACT(QCA8327_A_PHY_ID) }, 2184 { PHY_ID_MATCH_EXACT(QCA8327_B_PHY_ID) }, 2185 { PHY_ID_MATCH_EXACT(QCA9561_PHY_ID) }, 2186 { PHY_ID_MATCH_EXACT(QCA8081_PHY_ID) }, 2187 { } 2188 }; 2189 2190 MODULE_DEVICE_TABLE(mdio, atheros_tbl); 2191