1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for Aquantia PHY 4 * 5 * Author: Shaohui Xie <Shaohui.Xie@freescale.com> 6 * 7 * Copyright 2015 Freescale Semiconductor, Inc. 8 */ 9 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/delay.h> 13 #include <linux/bitfield.h> 14 #include <linux/phy.h> 15 16 #include "aquantia.h" 17 18 #define PHY_ID_AQ1202 0x03a1b445 19 #define PHY_ID_AQ2104 0x03a1b460 20 #define PHY_ID_AQR105 0x03a1b4a2 21 #define PHY_ID_AQR106 0x03a1b4d0 22 #define PHY_ID_AQR107 0x03a1b4e0 23 #define PHY_ID_AQCS109 0x03a1b5c2 24 #define PHY_ID_AQR405 0x03a1b4b0 25 26 #define MDIO_PHYXS_VEND_IF_STATUS 0xe812 27 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK GENMASK(7, 3) 28 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR 0 29 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI 2 30 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII 3 31 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII 6 32 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII 10 33 34 #define MDIO_AN_VEND_PROV 0xc400 35 #define MDIO_AN_VEND_PROV_1000BASET_FULL BIT(15) 36 #define MDIO_AN_VEND_PROV_1000BASET_HALF BIT(14) 37 #define MDIO_AN_VEND_PROV_5000BASET_FULL BIT(11) 38 #define MDIO_AN_VEND_PROV_2500BASET_FULL BIT(10) 39 #define MDIO_AN_VEND_PROV_DOWNSHIFT_EN BIT(4) 40 #define MDIO_AN_VEND_PROV_DOWNSHIFT_MASK GENMASK(3, 0) 41 #define MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT 4 42 43 #define MDIO_AN_TX_VEND_STATUS1 0xc800 44 #define MDIO_AN_TX_VEND_STATUS1_RATE_MASK GENMASK(3, 1) 45 #define MDIO_AN_TX_VEND_STATUS1_10BASET 0 46 #define MDIO_AN_TX_VEND_STATUS1_100BASETX 1 47 #define MDIO_AN_TX_VEND_STATUS1_1000BASET 2 48 #define MDIO_AN_TX_VEND_STATUS1_10GBASET 3 49 #define MDIO_AN_TX_VEND_STATUS1_2500BASET 4 50 #define MDIO_AN_TX_VEND_STATUS1_5000BASET 5 51 #define MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX BIT(0) 52 53 #define MDIO_AN_TX_VEND_INT_STATUS1 0xcc00 54 #define MDIO_AN_TX_VEND_INT_STATUS1_DOWNSHIFT BIT(1) 55 56 #define MDIO_AN_TX_VEND_INT_STATUS2 0xcc01 57 #define MDIO_AN_TX_VEND_INT_STATUS2_MASK BIT(0) 58 59 #define MDIO_AN_TX_VEND_INT_MASK2 0xd401 60 #define MDIO_AN_TX_VEND_INT_MASK2_LINK BIT(0) 61 62 #define MDIO_AN_RX_LP_STAT1 0xe820 63 #define MDIO_AN_RX_LP_STAT1_1000BASET_FULL BIT(15) 64 #define MDIO_AN_RX_LP_STAT1_1000BASET_HALF BIT(14) 65 #define MDIO_AN_RX_LP_STAT1_SHORT_REACH BIT(13) 66 #define MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT BIT(12) 67 #define MDIO_AN_RX_LP_STAT1_AQ_PHY BIT(2) 68 69 #define MDIO_AN_RX_LP_STAT4 0xe823 70 #define MDIO_AN_RX_LP_STAT4_FW_MAJOR GENMASK(15, 8) 71 #define MDIO_AN_RX_LP_STAT4_FW_MINOR GENMASK(7, 0) 72 73 #define MDIO_AN_RX_VEND_STAT3 0xe832 74 #define MDIO_AN_RX_VEND_STAT3_AFR BIT(0) 75 76 /* MDIO_MMD_C22EXT */ 77 #define MDIO_C22EXT_STAT_SGMII_RX_GOOD_FRAMES 0xd292 78 #define MDIO_C22EXT_STAT_SGMII_RX_BAD_FRAMES 0xd294 79 #define MDIO_C22EXT_STAT_SGMII_RX_FALSE_CARRIER 0xd297 80 #define MDIO_C22EXT_STAT_SGMII_TX_GOOD_FRAMES 0xd313 81 #define MDIO_C22EXT_STAT_SGMII_TX_BAD_FRAMES 0xd315 82 #define MDIO_C22EXT_STAT_SGMII_TX_FALSE_CARRIER 0xd317 83 #define MDIO_C22EXT_STAT_SGMII_TX_COLLISIONS 0xd318 84 #define MDIO_C22EXT_STAT_SGMII_TX_LINE_COLLISIONS 0xd319 85 #define MDIO_C22EXT_STAT_SGMII_TX_FRAME_ALIGN_ERR 0xd31a 86 #define MDIO_C22EXT_STAT_SGMII_TX_RUNT_FRAMES 0xd31b 87 88 /* Vendor specific 1, MDIO_MMD_VEND1 */ 89 #define VEND1_GLOBAL_FW_ID 0x0020 90 #define VEND1_GLOBAL_FW_ID_MAJOR GENMASK(15, 8) 91 #define VEND1_GLOBAL_FW_ID_MINOR GENMASK(7, 0) 92 93 #define VEND1_GLOBAL_RSVD_STAT1 0xc885 94 #define VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID GENMASK(7, 4) 95 #define VEND1_GLOBAL_RSVD_STAT1_PROV_ID GENMASK(3, 0) 96 97 #define VEND1_GLOBAL_RSVD_STAT9 0xc88d 98 #define VEND1_GLOBAL_RSVD_STAT9_MODE GENMASK(7, 0) 99 #define VEND1_GLOBAL_RSVD_STAT9_1000BT2 0x23 100 101 #define VEND1_GLOBAL_INT_STD_STATUS 0xfc00 102 #define VEND1_GLOBAL_INT_VEND_STATUS 0xfc01 103 104 #define VEND1_GLOBAL_INT_STD_MASK 0xff00 105 #define VEND1_GLOBAL_INT_STD_MASK_PMA1 BIT(15) 106 #define VEND1_GLOBAL_INT_STD_MASK_PMA2 BIT(14) 107 #define VEND1_GLOBAL_INT_STD_MASK_PCS1 BIT(13) 108 #define VEND1_GLOBAL_INT_STD_MASK_PCS2 BIT(12) 109 #define VEND1_GLOBAL_INT_STD_MASK_PCS3 BIT(11) 110 #define VEND1_GLOBAL_INT_STD_MASK_PHY_XS1 BIT(10) 111 #define VEND1_GLOBAL_INT_STD_MASK_PHY_XS2 BIT(9) 112 #define VEND1_GLOBAL_INT_STD_MASK_AN1 BIT(8) 113 #define VEND1_GLOBAL_INT_STD_MASK_AN2 BIT(7) 114 #define VEND1_GLOBAL_INT_STD_MASK_GBE BIT(6) 115 #define VEND1_GLOBAL_INT_STD_MASK_ALL BIT(0) 116 117 #define VEND1_GLOBAL_INT_VEND_MASK 0xff01 118 #define VEND1_GLOBAL_INT_VEND_MASK_PMA BIT(15) 119 #define VEND1_GLOBAL_INT_VEND_MASK_PCS BIT(14) 120 #define VEND1_GLOBAL_INT_VEND_MASK_PHY_XS BIT(13) 121 #define VEND1_GLOBAL_INT_VEND_MASK_AN BIT(12) 122 #define VEND1_GLOBAL_INT_VEND_MASK_GBE BIT(11) 123 #define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL1 BIT(2) 124 #define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL2 BIT(1) 125 #define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 BIT(0) 126 127 struct aqr107_hw_stat { 128 const char *name; 129 int reg; 130 int size; 131 }; 132 133 #define SGMII_STAT(n, r, s) { n, MDIO_C22EXT_STAT_SGMII_ ## r, s } 134 static const struct aqr107_hw_stat aqr107_hw_stats[] = { 135 SGMII_STAT("sgmii_rx_good_frames", RX_GOOD_FRAMES, 26), 136 SGMII_STAT("sgmii_rx_bad_frames", RX_BAD_FRAMES, 26), 137 SGMII_STAT("sgmii_rx_false_carrier_events", RX_FALSE_CARRIER, 8), 138 SGMII_STAT("sgmii_tx_good_frames", TX_GOOD_FRAMES, 26), 139 SGMII_STAT("sgmii_tx_bad_frames", TX_BAD_FRAMES, 26), 140 SGMII_STAT("sgmii_tx_false_carrier_events", TX_FALSE_CARRIER, 8), 141 SGMII_STAT("sgmii_tx_collisions", TX_COLLISIONS, 8), 142 SGMII_STAT("sgmii_tx_line_collisions", TX_LINE_COLLISIONS, 8), 143 SGMII_STAT("sgmii_tx_frame_alignment_err", TX_FRAME_ALIGN_ERR, 16), 144 SGMII_STAT("sgmii_tx_runt_frames", TX_RUNT_FRAMES, 22), 145 }; 146 #define AQR107_SGMII_STAT_SZ ARRAY_SIZE(aqr107_hw_stats) 147 148 struct aqr107_priv { 149 u64 sgmii_stats[AQR107_SGMII_STAT_SZ]; 150 }; 151 152 static int aqr107_get_sset_count(struct phy_device *phydev) 153 { 154 return AQR107_SGMII_STAT_SZ; 155 } 156 157 static void aqr107_get_strings(struct phy_device *phydev, u8 *data) 158 { 159 int i; 160 161 for (i = 0; i < AQR107_SGMII_STAT_SZ; i++) 162 strscpy(data + i * ETH_GSTRING_LEN, aqr107_hw_stats[i].name, 163 ETH_GSTRING_LEN); 164 } 165 166 static u64 aqr107_get_stat(struct phy_device *phydev, int index) 167 { 168 const struct aqr107_hw_stat *stat = aqr107_hw_stats + index; 169 int len_l = min(stat->size, 16); 170 int len_h = stat->size - len_l; 171 u64 ret; 172 int val; 173 174 val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg); 175 if (val < 0) 176 return U64_MAX; 177 178 ret = val & GENMASK(len_l - 1, 0); 179 if (len_h) { 180 val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg + 1); 181 if (val < 0) 182 return U64_MAX; 183 184 ret += (val & GENMASK(len_h - 1, 0)) << 16; 185 } 186 187 return ret; 188 } 189 190 static void aqr107_get_stats(struct phy_device *phydev, 191 struct ethtool_stats *stats, u64 *data) 192 { 193 struct aqr107_priv *priv = phydev->priv; 194 u64 val; 195 int i; 196 197 for (i = 0; i < AQR107_SGMII_STAT_SZ; i++) { 198 val = aqr107_get_stat(phydev, i); 199 if (val == U64_MAX) 200 phydev_err(phydev, "Reading HW Statistics failed for %s\n", 201 aqr107_hw_stats[i].name); 202 else 203 priv->sgmii_stats[i] += val; 204 205 data[i] = priv->sgmii_stats[i]; 206 } 207 } 208 209 static int aqr_config_aneg(struct phy_device *phydev) 210 { 211 bool changed = false; 212 u16 reg; 213 int ret; 214 215 if (phydev->autoneg == AUTONEG_DISABLE) 216 return genphy_c45_pma_setup_forced(phydev); 217 218 ret = genphy_c45_an_config_aneg(phydev); 219 if (ret < 0) 220 return ret; 221 if (ret > 0) 222 changed = true; 223 224 /* Clause 45 has no standardized support for 1000BaseT, therefore 225 * use vendor registers for this mode. 226 */ 227 reg = 0; 228 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 229 phydev->advertising)) 230 reg |= MDIO_AN_VEND_PROV_1000BASET_FULL; 231 232 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, 233 phydev->advertising)) 234 reg |= MDIO_AN_VEND_PROV_1000BASET_HALF; 235 236 /* Handle the case when the 2.5G and 5G speeds are not advertised */ 237 if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 238 phydev->advertising)) 239 reg |= MDIO_AN_VEND_PROV_2500BASET_FULL; 240 241 if (linkmode_test_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 242 phydev->advertising)) 243 reg |= MDIO_AN_VEND_PROV_5000BASET_FULL; 244 245 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV, 246 MDIO_AN_VEND_PROV_1000BASET_HALF | 247 MDIO_AN_VEND_PROV_1000BASET_FULL | 248 MDIO_AN_VEND_PROV_2500BASET_FULL | 249 MDIO_AN_VEND_PROV_5000BASET_FULL, reg); 250 if (ret < 0) 251 return ret; 252 if (ret > 0) 253 changed = true; 254 255 return genphy_c45_check_and_restart_aneg(phydev, changed); 256 } 257 258 static int aqr_config_intr(struct phy_device *phydev) 259 { 260 bool en = phydev->interrupts == PHY_INTERRUPT_ENABLED; 261 int err; 262 263 if (en) { 264 /* Clear any pending interrupts before enabling them */ 265 err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2); 266 if (err < 0) 267 return err; 268 } 269 270 err = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_MASK2, 271 en ? MDIO_AN_TX_VEND_INT_MASK2_LINK : 0); 272 if (err < 0) 273 return err; 274 275 err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_STD_MASK, 276 en ? VEND1_GLOBAL_INT_STD_MASK_ALL : 0); 277 if (err < 0) 278 return err; 279 280 err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_VEND_MASK, 281 en ? VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 | 282 VEND1_GLOBAL_INT_VEND_MASK_AN : 0); 283 if (err < 0) 284 return err; 285 286 if (!en) { 287 /* Clear any pending interrupts after we have disabled them */ 288 err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2); 289 if (err < 0) 290 return err; 291 } 292 293 return 0; 294 } 295 296 static irqreturn_t aqr_handle_interrupt(struct phy_device *phydev) 297 { 298 int irq_status; 299 300 irq_status = phy_read_mmd(phydev, MDIO_MMD_AN, 301 MDIO_AN_TX_VEND_INT_STATUS2); 302 if (irq_status < 0) { 303 phy_error(phydev); 304 return IRQ_NONE; 305 } 306 307 if (!(irq_status & MDIO_AN_TX_VEND_INT_STATUS2_MASK)) 308 return IRQ_NONE; 309 310 phy_trigger_machine(phydev); 311 312 return IRQ_HANDLED; 313 } 314 315 static int aqr_read_status(struct phy_device *phydev) 316 { 317 int val; 318 319 if (phydev->autoneg == AUTONEG_ENABLE) { 320 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1); 321 if (val < 0) 322 return val; 323 324 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 325 phydev->lp_advertising, 326 val & MDIO_AN_RX_LP_STAT1_1000BASET_FULL); 327 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, 328 phydev->lp_advertising, 329 val & MDIO_AN_RX_LP_STAT1_1000BASET_HALF); 330 } 331 332 return genphy_c45_read_status(phydev); 333 } 334 335 static int aqr107_read_rate(struct phy_device *phydev) 336 { 337 int val; 338 339 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_STATUS1); 340 if (val < 0) 341 return val; 342 343 switch (FIELD_GET(MDIO_AN_TX_VEND_STATUS1_RATE_MASK, val)) { 344 case MDIO_AN_TX_VEND_STATUS1_10BASET: 345 phydev->speed = SPEED_10; 346 break; 347 case MDIO_AN_TX_VEND_STATUS1_100BASETX: 348 phydev->speed = SPEED_100; 349 break; 350 case MDIO_AN_TX_VEND_STATUS1_1000BASET: 351 phydev->speed = SPEED_1000; 352 break; 353 case MDIO_AN_TX_VEND_STATUS1_2500BASET: 354 phydev->speed = SPEED_2500; 355 break; 356 case MDIO_AN_TX_VEND_STATUS1_5000BASET: 357 phydev->speed = SPEED_5000; 358 break; 359 case MDIO_AN_TX_VEND_STATUS1_10GBASET: 360 phydev->speed = SPEED_10000; 361 break; 362 default: 363 phydev->speed = SPEED_UNKNOWN; 364 break; 365 } 366 367 if (val & MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX) 368 phydev->duplex = DUPLEX_FULL; 369 else 370 phydev->duplex = DUPLEX_HALF; 371 372 return 0; 373 } 374 375 static int aqr107_read_status(struct phy_device *phydev) 376 { 377 int val, ret; 378 379 ret = aqr_read_status(phydev); 380 if (ret) 381 return ret; 382 383 if (!phydev->link || phydev->autoneg == AUTONEG_DISABLE) 384 return 0; 385 386 val = phy_read_mmd(phydev, MDIO_MMD_PHYXS, MDIO_PHYXS_VEND_IF_STATUS); 387 if (val < 0) 388 return val; 389 390 switch (FIELD_GET(MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK, val)) { 391 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR: 392 phydev->interface = PHY_INTERFACE_MODE_10GKR; 393 break; 394 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI: 395 phydev->interface = PHY_INTERFACE_MODE_10GBASER; 396 break; 397 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII: 398 phydev->interface = PHY_INTERFACE_MODE_USXGMII; 399 break; 400 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII: 401 phydev->interface = PHY_INTERFACE_MODE_SGMII; 402 break; 403 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII: 404 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 405 break; 406 default: 407 phydev->interface = PHY_INTERFACE_MODE_NA; 408 break; 409 } 410 411 /* Read possibly downshifted rate from vendor register */ 412 return aqr107_read_rate(phydev); 413 } 414 415 static int aqr107_get_downshift(struct phy_device *phydev, u8 *data) 416 { 417 int val, cnt, enable; 418 419 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV); 420 if (val < 0) 421 return val; 422 423 enable = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_EN, val); 424 cnt = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val); 425 426 *data = enable && cnt ? cnt : DOWNSHIFT_DEV_DISABLE; 427 428 return 0; 429 } 430 431 static int aqr107_set_downshift(struct phy_device *phydev, u8 cnt) 432 { 433 int val = 0; 434 435 if (!FIELD_FIT(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt)) 436 return -E2BIG; 437 438 if (cnt != DOWNSHIFT_DEV_DISABLE) { 439 val = MDIO_AN_VEND_PROV_DOWNSHIFT_EN; 440 val |= FIELD_PREP(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt); 441 } 442 443 return phy_modify_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV, 444 MDIO_AN_VEND_PROV_DOWNSHIFT_EN | 445 MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val); 446 } 447 448 static int aqr107_get_tunable(struct phy_device *phydev, 449 struct ethtool_tunable *tuna, void *data) 450 { 451 switch (tuna->id) { 452 case ETHTOOL_PHY_DOWNSHIFT: 453 return aqr107_get_downshift(phydev, data); 454 default: 455 return -EOPNOTSUPP; 456 } 457 } 458 459 static int aqr107_set_tunable(struct phy_device *phydev, 460 struct ethtool_tunable *tuna, const void *data) 461 { 462 switch (tuna->id) { 463 case ETHTOOL_PHY_DOWNSHIFT: 464 return aqr107_set_downshift(phydev, *(const u8 *)data); 465 default: 466 return -EOPNOTSUPP; 467 } 468 } 469 470 /* If we configure settings whilst firmware is still initializing the chip, 471 * then these settings may be overwritten. Therefore make sure chip 472 * initialization has completed. Use presence of the firmware ID as 473 * indicator for initialization having completed. 474 * The chip also provides a "reset completed" bit, but it's cleared after 475 * read. Therefore function would time out if called again. 476 */ 477 static int aqr107_wait_reset_complete(struct phy_device *phydev) 478 { 479 int val; 480 481 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, 482 VEND1_GLOBAL_FW_ID, val, val != 0, 483 20000, 2000000, false); 484 } 485 486 static void aqr107_chip_info(struct phy_device *phydev) 487 { 488 u8 fw_major, fw_minor, build_id, prov_id; 489 int val; 490 491 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_FW_ID); 492 if (val < 0) 493 return; 494 495 fw_major = FIELD_GET(VEND1_GLOBAL_FW_ID_MAJOR, val); 496 fw_minor = FIELD_GET(VEND1_GLOBAL_FW_ID_MINOR, val); 497 498 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT1); 499 if (val < 0) 500 return; 501 502 build_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID, val); 503 prov_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_PROV_ID, val); 504 505 phydev_dbg(phydev, "FW %u.%u, Build %u, Provisioning %u\n", 506 fw_major, fw_minor, build_id, prov_id); 507 } 508 509 static int aqr107_config_init(struct phy_device *phydev) 510 { 511 int ret; 512 513 /* Check that the PHY interface type is compatible */ 514 if (phydev->interface != PHY_INTERFACE_MODE_SGMII && 515 phydev->interface != PHY_INTERFACE_MODE_2500BASEX && 516 phydev->interface != PHY_INTERFACE_MODE_XGMII && 517 phydev->interface != PHY_INTERFACE_MODE_USXGMII && 518 phydev->interface != PHY_INTERFACE_MODE_10GKR && 519 phydev->interface != PHY_INTERFACE_MODE_10GBASER) 520 return -ENODEV; 521 522 WARN(phydev->interface == PHY_INTERFACE_MODE_XGMII, 523 "Your devicetree is out of date, please update it. The AQR107 family doesn't support XGMII, maybe you mean USXGMII.\n"); 524 525 ret = aqr107_wait_reset_complete(phydev); 526 if (!ret) 527 aqr107_chip_info(phydev); 528 529 return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT); 530 } 531 532 static int aqcs109_config_init(struct phy_device *phydev) 533 { 534 int ret; 535 536 /* Check that the PHY interface type is compatible */ 537 if (phydev->interface != PHY_INTERFACE_MODE_SGMII && 538 phydev->interface != PHY_INTERFACE_MODE_2500BASEX) 539 return -ENODEV; 540 541 ret = aqr107_wait_reset_complete(phydev); 542 if (!ret) 543 aqr107_chip_info(phydev); 544 545 /* AQCS109 belongs to a chip family partially supporting 10G and 5G. 546 * PMA speed ability bits are the same for all members of the family, 547 * AQCS109 however supports speeds up to 2.5G only. 548 */ 549 phy_set_max_speed(phydev, SPEED_2500); 550 551 return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT); 552 } 553 554 static void aqr107_link_change_notify(struct phy_device *phydev) 555 { 556 u8 fw_major, fw_minor; 557 bool downshift, short_reach, afr; 558 int mode, val; 559 560 if (phydev->state != PHY_RUNNING || phydev->autoneg == AUTONEG_DISABLE) 561 return; 562 563 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1); 564 /* call failed or link partner is no Aquantia PHY */ 565 if (val < 0 || !(val & MDIO_AN_RX_LP_STAT1_AQ_PHY)) 566 return; 567 568 short_reach = val & MDIO_AN_RX_LP_STAT1_SHORT_REACH; 569 downshift = val & MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT; 570 571 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT4); 572 if (val < 0) 573 return; 574 575 fw_major = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MAJOR, val); 576 fw_minor = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MINOR, val); 577 578 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_VEND_STAT3); 579 if (val < 0) 580 return; 581 582 afr = val & MDIO_AN_RX_VEND_STAT3_AFR; 583 584 phydev_dbg(phydev, "Link partner is Aquantia PHY, FW %u.%u%s%s%s\n", 585 fw_major, fw_minor, 586 short_reach ? ", short reach mode" : "", 587 downshift ? ", fast-retrain downshift advertised" : "", 588 afr ? ", fast reframe advertised" : ""); 589 590 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT9); 591 if (val < 0) 592 return; 593 594 mode = FIELD_GET(VEND1_GLOBAL_RSVD_STAT9_MODE, val); 595 if (mode == VEND1_GLOBAL_RSVD_STAT9_1000BT2) 596 phydev_info(phydev, "Aquantia 1000Base-T2 mode active\n"); 597 } 598 599 static int aqr107_suspend(struct phy_device *phydev) 600 { 601 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1, 602 MDIO_CTRL1_LPOWER); 603 } 604 605 static int aqr107_resume(struct phy_device *phydev) 606 { 607 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1, 608 MDIO_CTRL1_LPOWER); 609 } 610 611 static int aqr107_probe(struct phy_device *phydev) 612 { 613 phydev->priv = devm_kzalloc(&phydev->mdio.dev, 614 sizeof(struct aqr107_priv), GFP_KERNEL); 615 if (!phydev->priv) 616 return -ENOMEM; 617 618 return aqr_hwmon_probe(phydev); 619 } 620 621 static struct phy_driver aqr_driver[] = { 622 { 623 PHY_ID_MATCH_MODEL(PHY_ID_AQ1202), 624 .name = "Aquantia AQ1202", 625 .config_aneg = aqr_config_aneg, 626 .config_intr = aqr_config_intr, 627 .handle_interrupt = aqr_handle_interrupt, 628 .read_status = aqr_read_status, 629 }, 630 { 631 PHY_ID_MATCH_MODEL(PHY_ID_AQ2104), 632 .name = "Aquantia AQ2104", 633 .config_aneg = aqr_config_aneg, 634 .config_intr = aqr_config_intr, 635 .handle_interrupt = aqr_handle_interrupt, 636 .read_status = aqr_read_status, 637 }, 638 { 639 PHY_ID_MATCH_MODEL(PHY_ID_AQR105), 640 .name = "Aquantia AQR105", 641 .config_aneg = aqr_config_aneg, 642 .config_intr = aqr_config_intr, 643 .handle_interrupt = aqr_handle_interrupt, 644 .read_status = aqr_read_status, 645 .suspend = aqr107_suspend, 646 .resume = aqr107_resume, 647 }, 648 { 649 PHY_ID_MATCH_MODEL(PHY_ID_AQR106), 650 .name = "Aquantia AQR106", 651 .config_aneg = aqr_config_aneg, 652 .config_intr = aqr_config_intr, 653 .handle_interrupt = aqr_handle_interrupt, 654 .read_status = aqr_read_status, 655 }, 656 { 657 PHY_ID_MATCH_MODEL(PHY_ID_AQR107), 658 .name = "Aquantia AQR107", 659 .probe = aqr107_probe, 660 .config_init = aqr107_config_init, 661 .config_aneg = aqr_config_aneg, 662 .config_intr = aqr_config_intr, 663 .handle_interrupt = aqr_handle_interrupt, 664 .read_status = aqr107_read_status, 665 .get_tunable = aqr107_get_tunable, 666 .set_tunable = aqr107_set_tunable, 667 .suspend = aqr107_suspend, 668 .resume = aqr107_resume, 669 .get_sset_count = aqr107_get_sset_count, 670 .get_strings = aqr107_get_strings, 671 .get_stats = aqr107_get_stats, 672 .link_change_notify = aqr107_link_change_notify, 673 }, 674 { 675 PHY_ID_MATCH_MODEL(PHY_ID_AQCS109), 676 .name = "Aquantia AQCS109", 677 .probe = aqr107_probe, 678 .config_init = aqcs109_config_init, 679 .config_aneg = aqr_config_aneg, 680 .config_intr = aqr_config_intr, 681 .handle_interrupt = aqr_handle_interrupt, 682 .read_status = aqr107_read_status, 683 .get_tunable = aqr107_get_tunable, 684 .set_tunable = aqr107_set_tunable, 685 .suspend = aqr107_suspend, 686 .resume = aqr107_resume, 687 .get_sset_count = aqr107_get_sset_count, 688 .get_strings = aqr107_get_strings, 689 .get_stats = aqr107_get_stats, 690 .link_change_notify = aqr107_link_change_notify, 691 }, 692 { 693 PHY_ID_MATCH_MODEL(PHY_ID_AQR405), 694 .name = "Aquantia AQR405", 695 .config_aneg = aqr_config_aneg, 696 .config_intr = aqr_config_intr, 697 .handle_interrupt = aqr_handle_interrupt, 698 .read_status = aqr_read_status, 699 }, 700 }; 701 702 module_phy_driver(aqr_driver); 703 704 static struct mdio_device_id __maybe_unused aqr_tbl[] = { 705 { PHY_ID_MATCH_MODEL(PHY_ID_AQ1202) }, 706 { PHY_ID_MATCH_MODEL(PHY_ID_AQ2104) }, 707 { PHY_ID_MATCH_MODEL(PHY_ID_AQR105) }, 708 { PHY_ID_MATCH_MODEL(PHY_ID_AQR106) }, 709 { PHY_ID_MATCH_MODEL(PHY_ID_AQR107) }, 710 { PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) }, 711 { PHY_ID_MATCH_MODEL(PHY_ID_AQR405) }, 712 { } 713 }; 714 715 MODULE_DEVICE_TABLE(mdio, aqr_tbl); 716 717 MODULE_DESCRIPTION("Aquantia PHY driver"); 718 MODULE_AUTHOR("Shaohui Xie <Shaohui.Xie@freescale.com>"); 719 MODULE_LICENSE("GPL v2"); 720