1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for Aquantia PHY 4 * 5 * Author: Shaohui Xie <Shaohui.Xie@freescale.com> 6 * 7 * Copyright 2015 Freescale Semiconductor, Inc. 8 */ 9 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/delay.h> 13 #include <linux/bitfield.h> 14 #include <linux/phy.h> 15 16 #include "aquantia.h" 17 18 #define PHY_ID_AQ1202 0x03a1b445 19 #define PHY_ID_AQ2104 0x03a1b460 20 #define PHY_ID_AQR105 0x03a1b4a2 21 #define PHY_ID_AQR106 0x03a1b4d0 22 #define PHY_ID_AQR107 0x03a1b4e0 23 #define PHY_ID_AQCS109 0x03a1b5c2 24 #define PHY_ID_AQR405 0x03a1b4b0 25 #define PHY_ID_AQR113C 0x31c31c12 26 27 #define MDIO_PHYXS_VEND_IF_STATUS 0xe812 28 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK GENMASK(7, 3) 29 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR 0 30 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KX 1 31 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI 2 32 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII 3 33 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_XAUI 4 34 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII 6 35 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_RXAUI 7 36 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII 10 37 38 #define MDIO_AN_VEND_PROV 0xc400 39 #define MDIO_AN_VEND_PROV_1000BASET_FULL BIT(15) 40 #define MDIO_AN_VEND_PROV_1000BASET_HALF BIT(14) 41 #define MDIO_AN_VEND_PROV_5000BASET_FULL BIT(11) 42 #define MDIO_AN_VEND_PROV_2500BASET_FULL BIT(10) 43 #define MDIO_AN_VEND_PROV_DOWNSHIFT_EN BIT(4) 44 #define MDIO_AN_VEND_PROV_DOWNSHIFT_MASK GENMASK(3, 0) 45 #define MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT 4 46 47 #define MDIO_AN_TX_VEND_STATUS1 0xc800 48 #define MDIO_AN_TX_VEND_STATUS1_RATE_MASK GENMASK(3, 1) 49 #define MDIO_AN_TX_VEND_STATUS1_10BASET 0 50 #define MDIO_AN_TX_VEND_STATUS1_100BASETX 1 51 #define MDIO_AN_TX_VEND_STATUS1_1000BASET 2 52 #define MDIO_AN_TX_VEND_STATUS1_10GBASET 3 53 #define MDIO_AN_TX_VEND_STATUS1_2500BASET 4 54 #define MDIO_AN_TX_VEND_STATUS1_5000BASET 5 55 #define MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX BIT(0) 56 57 #define MDIO_AN_TX_VEND_INT_STATUS1 0xcc00 58 #define MDIO_AN_TX_VEND_INT_STATUS1_DOWNSHIFT BIT(1) 59 60 #define MDIO_AN_TX_VEND_INT_STATUS2 0xcc01 61 #define MDIO_AN_TX_VEND_INT_STATUS2_MASK BIT(0) 62 63 #define MDIO_AN_TX_VEND_INT_MASK2 0xd401 64 #define MDIO_AN_TX_VEND_INT_MASK2_LINK BIT(0) 65 66 #define MDIO_AN_RX_LP_STAT1 0xe820 67 #define MDIO_AN_RX_LP_STAT1_1000BASET_FULL BIT(15) 68 #define MDIO_AN_RX_LP_STAT1_1000BASET_HALF BIT(14) 69 #define MDIO_AN_RX_LP_STAT1_SHORT_REACH BIT(13) 70 #define MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT BIT(12) 71 #define MDIO_AN_RX_LP_STAT1_AQ_PHY BIT(2) 72 73 #define MDIO_AN_RX_LP_STAT4 0xe823 74 #define MDIO_AN_RX_LP_STAT4_FW_MAJOR GENMASK(15, 8) 75 #define MDIO_AN_RX_LP_STAT4_FW_MINOR GENMASK(7, 0) 76 77 #define MDIO_AN_RX_VEND_STAT3 0xe832 78 #define MDIO_AN_RX_VEND_STAT3_AFR BIT(0) 79 80 /* MDIO_MMD_C22EXT */ 81 #define MDIO_C22EXT_STAT_SGMII_RX_GOOD_FRAMES 0xd292 82 #define MDIO_C22EXT_STAT_SGMII_RX_BAD_FRAMES 0xd294 83 #define MDIO_C22EXT_STAT_SGMII_RX_FALSE_CARRIER 0xd297 84 #define MDIO_C22EXT_STAT_SGMII_TX_GOOD_FRAMES 0xd313 85 #define MDIO_C22EXT_STAT_SGMII_TX_BAD_FRAMES 0xd315 86 #define MDIO_C22EXT_STAT_SGMII_TX_FALSE_CARRIER 0xd317 87 #define MDIO_C22EXT_STAT_SGMII_TX_COLLISIONS 0xd318 88 #define MDIO_C22EXT_STAT_SGMII_TX_LINE_COLLISIONS 0xd319 89 #define MDIO_C22EXT_STAT_SGMII_TX_FRAME_ALIGN_ERR 0xd31a 90 #define MDIO_C22EXT_STAT_SGMII_TX_RUNT_FRAMES 0xd31b 91 92 /* Vendor specific 1, MDIO_MMD_VEND1 */ 93 #define VEND1_GLOBAL_FW_ID 0x0020 94 #define VEND1_GLOBAL_FW_ID_MAJOR GENMASK(15, 8) 95 #define VEND1_GLOBAL_FW_ID_MINOR GENMASK(7, 0) 96 97 #define VEND1_GLOBAL_GEN_STAT2 0xc831 98 #define VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG BIT(15) 99 100 /* The following registers all have similar layouts; first the registers... */ 101 #define VEND1_GLOBAL_CFG_10M 0x0310 102 #define VEND1_GLOBAL_CFG_100M 0x031b 103 #define VEND1_GLOBAL_CFG_1G 0x031c 104 #define VEND1_GLOBAL_CFG_2_5G 0x031d 105 #define VEND1_GLOBAL_CFG_5G 0x031e 106 #define VEND1_GLOBAL_CFG_10G 0x031f 107 /* ...and now the fields */ 108 #define VEND1_GLOBAL_CFG_RATE_ADAPT GENMASK(8, 7) 109 #define VEND1_GLOBAL_CFG_RATE_ADAPT_NONE 0 110 #define VEND1_GLOBAL_CFG_RATE_ADAPT_USX 1 111 #define VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE 2 112 113 #define VEND1_GLOBAL_RSVD_STAT1 0xc885 114 #define VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID GENMASK(7, 4) 115 #define VEND1_GLOBAL_RSVD_STAT1_PROV_ID GENMASK(3, 0) 116 117 #define VEND1_GLOBAL_RSVD_STAT9 0xc88d 118 #define VEND1_GLOBAL_RSVD_STAT9_MODE GENMASK(7, 0) 119 #define VEND1_GLOBAL_RSVD_STAT9_1000BT2 0x23 120 121 #define VEND1_GLOBAL_INT_STD_STATUS 0xfc00 122 #define VEND1_GLOBAL_INT_VEND_STATUS 0xfc01 123 124 #define VEND1_GLOBAL_INT_STD_MASK 0xff00 125 #define VEND1_GLOBAL_INT_STD_MASK_PMA1 BIT(15) 126 #define VEND1_GLOBAL_INT_STD_MASK_PMA2 BIT(14) 127 #define VEND1_GLOBAL_INT_STD_MASK_PCS1 BIT(13) 128 #define VEND1_GLOBAL_INT_STD_MASK_PCS2 BIT(12) 129 #define VEND1_GLOBAL_INT_STD_MASK_PCS3 BIT(11) 130 #define VEND1_GLOBAL_INT_STD_MASK_PHY_XS1 BIT(10) 131 #define VEND1_GLOBAL_INT_STD_MASK_PHY_XS2 BIT(9) 132 #define VEND1_GLOBAL_INT_STD_MASK_AN1 BIT(8) 133 #define VEND1_GLOBAL_INT_STD_MASK_AN2 BIT(7) 134 #define VEND1_GLOBAL_INT_STD_MASK_GBE BIT(6) 135 #define VEND1_GLOBAL_INT_STD_MASK_ALL BIT(0) 136 137 #define VEND1_GLOBAL_INT_VEND_MASK 0xff01 138 #define VEND1_GLOBAL_INT_VEND_MASK_PMA BIT(15) 139 #define VEND1_GLOBAL_INT_VEND_MASK_PCS BIT(14) 140 #define VEND1_GLOBAL_INT_VEND_MASK_PHY_XS BIT(13) 141 #define VEND1_GLOBAL_INT_VEND_MASK_AN BIT(12) 142 #define VEND1_GLOBAL_INT_VEND_MASK_GBE BIT(11) 143 #define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL1 BIT(2) 144 #define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL2 BIT(1) 145 #define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 BIT(0) 146 147 /* Sleep and timeout for checking if the Processor-Intensive 148 * MDIO operation is finished 149 */ 150 #define AQR107_OP_IN_PROG_SLEEP 1000 151 #define AQR107_OP_IN_PROG_TIMEOUT 100000 152 153 struct aqr107_hw_stat { 154 const char *name; 155 int reg; 156 int size; 157 }; 158 159 #define SGMII_STAT(n, r, s) { n, MDIO_C22EXT_STAT_SGMII_ ## r, s } 160 static const struct aqr107_hw_stat aqr107_hw_stats[] = { 161 SGMII_STAT("sgmii_rx_good_frames", RX_GOOD_FRAMES, 26), 162 SGMII_STAT("sgmii_rx_bad_frames", RX_BAD_FRAMES, 26), 163 SGMII_STAT("sgmii_rx_false_carrier_events", RX_FALSE_CARRIER, 8), 164 SGMII_STAT("sgmii_tx_good_frames", TX_GOOD_FRAMES, 26), 165 SGMII_STAT("sgmii_tx_bad_frames", TX_BAD_FRAMES, 26), 166 SGMII_STAT("sgmii_tx_false_carrier_events", TX_FALSE_CARRIER, 8), 167 SGMII_STAT("sgmii_tx_collisions", TX_COLLISIONS, 8), 168 SGMII_STAT("sgmii_tx_line_collisions", TX_LINE_COLLISIONS, 8), 169 SGMII_STAT("sgmii_tx_frame_alignment_err", TX_FRAME_ALIGN_ERR, 16), 170 SGMII_STAT("sgmii_tx_runt_frames", TX_RUNT_FRAMES, 22), 171 }; 172 #define AQR107_SGMII_STAT_SZ ARRAY_SIZE(aqr107_hw_stats) 173 174 struct aqr107_priv { 175 u64 sgmii_stats[AQR107_SGMII_STAT_SZ]; 176 }; 177 178 static int aqr107_get_sset_count(struct phy_device *phydev) 179 { 180 return AQR107_SGMII_STAT_SZ; 181 } 182 183 static void aqr107_get_strings(struct phy_device *phydev, u8 *data) 184 { 185 int i; 186 187 for (i = 0; i < AQR107_SGMII_STAT_SZ; i++) 188 strscpy(data + i * ETH_GSTRING_LEN, aqr107_hw_stats[i].name, 189 ETH_GSTRING_LEN); 190 } 191 192 static u64 aqr107_get_stat(struct phy_device *phydev, int index) 193 { 194 const struct aqr107_hw_stat *stat = aqr107_hw_stats + index; 195 int len_l = min(stat->size, 16); 196 int len_h = stat->size - len_l; 197 u64 ret; 198 int val; 199 200 val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg); 201 if (val < 0) 202 return U64_MAX; 203 204 ret = val & GENMASK(len_l - 1, 0); 205 if (len_h) { 206 val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg + 1); 207 if (val < 0) 208 return U64_MAX; 209 210 ret += (val & GENMASK(len_h - 1, 0)) << 16; 211 } 212 213 return ret; 214 } 215 216 static void aqr107_get_stats(struct phy_device *phydev, 217 struct ethtool_stats *stats, u64 *data) 218 { 219 struct aqr107_priv *priv = phydev->priv; 220 u64 val; 221 int i; 222 223 for (i = 0; i < AQR107_SGMII_STAT_SZ; i++) { 224 val = aqr107_get_stat(phydev, i); 225 if (val == U64_MAX) 226 phydev_err(phydev, "Reading HW Statistics failed for %s\n", 227 aqr107_hw_stats[i].name); 228 else 229 priv->sgmii_stats[i] += val; 230 231 data[i] = priv->sgmii_stats[i]; 232 } 233 } 234 235 static int aqr_config_aneg(struct phy_device *phydev) 236 { 237 bool changed = false; 238 u16 reg; 239 int ret; 240 241 if (phydev->autoneg == AUTONEG_DISABLE) 242 return genphy_c45_pma_setup_forced(phydev); 243 244 ret = genphy_c45_an_config_aneg(phydev); 245 if (ret < 0) 246 return ret; 247 if (ret > 0) 248 changed = true; 249 250 /* Clause 45 has no standardized support for 1000BaseT, therefore 251 * use vendor registers for this mode. 252 */ 253 reg = 0; 254 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 255 phydev->advertising)) 256 reg |= MDIO_AN_VEND_PROV_1000BASET_FULL; 257 258 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, 259 phydev->advertising)) 260 reg |= MDIO_AN_VEND_PROV_1000BASET_HALF; 261 262 /* Handle the case when the 2.5G and 5G speeds are not advertised */ 263 if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 264 phydev->advertising)) 265 reg |= MDIO_AN_VEND_PROV_2500BASET_FULL; 266 267 if (linkmode_test_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 268 phydev->advertising)) 269 reg |= MDIO_AN_VEND_PROV_5000BASET_FULL; 270 271 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV, 272 MDIO_AN_VEND_PROV_1000BASET_HALF | 273 MDIO_AN_VEND_PROV_1000BASET_FULL | 274 MDIO_AN_VEND_PROV_2500BASET_FULL | 275 MDIO_AN_VEND_PROV_5000BASET_FULL, reg); 276 if (ret < 0) 277 return ret; 278 if (ret > 0) 279 changed = true; 280 281 return genphy_c45_check_and_restart_aneg(phydev, changed); 282 } 283 284 static int aqr_config_intr(struct phy_device *phydev) 285 { 286 bool en = phydev->interrupts == PHY_INTERRUPT_ENABLED; 287 int err; 288 289 if (en) { 290 /* Clear any pending interrupts before enabling them */ 291 err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2); 292 if (err < 0) 293 return err; 294 } 295 296 err = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_MASK2, 297 en ? MDIO_AN_TX_VEND_INT_MASK2_LINK : 0); 298 if (err < 0) 299 return err; 300 301 err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_STD_MASK, 302 en ? VEND1_GLOBAL_INT_STD_MASK_ALL : 0); 303 if (err < 0) 304 return err; 305 306 err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_VEND_MASK, 307 en ? VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 | 308 VEND1_GLOBAL_INT_VEND_MASK_AN : 0); 309 if (err < 0) 310 return err; 311 312 if (!en) { 313 /* Clear any pending interrupts after we have disabled them */ 314 err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2); 315 if (err < 0) 316 return err; 317 } 318 319 return 0; 320 } 321 322 static irqreturn_t aqr_handle_interrupt(struct phy_device *phydev) 323 { 324 int irq_status; 325 326 irq_status = phy_read_mmd(phydev, MDIO_MMD_AN, 327 MDIO_AN_TX_VEND_INT_STATUS2); 328 if (irq_status < 0) { 329 phy_error(phydev); 330 return IRQ_NONE; 331 } 332 333 if (!(irq_status & MDIO_AN_TX_VEND_INT_STATUS2_MASK)) 334 return IRQ_NONE; 335 336 phy_trigger_machine(phydev); 337 338 return IRQ_HANDLED; 339 } 340 341 static int aqr_read_status(struct phy_device *phydev) 342 { 343 int val; 344 345 if (phydev->autoneg == AUTONEG_ENABLE) { 346 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1); 347 if (val < 0) 348 return val; 349 350 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 351 phydev->lp_advertising, 352 val & MDIO_AN_RX_LP_STAT1_1000BASET_FULL); 353 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, 354 phydev->lp_advertising, 355 val & MDIO_AN_RX_LP_STAT1_1000BASET_HALF); 356 } 357 358 return genphy_c45_read_status(phydev); 359 } 360 361 static int aqr107_read_rate(struct phy_device *phydev) 362 { 363 u32 config_reg; 364 int val; 365 366 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_STATUS1); 367 if (val < 0) 368 return val; 369 370 if (val & MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX) 371 phydev->duplex = DUPLEX_FULL; 372 else 373 phydev->duplex = DUPLEX_HALF; 374 375 switch (FIELD_GET(MDIO_AN_TX_VEND_STATUS1_RATE_MASK, val)) { 376 case MDIO_AN_TX_VEND_STATUS1_10BASET: 377 phydev->speed = SPEED_10; 378 config_reg = VEND1_GLOBAL_CFG_10M; 379 break; 380 case MDIO_AN_TX_VEND_STATUS1_100BASETX: 381 phydev->speed = SPEED_100; 382 config_reg = VEND1_GLOBAL_CFG_100M; 383 break; 384 case MDIO_AN_TX_VEND_STATUS1_1000BASET: 385 phydev->speed = SPEED_1000; 386 config_reg = VEND1_GLOBAL_CFG_1G; 387 break; 388 case MDIO_AN_TX_VEND_STATUS1_2500BASET: 389 phydev->speed = SPEED_2500; 390 config_reg = VEND1_GLOBAL_CFG_2_5G; 391 break; 392 case MDIO_AN_TX_VEND_STATUS1_5000BASET: 393 phydev->speed = SPEED_5000; 394 config_reg = VEND1_GLOBAL_CFG_5G; 395 break; 396 case MDIO_AN_TX_VEND_STATUS1_10GBASET: 397 phydev->speed = SPEED_10000; 398 config_reg = VEND1_GLOBAL_CFG_10G; 399 break; 400 default: 401 phydev->speed = SPEED_UNKNOWN; 402 return 0; 403 } 404 405 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, config_reg); 406 if (val < 0) 407 return val; 408 409 if (FIELD_GET(VEND1_GLOBAL_CFG_RATE_ADAPT, val) == 410 VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE) 411 phydev->rate_matching = RATE_MATCH_PAUSE; 412 else 413 phydev->rate_matching = RATE_MATCH_NONE; 414 415 return 0; 416 } 417 418 static int aqr107_read_status(struct phy_device *phydev) 419 { 420 int val, ret; 421 422 ret = aqr_read_status(phydev); 423 if (ret) 424 return ret; 425 426 if (!phydev->link || phydev->autoneg == AUTONEG_DISABLE) 427 return 0; 428 429 val = phy_read_mmd(phydev, MDIO_MMD_PHYXS, MDIO_PHYXS_VEND_IF_STATUS); 430 if (val < 0) 431 return val; 432 433 switch (FIELD_GET(MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK, val)) { 434 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR: 435 phydev->interface = PHY_INTERFACE_MODE_10GKR; 436 break; 437 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KX: 438 phydev->interface = PHY_INTERFACE_MODE_1000BASEKX; 439 break; 440 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI: 441 phydev->interface = PHY_INTERFACE_MODE_10GBASER; 442 break; 443 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII: 444 phydev->interface = PHY_INTERFACE_MODE_USXGMII; 445 break; 446 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XAUI: 447 phydev->interface = PHY_INTERFACE_MODE_XAUI; 448 break; 449 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII: 450 phydev->interface = PHY_INTERFACE_MODE_SGMII; 451 break; 452 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_RXAUI: 453 phydev->interface = PHY_INTERFACE_MODE_RXAUI; 454 break; 455 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII: 456 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 457 break; 458 default: 459 phydev->interface = PHY_INTERFACE_MODE_NA; 460 break; 461 } 462 463 /* Read possibly downshifted rate from vendor register */ 464 return aqr107_read_rate(phydev); 465 } 466 467 static int aqr107_get_downshift(struct phy_device *phydev, u8 *data) 468 { 469 int val, cnt, enable; 470 471 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV); 472 if (val < 0) 473 return val; 474 475 enable = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_EN, val); 476 cnt = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val); 477 478 *data = enable && cnt ? cnt : DOWNSHIFT_DEV_DISABLE; 479 480 return 0; 481 } 482 483 static int aqr107_set_downshift(struct phy_device *phydev, u8 cnt) 484 { 485 int val = 0; 486 487 if (!FIELD_FIT(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt)) 488 return -E2BIG; 489 490 if (cnt != DOWNSHIFT_DEV_DISABLE) { 491 val = MDIO_AN_VEND_PROV_DOWNSHIFT_EN; 492 val |= FIELD_PREP(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt); 493 } 494 495 return phy_modify_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV, 496 MDIO_AN_VEND_PROV_DOWNSHIFT_EN | 497 MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val); 498 } 499 500 static int aqr107_get_tunable(struct phy_device *phydev, 501 struct ethtool_tunable *tuna, void *data) 502 { 503 switch (tuna->id) { 504 case ETHTOOL_PHY_DOWNSHIFT: 505 return aqr107_get_downshift(phydev, data); 506 default: 507 return -EOPNOTSUPP; 508 } 509 } 510 511 static int aqr107_set_tunable(struct phy_device *phydev, 512 struct ethtool_tunable *tuna, const void *data) 513 { 514 switch (tuna->id) { 515 case ETHTOOL_PHY_DOWNSHIFT: 516 return aqr107_set_downshift(phydev, *(const u8 *)data); 517 default: 518 return -EOPNOTSUPP; 519 } 520 } 521 522 /* If we configure settings whilst firmware is still initializing the chip, 523 * then these settings may be overwritten. Therefore make sure chip 524 * initialization has completed. Use presence of the firmware ID as 525 * indicator for initialization having completed. 526 * The chip also provides a "reset completed" bit, but it's cleared after 527 * read. Therefore function would time out if called again. 528 */ 529 static int aqr107_wait_reset_complete(struct phy_device *phydev) 530 { 531 int val; 532 533 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, 534 VEND1_GLOBAL_FW_ID, val, val != 0, 535 20000, 2000000, false); 536 } 537 538 static void aqr107_chip_info(struct phy_device *phydev) 539 { 540 u8 fw_major, fw_minor, build_id, prov_id; 541 int val; 542 543 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_FW_ID); 544 if (val < 0) 545 return; 546 547 fw_major = FIELD_GET(VEND1_GLOBAL_FW_ID_MAJOR, val); 548 fw_minor = FIELD_GET(VEND1_GLOBAL_FW_ID_MINOR, val); 549 550 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT1); 551 if (val < 0) 552 return; 553 554 build_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID, val); 555 prov_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_PROV_ID, val); 556 557 phydev_dbg(phydev, "FW %u.%u, Build %u, Provisioning %u\n", 558 fw_major, fw_minor, build_id, prov_id); 559 } 560 561 static int aqr107_config_init(struct phy_device *phydev) 562 { 563 int ret; 564 565 /* Check that the PHY interface type is compatible */ 566 if (phydev->interface != PHY_INTERFACE_MODE_SGMII && 567 phydev->interface != PHY_INTERFACE_MODE_1000BASEKX && 568 phydev->interface != PHY_INTERFACE_MODE_2500BASEX && 569 phydev->interface != PHY_INTERFACE_MODE_XGMII && 570 phydev->interface != PHY_INTERFACE_MODE_USXGMII && 571 phydev->interface != PHY_INTERFACE_MODE_10GKR && 572 phydev->interface != PHY_INTERFACE_MODE_10GBASER && 573 phydev->interface != PHY_INTERFACE_MODE_XAUI && 574 phydev->interface != PHY_INTERFACE_MODE_RXAUI) 575 return -ENODEV; 576 577 WARN(phydev->interface == PHY_INTERFACE_MODE_XGMII, 578 "Your devicetree is out of date, please update it. The AQR107 family doesn't support XGMII, maybe you mean USXGMII.\n"); 579 580 ret = aqr107_wait_reset_complete(phydev); 581 if (!ret) 582 aqr107_chip_info(phydev); 583 584 return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT); 585 } 586 587 static int aqcs109_config_init(struct phy_device *phydev) 588 { 589 int ret; 590 591 /* Check that the PHY interface type is compatible */ 592 if (phydev->interface != PHY_INTERFACE_MODE_SGMII && 593 phydev->interface != PHY_INTERFACE_MODE_2500BASEX) 594 return -ENODEV; 595 596 ret = aqr107_wait_reset_complete(phydev); 597 if (!ret) 598 aqr107_chip_info(phydev); 599 600 /* AQCS109 belongs to a chip family partially supporting 10G and 5G. 601 * PMA speed ability bits are the same for all members of the family, 602 * AQCS109 however supports speeds up to 2.5G only. 603 */ 604 phy_set_max_speed(phydev, SPEED_2500); 605 606 return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT); 607 } 608 609 static void aqr107_link_change_notify(struct phy_device *phydev) 610 { 611 u8 fw_major, fw_minor; 612 bool downshift, short_reach, afr; 613 int mode, val; 614 615 if (phydev->state != PHY_RUNNING || phydev->autoneg == AUTONEG_DISABLE) 616 return; 617 618 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1); 619 /* call failed or link partner is no Aquantia PHY */ 620 if (val < 0 || !(val & MDIO_AN_RX_LP_STAT1_AQ_PHY)) 621 return; 622 623 short_reach = val & MDIO_AN_RX_LP_STAT1_SHORT_REACH; 624 downshift = val & MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT; 625 626 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT4); 627 if (val < 0) 628 return; 629 630 fw_major = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MAJOR, val); 631 fw_minor = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MINOR, val); 632 633 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_VEND_STAT3); 634 if (val < 0) 635 return; 636 637 afr = val & MDIO_AN_RX_VEND_STAT3_AFR; 638 639 phydev_dbg(phydev, "Link partner is Aquantia PHY, FW %u.%u%s%s%s\n", 640 fw_major, fw_minor, 641 short_reach ? ", short reach mode" : "", 642 downshift ? ", fast-retrain downshift advertised" : "", 643 afr ? ", fast reframe advertised" : ""); 644 645 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT9); 646 if (val < 0) 647 return; 648 649 mode = FIELD_GET(VEND1_GLOBAL_RSVD_STAT9_MODE, val); 650 if (mode == VEND1_GLOBAL_RSVD_STAT9_1000BT2) 651 phydev_info(phydev, "Aquantia 1000Base-T2 mode active\n"); 652 } 653 654 static int aqr107_wait_processor_intensive_op(struct phy_device *phydev) 655 { 656 int val, err; 657 658 /* The datasheet notes to wait at least 1ms after issuing a 659 * processor intensive operation before checking. 660 * We cannot use the 'sleep_before_read' parameter of read_poll_timeout 661 * because that just determines the maximum time slept, not the minimum. 662 */ 663 usleep_range(1000, 5000); 664 665 err = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, 666 VEND1_GLOBAL_GEN_STAT2, val, 667 !(val & VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG), 668 AQR107_OP_IN_PROG_SLEEP, 669 AQR107_OP_IN_PROG_TIMEOUT, false); 670 if (err) { 671 phydev_err(phydev, "timeout: processor-intensive MDIO operation\n"); 672 return err; 673 } 674 675 return 0; 676 } 677 678 static int aqr107_get_rate_matching(struct phy_device *phydev, 679 phy_interface_t iface) 680 { 681 if (iface == PHY_INTERFACE_MODE_10GBASER || 682 iface == PHY_INTERFACE_MODE_2500BASEX || 683 iface == PHY_INTERFACE_MODE_NA) 684 return RATE_MATCH_PAUSE; 685 return RATE_MATCH_NONE; 686 } 687 688 static int aqr107_suspend(struct phy_device *phydev) 689 { 690 int err; 691 692 err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1, 693 MDIO_CTRL1_LPOWER); 694 if (err) 695 return err; 696 697 return aqr107_wait_processor_intensive_op(phydev); 698 } 699 700 static int aqr107_resume(struct phy_device *phydev) 701 { 702 int err; 703 704 err = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1, 705 MDIO_CTRL1_LPOWER); 706 if (err) 707 return err; 708 709 return aqr107_wait_processor_intensive_op(phydev); 710 } 711 712 static int aqr107_probe(struct phy_device *phydev) 713 { 714 phydev->priv = devm_kzalloc(&phydev->mdio.dev, 715 sizeof(struct aqr107_priv), GFP_KERNEL); 716 if (!phydev->priv) 717 return -ENOMEM; 718 719 return aqr_hwmon_probe(phydev); 720 } 721 722 static struct phy_driver aqr_driver[] = { 723 { 724 PHY_ID_MATCH_MODEL(PHY_ID_AQ1202), 725 .name = "Aquantia AQ1202", 726 .config_aneg = aqr_config_aneg, 727 .config_intr = aqr_config_intr, 728 .handle_interrupt = aqr_handle_interrupt, 729 .read_status = aqr_read_status, 730 }, 731 { 732 PHY_ID_MATCH_MODEL(PHY_ID_AQ2104), 733 .name = "Aquantia AQ2104", 734 .config_aneg = aqr_config_aneg, 735 .config_intr = aqr_config_intr, 736 .handle_interrupt = aqr_handle_interrupt, 737 .read_status = aqr_read_status, 738 }, 739 { 740 PHY_ID_MATCH_MODEL(PHY_ID_AQR105), 741 .name = "Aquantia AQR105", 742 .config_aneg = aqr_config_aneg, 743 .config_intr = aqr_config_intr, 744 .handle_interrupt = aqr_handle_interrupt, 745 .read_status = aqr_read_status, 746 .suspend = aqr107_suspend, 747 .resume = aqr107_resume, 748 }, 749 { 750 PHY_ID_MATCH_MODEL(PHY_ID_AQR106), 751 .name = "Aquantia AQR106", 752 .config_aneg = aqr_config_aneg, 753 .config_intr = aqr_config_intr, 754 .handle_interrupt = aqr_handle_interrupt, 755 .read_status = aqr_read_status, 756 }, 757 { 758 PHY_ID_MATCH_MODEL(PHY_ID_AQR107), 759 .name = "Aquantia AQR107", 760 .probe = aqr107_probe, 761 .get_rate_matching = aqr107_get_rate_matching, 762 .config_init = aqr107_config_init, 763 .config_aneg = aqr_config_aneg, 764 .config_intr = aqr_config_intr, 765 .handle_interrupt = aqr_handle_interrupt, 766 .read_status = aqr107_read_status, 767 .get_tunable = aqr107_get_tunable, 768 .set_tunable = aqr107_set_tunable, 769 .suspend = aqr107_suspend, 770 .resume = aqr107_resume, 771 .get_sset_count = aqr107_get_sset_count, 772 .get_strings = aqr107_get_strings, 773 .get_stats = aqr107_get_stats, 774 .link_change_notify = aqr107_link_change_notify, 775 }, 776 { 777 PHY_ID_MATCH_MODEL(PHY_ID_AQCS109), 778 .name = "Aquantia AQCS109", 779 .probe = aqr107_probe, 780 .get_rate_matching = aqr107_get_rate_matching, 781 .config_init = aqcs109_config_init, 782 .config_aneg = aqr_config_aneg, 783 .config_intr = aqr_config_intr, 784 .handle_interrupt = aqr_handle_interrupt, 785 .read_status = aqr107_read_status, 786 .get_tunable = aqr107_get_tunable, 787 .set_tunable = aqr107_set_tunable, 788 .suspend = aqr107_suspend, 789 .resume = aqr107_resume, 790 .get_sset_count = aqr107_get_sset_count, 791 .get_strings = aqr107_get_strings, 792 .get_stats = aqr107_get_stats, 793 .link_change_notify = aqr107_link_change_notify, 794 }, 795 { 796 PHY_ID_MATCH_MODEL(PHY_ID_AQR405), 797 .name = "Aquantia AQR405", 798 .config_aneg = aqr_config_aneg, 799 .config_intr = aqr_config_intr, 800 .handle_interrupt = aqr_handle_interrupt, 801 .read_status = aqr_read_status, 802 }, 803 { 804 PHY_ID_MATCH_MODEL(PHY_ID_AQR113C), 805 .name = "Aquantia AQR113C", 806 .probe = aqr107_probe, 807 .get_rate_matching = aqr107_get_rate_matching, 808 .config_init = aqr107_config_init, 809 .config_aneg = aqr_config_aneg, 810 .config_intr = aqr_config_intr, 811 .handle_interrupt = aqr_handle_interrupt, 812 .read_status = aqr107_read_status, 813 .get_tunable = aqr107_get_tunable, 814 .set_tunable = aqr107_set_tunable, 815 .suspend = aqr107_suspend, 816 .resume = aqr107_resume, 817 .get_sset_count = aqr107_get_sset_count, 818 .get_strings = aqr107_get_strings, 819 .get_stats = aqr107_get_stats, 820 .link_change_notify = aqr107_link_change_notify, 821 }, 822 }; 823 824 module_phy_driver(aqr_driver); 825 826 static struct mdio_device_id __maybe_unused aqr_tbl[] = { 827 { PHY_ID_MATCH_MODEL(PHY_ID_AQ1202) }, 828 { PHY_ID_MATCH_MODEL(PHY_ID_AQ2104) }, 829 { PHY_ID_MATCH_MODEL(PHY_ID_AQR105) }, 830 { PHY_ID_MATCH_MODEL(PHY_ID_AQR106) }, 831 { PHY_ID_MATCH_MODEL(PHY_ID_AQR107) }, 832 { PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) }, 833 { PHY_ID_MATCH_MODEL(PHY_ID_AQR405) }, 834 { PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) }, 835 { } 836 }; 837 838 MODULE_DEVICE_TABLE(mdio, aqr_tbl); 839 840 MODULE_DESCRIPTION("Aquantia PHY driver"); 841 MODULE_AUTHOR("Shaohui Xie <Shaohui.Xie@freescale.com>"); 842 MODULE_LICENSE("GPL v2"); 843