1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for Aquantia PHY 4 * 5 * Author: Shaohui Xie <Shaohui.Xie@freescale.com> 6 * 7 * Copyright 2015 Freescale Semiconductor, Inc. 8 */ 9 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/delay.h> 13 #include <linux/bitfield.h> 14 #include <linux/phy.h> 15 16 #include "aquantia.h" 17 18 #define PHY_ID_AQ1202 0x03a1b445 19 #define PHY_ID_AQ2104 0x03a1b460 20 #define PHY_ID_AQR105 0x03a1b4a2 21 #define PHY_ID_AQR106 0x03a1b4d0 22 #define PHY_ID_AQR107 0x03a1b4e0 23 #define PHY_ID_AQCS109 0x03a1b5c2 24 #define PHY_ID_AQR405 0x03a1b4b0 25 26 #define MDIO_PHYXS_VEND_IF_STATUS 0xe812 27 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK GENMASK(7, 3) 28 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR 0 29 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI 2 30 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII 3 31 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII 6 32 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII 10 33 34 #define MDIO_AN_VEND_PROV 0xc400 35 #define MDIO_AN_VEND_PROV_1000BASET_FULL BIT(15) 36 #define MDIO_AN_VEND_PROV_1000BASET_HALF BIT(14) 37 #define MDIO_AN_VEND_PROV_DOWNSHIFT_EN BIT(4) 38 #define MDIO_AN_VEND_PROV_DOWNSHIFT_MASK GENMASK(3, 0) 39 #define MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT 4 40 41 #define MDIO_AN_TX_VEND_STATUS1 0xc800 42 #define MDIO_AN_TX_VEND_STATUS1_RATE_MASK GENMASK(3, 1) 43 #define MDIO_AN_TX_VEND_STATUS1_10BASET 0 44 #define MDIO_AN_TX_VEND_STATUS1_100BASETX 1 45 #define MDIO_AN_TX_VEND_STATUS1_1000BASET 2 46 #define MDIO_AN_TX_VEND_STATUS1_10GBASET 3 47 #define MDIO_AN_TX_VEND_STATUS1_2500BASET 4 48 #define MDIO_AN_TX_VEND_STATUS1_5000BASET 5 49 #define MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX BIT(0) 50 51 #define MDIO_AN_TX_VEND_INT_STATUS1 0xcc00 52 #define MDIO_AN_TX_VEND_INT_STATUS1_DOWNSHIFT BIT(1) 53 54 #define MDIO_AN_TX_VEND_INT_STATUS2 0xcc01 55 56 #define MDIO_AN_TX_VEND_INT_MASK2 0xd401 57 #define MDIO_AN_TX_VEND_INT_MASK2_LINK BIT(0) 58 59 #define MDIO_AN_RX_LP_STAT1 0xe820 60 #define MDIO_AN_RX_LP_STAT1_1000BASET_FULL BIT(15) 61 #define MDIO_AN_RX_LP_STAT1_1000BASET_HALF BIT(14) 62 #define MDIO_AN_RX_LP_STAT1_SHORT_REACH BIT(13) 63 #define MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT BIT(12) 64 #define MDIO_AN_RX_LP_STAT1_AQ_PHY BIT(2) 65 66 #define MDIO_AN_RX_LP_STAT4 0xe823 67 #define MDIO_AN_RX_LP_STAT4_FW_MAJOR GENMASK(15, 8) 68 #define MDIO_AN_RX_LP_STAT4_FW_MINOR GENMASK(7, 0) 69 70 #define MDIO_AN_RX_VEND_STAT3 0xe832 71 #define MDIO_AN_RX_VEND_STAT3_AFR BIT(0) 72 73 /* MDIO_MMD_C22EXT */ 74 #define MDIO_C22EXT_STAT_SGMII_RX_GOOD_FRAMES 0xd292 75 #define MDIO_C22EXT_STAT_SGMII_RX_BAD_FRAMES 0xd294 76 #define MDIO_C22EXT_STAT_SGMII_RX_FALSE_CARRIER 0xd297 77 #define MDIO_C22EXT_STAT_SGMII_TX_GOOD_FRAMES 0xd313 78 #define MDIO_C22EXT_STAT_SGMII_TX_BAD_FRAMES 0xd315 79 #define MDIO_C22EXT_STAT_SGMII_TX_FALSE_CARRIER 0xd317 80 #define MDIO_C22EXT_STAT_SGMII_TX_COLLISIONS 0xd318 81 #define MDIO_C22EXT_STAT_SGMII_TX_LINE_COLLISIONS 0xd319 82 #define MDIO_C22EXT_STAT_SGMII_TX_FRAME_ALIGN_ERR 0xd31a 83 #define MDIO_C22EXT_STAT_SGMII_TX_RUNT_FRAMES 0xd31b 84 85 /* Vendor specific 1, MDIO_MMD_VEND1 */ 86 #define VEND1_GLOBAL_FW_ID 0x0020 87 #define VEND1_GLOBAL_FW_ID_MAJOR GENMASK(15, 8) 88 #define VEND1_GLOBAL_FW_ID_MINOR GENMASK(7, 0) 89 90 #define VEND1_GLOBAL_RSVD_STAT1 0xc885 91 #define VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID GENMASK(7, 4) 92 #define VEND1_GLOBAL_RSVD_STAT1_PROV_ID GENMASK(3, 0) 93 94 #define VEND1_GLOBAL_RSVD_STAT9 0xc88d 95 #define VEND1_GLOBAL_RSVD_STAT9_MODE GENMASK(7, 0) 96 #define VEND1_GLOBAL_RSVD_STAT9_1000BT2 0x23 97 98 #define VEND1_GLOBAL_INT_STD_STATUS 0xfc00 99 #define VEND1_GLOBAL_INT_VEND_STATUS 0xfc01 100 101 #define VEND1_GLOBAL_INT_STD_MASK 0xff00 102 #define VEND1_GLOBAL_INT_STD_MASK_PMA1 BIT(15) 103 #define VEND1_GLOBAL_INT_STD_MASK_PMA2 BIT(14) 104 #define VEND1_GLOBAL_INT_STD_MASK_PCS1 BIT(13) 105 #define VEND1_GLOBAL_INT_STD_MASK_PCS2 BIT(12) 106 #define VEND1_GLOBAL_INT_STD_MASK_PCS3 BIT(11) 107 #define VEND1_GLOBAL_INT_STD_MASK_PHY_XS1 BIT(10) 108 #define VEND1_GLOBAL_INT_STD_MASK_PHY_XS2 BIT(9) 109 #define VEND1_GLOBAL_INT_STD_MASK_AN1 BIT(8) 110 #define VEND1_GLOBAL_INT_STD_MASK_AN2 BIT(7) 111 #define VEND1_GLOBAL_INT_STD_MASK_GBE BIT(6) 112 #define VEND1_GLOBAL_INT_STD_MASK_ALL BIT(0) 113 114 #define VEND1_GLOBAL_INT_VEND_MASK 0xff01 115 #define VEND1_GLOBAL_INT_VEND_MASK_PMA BIT(15) 116 #define VEND1_GLOBAL_INT_VEND_MASK_PCS BIT(14) 117 #define VEND1_GLOBAL_INT_VEND_MASK_PHY_XS BIT(13) 118 #define VEND1_GLOBAL_INT_VEND_MASK_AN BIT(12) 119 #define VEND1_GLOBAL_INT_VEND_MASK_GBE BIT(11) 120 #define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL1 BIT(2) 121 #define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL2 BIT(1) 122 #define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 BIT(0) 123 124 struct aqr107_hw_stat { 125 const char *name; 126 int reg; 127 int size; 128 }; 129 130 #define SGMII_STAT(n, r, s) { n, MDIO_C22EXT_STAT_SGMII_ ## r, s } 131 static const struct aqr107_hw_stat aqr107_hw_stats[] = { 132 SGMII_STAT("sgmii_rx_good_frames", RX_GOOD_FRAMES, 26), 133 SGMII_STAT("sgmii_rx_bad_frames", RX_BAD_FRAMES, 26), 134 SGMII_STAT("sgmii_rx_false_carrier_events", RX_FALSE_CARRIER, 8), 135 SGMII_STAT("sgmii_tx_good_frames", TX_GOOD_FRAMES, 26), 136 SGMII_STAT("sgmii_tx_bad_frames", TX_BAD_FRAMES, 26), 137 SGMII_STAT("sgmii_tx_false_carrier_events", TX_FALSE_CARRIER, 8), 138 SGMII_STAT("sgmii_tx_collisions", TX_COLLISIONS, 8), 139 SGMII_STAT("sgmii_tx_line_collisions", TX_LINE_COLLISIONS, 8), 140 SGMII_STAT("sgmii_tx_frame_alignment_err", TX_FRAME_ALIGN_ERR, 16), 141 SGMII_STAT("sgmii_tx_runt_frames", TX_RUNT_FRAMES, 22), 142 }; 143 #define AQR107_SGMII_STAT_SZ ARRAY_SIZE(aqr107_hw_stats) 144 145 struct aqr107_priv { 146 u64 sgmii_stats[AQR107_SGMII_STAT_SZ]; 147 }; 148 149 static int aqr107_get_sset_count(struct phy_device *phydev) 150 { 151 return AQR107_SGMII_STAT_SZ; 152 } 153 154 static void aqr107_get_strings(struct phy_device *phydev, u8 *data) 155 { 156 int i; 157 158 for (i = 0; i < AQR107_SGMII_STAT_SZ; i++) 159 strscpy(data + i * ETH_GSTRING_LEN, aqr107_hw_stats[i].name, 160 ETH_GSTRING_LEN); 161 } 162 163 static u64 aqr107_get_stat(struct phy_device *phydev, int index) 164 { 165 const struct aqr107_hw_stat *stat = aqr107_hw_stats + index; 166 int len_l = min(stat->size, 16); 167 int len_h = stat->size - len_l; 168 u64 ret; 169 int val; 170 171 val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg); 172 if (val < 0) 173 return U64_MAX; 174 175 ret = val & GENMASK(len_l - 1, 0); 176 if (len_h) { 177 val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg + 1); 178 if (val < 0) 179 return U64_MAX; 180 181 ret += (val & GENMASK(len_h - 1, 0)) << 16; 182 } 183 184 return ret; 185 } 186 187 static void aqr107_get_stats(struct phy_device *phydev, 188 struct ethtool_stats *stats, u64 *data) 189 { 190 struct aqr107_priv *priv = phydev->priv; 191 u64 val; 192 int i; 193 194 for (i = 0; i < AQR107_SGMII_STAT_SZ; i++) { 195 val = aqr107_get_stat(phydev, i); 196 if (val == U64_MAX) 197 phydev_err(phydev, "Reading HW Statistics failed for %s\n", 198 aqr107_hw_stats[i].name); 199 else 200 priv->sgmii_stats[i] += val; 201 202 data[i] = priv->sgmii_stats[i]; 203 } 204 } 205 206 static int aqr_config_aneg(struct phy_device *phydev) 207 { 208 bool changed = false; 209 u16 reg; 210 int ret; 211 212 if (phydev->autoneg == AUTONEG_DISABLE) 213 return genphy_c45_pma_setup_forced(phydev); 214 215 ret = genphy_c45_an_config_aneg(phydev); 216 if (ret < 0) 217 return ret; 218 if (ret > 0) 219 changed = true; 220 221 /* Clause 45 has no standardized support for 1000BaseT, therefore 222 * use vendor registers for this mode. 223 */ 224 reg = 0; 225 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 226 phydev->advertising)) 227 reg |= MDIO_AN_VEND_PROV_1000BASET_FULL; 228 229 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, 230 phydev->advertising)) 231 reg |= MDIO_AN_VEND_PROV_1000BASET_HALF; 232 233 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV, 234 MDIO_AN_VEND_PROV_1000BASET_HALF | 235 MDIO_AN_VEND_PROV_1000BASET_FULL, reg); 236 if (ret < 0) 237 return ret; 238 if (ret > 0) 239 changed = true; 240 241 return genphy_c45_check_and_restart_aneg(phydev, changed); 242 } 243 244 static int aqr_config_intr(struct phy_device *phydev) 245 { 246 bool en = phydev->interrupts == PHY_INTERRUPT_ENABLED; 247 int err; 248 249 err = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_MASK2, 250 en ? MDIO_AN_TX_VEND_INT_MASK2_LINK : 0); 251 if (err < 0) 252 return err; 253 254 err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_STD_MASK, 255 en ? VEND1_GLOBAL_INT_STD_MASK_ALL : 0); 256 if (err < 0) 257 return err; 258 259 return phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_VEND_MASK, 260 en ? VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 | 261 VEND1_GLOBAL_INT_VEND_MASK_AN : 0); 262 } 263 264 static int aqr_ack_interrupt(struct phy_device *phydev) 265 { 266 int reg; 267 268 reg = phy_read_mmd(phydev, MDIO_MMD_AN, 269 MDIO_AN_TX_VEND_INT_STATUS2); 270 return (reg < 0) ? reg : 0; 271 } 272 273 static int aqr_read_status(struct phy_device *phydev) 274 { 275 int val; 276 277 if (phydev->autoneg == AUTONEG_ENABLE) { 278 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1); 279 if (val < 0) 280 return val; 281 282 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 283 phydev->lp_advertising, 284 val & MDIO_AN_RX_LP_STAT1_1000BASET_FULL); 285 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, 286 phydev->lp_advertising, 287 val & MDIO_AN_RX_LP_STAT1_1000BASET_HALF); 288 } 289 290 return genphy_c45_read_status(phydev); 291 } 292 293 static int aqr107_read_rate(struct phy_device *phydev) 294 { 295 int val; 296 297 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_STATUS1); 298 if (val < 0) 299 return val; 300 301 switch (FIELD_GET(MDIO_AN_TX_VEND_STATUS1_RATE_MASK, val)) { 302 case MDIO_AN_TX_VEND_STATUS1_10BASET: 303 phydev->speed = SPEED_10; 304 break; 305 case MDIO_AN_TX_VEND_STATUS1_100BASETX: 306 phydev->speed = SPEED_100; 307 break; 308 case MDIO_AN_TX_VEND_STATUS1_1000BASET: 309 phydev->speed = SPEED_1000; 310 break; 311 case MDIO_AN_TX_VEND_STATUS1_2500BASET: 312 phydev->speed = SPEED_2500; 313 break; 314 case MDIO_AN_TX_VEND_STATUS1_5000BASET: 315 phydev->speed = SPEED_5000; 316 break; 317 case MDIO_AN_TX_VEND_STATUS1_10GBASET: 318 phydev->speed = SPEED_10000; 319 break; 320 default: 321 phydev->speed = SPEED_UNKNOWN; 322 break; 323 } 324 325 if (val & MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX) 326 phydev->duplex = DUPLEX_FULL; 327 else 328 phydev->duplex = DUPLEX_HALF; 329 330 return 0; 331 } 332 333 static int aqr107_read_status(struct phy_device *phydev) 334 { 335 int val, ret; 336 337 ret = aqr_read_status(phydev); 338 if (ret) 339 return ret; 340 341 if (!phydev->link || phydev->autoneg == AUTONEG_DISABLE) 342 return 0; 343 344 val = phy_read_mmd(phydev, MDIO_MMD_PHYXS, MDIO_PHYXS_VEND_IF_STATUS); 345 if (val < 0) 346 return val; 347 348 switch (FIELD_GET(MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK, val)) { 349 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR: 350 phydev->interface = PHY_INTERFACE_MODE_10GKR; 351 break; 352 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI: 353 phydev->interface = PHY_INTERFACE_MODE_10GBASER; 354 break; 355 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII: 356 phydev->interface = PHY_INTERFACE_MODE_USXGMII; 357 break; 358 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII: 359 phydev->interface = PHY_INTERFACE_MODE_SGMII; 360 break; 361 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII: 362 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 363 break; 364 default: 365 phydev->interface = PHY_INTERFACE_MODE_NA; 366 break; 367 } 368 369 /* Read possibly downshifted rate from vendor register */ 370 return aqr107_read_rate(phydev); 371 } 372 373 static int aqr107_get_downshift(struct phy_device *phydev, u8 *data) 374 { 375 int val, cnt, enable; 376 377 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV); 378 if (val < 0) 379 return val; 380 381 enable = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_EN, val); 382 cnt = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val); 383 384 *data = enable && cnt ? cnt : DOWNSHIFT_DEV_DISABLE; 385 386 return 0; 387 } 388 389 static int aqr107_set_downshift(struct phy_device *phydev, u8 cnt) 390 { 391 int val = 0; 392 393 if (!FIELD_FIT(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt)) 394 return -E2BIG; 395 396 if (cnt != DOWNSHIFT_DEV_DISABLE) { 397 val = MDIO_AN_VEND_PROV_DOWNSHIFT_EN; 398 val |= FIELD_PREP(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt); 399 } 400 401 return phy_modify_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV, 402 MDIO_AN_VEND_PROV_DOWNSHIFT_EN | 403 MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val); 404 } 405 406 static int aqr107_get_tunable(struct phy_device *phydev, 407 struct ethtool_tunable *tuna, void *data) 408 { 409 switch (tuna->id) { 410 case ETHTOOL_PHY_DOWNSHIFT: 411 return aqr107_get_downshift(phydev, data); 412 default: 413 return -EOPNOTSUPP; 414 } 415 } 416 417 static int aqr107_set_tunable(struct phy_device *phydev, 418 struct ethtool_tunable *tuna, const void *data) 419 { 420 switch (tuna->id) { 421 case ETHTOOL_PHY_DOWNSHIFT: 422 return aqr107_set_downshift(phydev, *(const u8 *)data); 423 default: 424 return -EOPNOTSUPP; 425 } 426 } 427 428 /* If we configure settings whilst firmware is still initializing the chip, 429 * then these settings may be overwritten. Therefore make sure chip 430 * initialization has completed. Use presence of the firmware ID as 431 * indicator for initialization having completed. 432 * The chip also provides a "reset completed" bit, but it's cleared after 433 * read. Therefore function would time out if called again. 434 */ 435 static int aqr107_wait_reset_complete(struct phy_device *phydev) 436 { 437 int val; 438 439 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, 440 VEND1_GLOBAL_FW_ID, val, val != 0, 441 20000, 2000000, false); 442 } 443 444 static void aqr107_chip_info(struct phy_device *phydev) 445 { 446 u8 fw_major, fw_minor, build_id, prov_id; 447 int val; 448 449 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_FW_ID); 450 if (val < 0) 451 return; 452 453 fw_major = FIELD_GET(VEND1_GLOBAL_FW_ID_MAJOR, val); 454 fw_minor = FIELD_GET(VEND1_GLOBAL_FW_ID_MINOR, val); 455 456 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT1); 457 if (val < 0) 458 return; 459 460 build_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID, val); 461 prov_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_PROV_ID, val); 462 463 phydev_dbg(phydev, "FW %u.%u, Build %u, Provisioning %u\n", 464 fw_major, fw_minor, build_id, prov_id); 465 } 466 467 static int aqr107_config_init(struct phy_device *phydev) 468 { 469 int ret; 470 471 /* Check that the PHY interface type is compatible */ 472 if (phydev->interface != PHY_INTERFACE_MODE_SGMII && 473 phydev->interface != PHY_INTERFACE_MODE_2500BASEX && 474 phydev->interface != PHY_INTERFACE_MODE_XGMII && 475 phydev->interface != PHY_INTERFACE_MODE_USXGMII && 476 phydev->interface != PHY_INTERFACE_MODE_10GKR && 477 phydev->interface != PHY_INTERFACE_MODE_10GBASER) 478 return -ENODEV; 479 480 WARN(phydev->interface == PHY_INTERFACE_MODE_XGMII, 481 "Your devicetree is out of date, please update it. The AQR107 family doesn't support XGMII, maybe you mean USXGMII.\n"); 482 483 ret = aqr107_wait_reset_complete(phydev); 484 if (!ret) 485 aqr107_chip_info(phydev); 486 487 return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT); 488 } 489 490 static int aqcs109_config_init(struct phy_device *phydev) 491 { 492 int ret; 493 494 /* Check that the PHY interface type is compatible */ 495 if (phydev->interface != PHY_INTERFACE_MODE_SGMII && 496 phydev->interface != PHY_INTERFACE_MODE_2500BASEX) 497 return -ENODEV; 498 499 ret = aqr107_wait_reset_complete(phydev); 500 if (!ret) 501 aqr107_chip_info(phydev); 502 503 /* AQCS109 belongs to a chip family partially supporting 10G and 5G. 504 * PMA speed ability bits are the same for all members of the family, 505 * AQCS109 however supports speeds up to 2.5G only. 506 */ 507 ret = phy_set_max_speed(phydev, SPEED_2500); 508 if (ret) 509 return ret; 510 511 return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT); 512 } 513 514 static void aqr107_link_change_notify(struct phy_device *phydev) 515 { 516 u8 fw_major, fw_minor; 517 bool downshift, short_reach, afr; 518 int mode, val; 519 520 if (phydev->state != PHY_RUNNING || phydev->autoneg == AUTONEG_DISABLE) 521 return; 522 523 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1); 524 /* call failed or link partner is no Aquantia PHY */ 525 if (val < 0 || !(val & MDIO_AN_RX_LP_STAT1_AQ_PHY)) 526 return; 527 528 short_reach = val & MDIO_AN_RX_LP_STAT1_SHORT_REACH; 529 downshift = val & MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT; 530 531 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT4); 532 if (val < 0) 533 return; 534 535 fw_major = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MAJOR, val); 536 fw_minor = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MINOR, val); 537 538 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_VEND_STAT3); 539 if (val < 0) 540 return; 541 542 afr = val & MDIO_AN_RX_VEND_STAT3_AFR; 543 544 phydev_dbg(phydev, "Link partner is Aquantia PHY, FW %u.%u%s%s%s\n", 545 fw_major, fw_minor, 546 short_reach ? ", short reach mode" : "", 547 downshift ? ", fast-retrain downshift advertised" : "", 548 afr ? ", fast reframe advertised" : ""); 549 550 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT9); 551 if (val < 0) 552 return; 553 554 mode = FIELD_GET(VEND1_GLOBAL_RSVD_STAT9_MODE, val); 555 if (mode == VEND1_GLOBAL_RSVD_STAT9_1000BT2) 556 phydev_info(phydev, "Aquantia 1000Base-T2 mode active\n"); 557 } 558 559 static int aqr107_suspend(struct phy_device *phydev) 560 { 561 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1, 562 MDIO_CTRL1_LPOWER); 563 } 564 565 static int aqr107_resume(struct phy_device *phydev) 566 { 567 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1, 568 MDIO_CTRL1_LPOWER); 569 } 570 571 static int aqr107_probe(struct phy_device *phydev) 572 { 573 phydev->priv = devm_kzalloc(&phydev->mdio.dev, 574 sizeof(struct aqr107_priv), GFP_KERNEL); 575 if (!phydev->priv) 576 return -ENOMEM; 577 578 return aqr_hwmon_probe(phydev); 579 } 580 581 static struct phy_driver aqr_driver[] = { 582 { 583 PHY_ID_MATCH_MODEL(PHY_ID_AQ1202), 584 .name = "Aquantia AQ1202", 585 .config_aneg = aqr_config_aneg, 586 .config_intr = aqr_config_intr, 587 .ack_interrupt = aqr_ack_interrupt, 588 .read_status = aqr_read_status, 589 }, 590 { 591 PHY_ID_MATCH_MODEL(PHY_ID_AQ2104), 592 .name = "Aquantia AQ2104", 593 .config_aneg = aqr_config_aneg, 594 .config_intr = aqr_config_intr, 595 .ack_interrupt = aqr_ack_interrupt, 596 .read_status = aqr_read_status, 597 }, 598 { 599 PHY_ID_MATCH_MODEL(PHY_ID_AQR105), 600 .name = "Aquantia AQR105", 601 .config_aneg = aqr_config_aneg, 602 .config_intr = aqr_config_intr, 603 .ack_interrupt = aqr_ack_interrupt, 604 .read_status = aqr_read_status, 605 .suspend = aqr107_suspend, 606 .resume = aqr107_resume, 607 }, 608 { 609 PHY_ID_MATCH_MODEL(PHY_ID_AQR106), 610 .name = "Aquantia AQR106", 611 .config_aneg = aqr_config_aneg, 612 .config_intr = aqr_config_intr, 613 .ack_interrupt = aqr_ack_interrupt, 614 .read_status = aqr_read_status, 615 }, 616 { 617 PHY_ID_MATCH_MODEL(PHY_ID_AQR107), 618 .name = "Aquantia AQR107", 619 .probe = aqr107_probe, 620 .config_init = aqr107_config_init, 621 .config_aneg = aqr_config_aneg, 622 .config_intr = aqr_config_intr, 623 .ack_interrupt = aqr_ack_interrupt, 624 .read_status = aqr107_read_status, 625 .get_tunable = aqr107_get_tunable, 626 .set_tunable = aqr107_set_tunable, 627 .suspend = aqr107_suspend, 628 .resume = aqr107_resume, 629 .get_sset_count = aqr107_get_sset_count, 630 .get_strings = aqr107_get_strings, 631 .get_stats = aqr107_get_stats, 632 .link_change_notify = aqr107_link_change_notify, 633 }, 634 { 635 PHY_ID_MATCH_MODEL(PHY_ID_AQCS109), 636 .name = "Aquantia AQCS109", 637 .probe = aqr107_probe, 638 .config_init = aqcs109_config_init, 639 .config_aneg = aqr_config_aneg, 640 .config_intr = aqr_config_intr, 641 .ack_interrupt = aqr_ack_interrupt, 642 .read_status = aqr107_read_status, 643 .get_tunable = aqr107_get_tunable, 644 .set_tunable = aqr107_set_tunable, 645 .suspend = aqr107_suspend, 646 .resume = aqr107_resume, 647 .get_sset_count = aqr107_get_sset_count, 648 .get_strings = aqr107_get_strings, 649 .get_stats = aqr107_get_stats, 650 .link_change_notify = aqr107_link_change_notify, 651 }, 652 { 653 PHY_ID_MATCH_MODEL(PHY_ID_AQR405), 654 .name = "Aquantia AQR405", 655 .config_aneg = aqr_config_aneg, 656 .config_intr = aqr_config_intr, 657 .ack_interrupt = aqr_ack_interrupt, 658 .read_status = aqr_read_status, 659 }, 660 }; 661 662 module_phy_driver(aqr_driver); 663 664 static struct mdio_device_id __maybe_unused aqr_tbl[] = { 665 { PHY_ID_MATCH_MODEL(PHY_ID_AQ1202) }, 666 { PHY_ID_MATCH_MODEL(PHY_ID_AQ2104) }, 667 { PHY_ID_MATCH_MODEL(PHY_ID_AQR105) }, 668 { PHY_ID_MATCH_MODEL(PHY_ID_AQR106) }, 669 { PHY_ID_MATCH_MODEL(PHY_ID_AQR107) }, 670 { PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) }, 671 { PHY_ID_MATCH_MODEL(PHY_ID_AQR405) }, 672 { } 673 }; 674 675 MODULE_DEVICE_TABLE(mdio, aqr_tbl); 676 677 MODULE_DESCRIPTION("Aquantia PHY driver"); 678 MODULE_AUTHOR("Shaohui Xie <Shaohui.Xie@freescale.com>"); 679 MODULE_LICENSE("GPL v2"); 680