1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for Aquantia PHY 4 * 5 * Author: Shaohui Xie <Shaohui.Xie@freescale.com> 6 * 7 * Copyright 2015 Freescale Semiconductor, Inc. 8 */ 9 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/delay.h> 13 #include <linux/bitfield.h> 14 #include <linux/phy.h> 15 16 #include "aquantia.h" 17 18 #define PHY_ID_AQ1202 0x03a1b445 19 #define PHY_ID_AQ2104 0x03a1b460 20 #define PHY_ID_AQR105 0x03a1b4a2 21 #define PHY_ID_AQR106 0x03a1b4d0 22 #define PHY_ID_AQR107 0x03a1b4e0 23 #define PHY_ID_AQCS109 0x03a1b5c2 24 #define PHY_ID_AQR405 0x03a1b4b0 25 #define PHY_ID_AQR113C 0x31c31c12 26 27 #define MDIO_PHYXS_VEND_IF_STATUS 0xe812 28 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK GENMASK(7, 3) 29 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR 0 30 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI 2 31 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII 3 32 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII 6 33 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII 10 34 35 #define MDIO_AN_VEND_PROV 0xc400 36 #define MDIO_AN_VEND_PROV_1000BASET_FULL BIT(15) 37 #define MDIO_AN_VEND_PROV_1000BASET_HALF BIT(14) 38 #define MDIO_AN_VEND_PROV_5000BASET_FULL BIT(11) 39 #define MDIO_AN_VEND_PROV_2500BASET_FULL BIT(10) 40 #define MDIO_AN_VEND_PROV_DOWNSHIFT_EN BIT(4) 41 #define MDIO_AN_VEND_PROV_DOWNSHIFT_MASK GENMASK(3, 0) 42 #define MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT 4 43 44 #define MDIO_AN_TX_VEND_STATUS1 0xc800 45 #define MDIO_AN_TX_VEND_STATUS1_RATE_MASK GENMASK(3, 1) 46 #define MDIO_AN_TX_VEND_STATUS1_10BASET 0 47 #define MDIO_AN_TX_VEND_STATUS1_100BASETX 1 48 #define MDIO_AN_TX_VEND_STATUS1_1000BASET 2 49 #define MDIO_AN_TX_VEND_STATUS1_10GBASET 3 50 #define MDIO_AN_TX_VEND_STATUS1_2500BASET 4 51 #define MDIO_AN_TX_VEND_STATUS1_5000BASET 5 52 #define MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX BIT(0) 53 54 #define MDIO_AN_TX_VEND_INT_STATUS1 0xcc00 55 #define MDIO_AN_TX_VEND_INT_STATUS1_DOWNSHIFT BIT(1) 56 57 #define MDIO_AN_TX_VEND_INT_STATUS2 0xcc01 58 #define MDIO_AN_TX_VEND_INT_STATUS2_MASK BIT(0) 59 60 #define MDIO_AN_TX_VEND_INT_MASK2 0xd401 61 #define MDIO_AN_TX_VEND_INT_MASK2_LINK BIT(0) 62 63 #define MDIO_AN_RX_LP_STAT1 0xe820 64 #define MDIO_AN_RX_LP_STAT1_1000BASET_FULL BIT(15) 65 #define MDIO_AN_RX_LP_STAT1_1000BASET_HALF BIT(14) 66 #define MDIO_AN_RX_LP_STAT1_SHORT_REACH BIT(13) 67 #define MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT BIT(12) 68 #define MDIO_AN_RX_LP_STAT1_AQ_PHY BIT(2) 69 70 #define MDIO_AN_RX_LP_STAT4 0xe823 71 #define MDIO_AN_RX_LP_STAT4_FW_MAJOR GENMASK(15, 8) 72 #define MDIO_AN_RX_LP_STAT4_FW_MINOR GENMASK(7, 0) 73 74 #define MDIO_AN_RX_VEND_STAT3 0xe832 75 #define MDIO_AN_RX_VEND_STAT3_AFR BIT(0) 76 77 /* MDIO_MMD_C22EXT */ 78 #define MDIO_C22EXT_STAT_SGMII_RX_GOOD_FRAMES 0xd292 79 #define MDIO_C22EXT_STAT_SGMII_RX_BAD_FRAMES 0xd294 80 #define MDIO_C22EXT_STAT_SGMII_RX_FALSE_CARRIER 0xd297 81 #define MDIO_C22EXT_STAT_SGMII_TX_GOOD_FRAMES 0xd313 82 #define MDIO_C22EXT_STAT_SGMII_TX_BAD_FRAMES 0xd315 83 #define MDIO_C22EXT_STAT_SGMII_TX_FALSE_CARRIER 0xd317 84 #define MDIO_C22EXT_STAT_SGMII_TX_COLLISIONS 0xd318 85 #define MDIO_C22EXT_STAT_SGMII_TX_LINE_COLLISIONS 0xd319 86 #define MDIO_C22EXT_STAT_SGMII_TX_FRAME_ALIGN_ERR 0xd31a 87 #define MDIO_C22EXT_STAT_SGMII_TX_RUNT_FRAMES 0xd31b 88 89 /* Vendor specific 1, MDIO_MMD_VEND1 */ 90 #define VEND1_GLOBAL_FW_ID 0x0020 91 #define VEND1_GLOBAL_FW_ID_MAJOR GENMASK(15, 8) 92 #define VEND1_GLOBAL_FW_ID_MINOR GENMASK(7, 0) 93 94 #define VEND1_GLOBAL_RSVD_STAT1 0xc885 95 #define VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID GENMASK(7, 4) 96 #define VEND1_GLOBAL_RSVD_STAT1_PROV_ID GENMASK(3, 0) 97 98 #define VEND1_GLOBAL_RSVD_STAT9 0xc88d 99 #define VEND1_GLOBAL_RSVD_STAT9_MODE GENMASK(7, 0) 100 #define VEND1_GLOBAL_RSVD_STAT9_1000BT2 0x23 101 102 #define VEND1_GLOBAL_INT_STD_STATUS 0xfc00 103 #define VEND1_GLOBAL_INT_VEND_STATUS 0xfc01 104 105 #define VEND1_GLOBAL_INT_STD_MASK 0xff00 106 #define VEND1_GLOBAL_INT_STD_MASK_PMA1 BIT(15) 107 #define VEND1_GLOBAL_INT_STD_MASK_PMA2 BIT(14) 108 #define VEND1_GLOBAL_INT_STD_MASK_PCS1 BIT(13) 109 #define VEND1_GLOBAL_INT_STD_MASK_PCS2 BIT(12) 110 #define VEND1_GLOBAL_INT_STD_MASK_PCS3 BIT(11) 111 #define VEND1_GLOBAL_INT_STD_MASK_PHY_XS1 BIT(10) 112 #define VEND1_GLOBAL_INT_STD_MASK_PHY_XS2 BIT(9) 113 #define VEND1_GLOBAL_INT_STD_MASK_AN1 BIT(8) 114 #define VEND1_GLOBAL_INT_STD_MASK_AN2 BIT(7) 115 #define VEND1_GLOBAL_INT_STD_MASK_GBE BIT(6) 116 #define VEND1_GLOBAL_INT_STD_MASK_ALL BIT(0) 117 118 #define VEND1_GLOBAL_INT_VEND_MASK 0xff01 119 #define VEND1_GLOBAL_INT_VEND_MASK_PMA BIT(15) 120 #define VEND1_GLOBAL_INT_VEND_MASK_PCS BIT(14) 121 #define VEND1_GLOBAL_INT_VEND_MASK_PHY_XS BIT(13) 122 #define VEND1_GLOBAL_INT_VEND_MASK_AN BIT(12) 123 #define VEND1_GLOBAL_INT_VEND_MASK_GBE BIT(11) 124 #define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL1 BIT(2) 125 #define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL2 BIT(1) 126 #define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 BIT(0) 127 128 struct aqr107_hw_stat { 129 const char *name; 130 int reg; 131 int size; 132 }; 133 134 #define SGMII_STAT(n, r, s) { n, MDIO_C22EXT_STAT_SGMII_ ## r, s } 135 static const struct aqr107_hw_stat aqr107_hw_stats[] = { 136 SGMII_STAT("sgmii_rx_good_frames", RX_GOOD_FRAMES, 26), 137 SGMII_STAT("sgmii_rx_bad_frames", RX_BAD_FRAMES, 26), 138 SGMII_STAT("sgmii_rx_false_carrier_events", RX_FALSE_CARRIER, 8), 139 SGMII_STAT("sgmii_tx_good_frames", TX_GOOD_FRAMES, 26), 140 SGMII_STAT("sgmii_tx_bad_frames", TX_BAD_FRAMES, 26), 141 SGMII_STAT("sgmii_tx_false_carrier_events", TX_FALSE_CARRIER, 8), 142 SGMII_STAT("sgmii_tx_collisions", TX_COLLISIONS, 8), 143 SGMII_STAT("sgmii_tx_line_collisions", TX_LINE_COLLISIONS, 8), 144 SGMII_STAT("sgmii_tx_frame_alignment_err", TX_FRAME_ALIGN_ERR, 16), 145 SGMII_STAT("sgmii_tx_runt_frames", TX_RUNT_FRAMES, 22), 146 }; 147 #define AQR107_SGMII_STAT_SZ ARRAY_SIZE(aqr107_hw_stats) 148 149 struct aqr107_priv { 150 u64 sgmii_stats[AQR107_SGMII_STAT_SZ]; 151 }; 152 153 static int aqr107_get_sset_count(struct phy_device *phydev) 154 { 155 return AQR107_SGMII_STAT_SZ; 156 } 157 158 static void aqr107_get_strings(struct phy_device *phydev, u8 *data) 159 { 160 int i; 161 162 for (i = 0; i < AQR107_SGMII_STAT_SZ; i++) 163 strscpy(data + i * ETH_GSTRING_LEN, aqr107_hw_stats[i].name, 164 ETH_GSTRING_LEN); 165 } 166 167 static u64 aqr107_get_stat(struct phy_device *phydev, int index) 168 { 169 const struct aqr107_hw_stat *stat = aqr107_hw_stats + index; 170 int len_l = min(stat->size, 16); 171 int len_h = stat->size - len_l; 172 u64 ret; 173 int val; 174 175 val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg); 176 if (val < 0) 177 return U64_MAX; 178 179 ret = val & GENMASK(len_l - 1, 0); 180 if (len_h) { 181 val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg + 1); 182 if (val < 0) 183 return U64_MAX; 184 185 ret += (val & GENMASK(len_h - 1, 0)) << 16; 186 } 187 188 return ret; 189 } 190 191 static void aqr107_get_stats(struct phy_device *phydev, 192 struct ethtool_stats *stats, u64 *data) 193 { 194 struct aqr107_priv *priv = phydev->priv; 195 u64 val; 196 int i; 197 198 for (i = 0; i < AQR107_SGMII_STAT_SZ; i++) { 199 val = aqr107_get_stat(phydev, i); 200 if (val == U64_MAX) 201 phydev_err(phydev, "Reading HW Statistics failed for %s\n", 202 aqr107_hw_stats[i].name); 203 else 204 priv->sgmii_stats[i] += val; 205 206 data[i] = priv->sgmii_stats[i]; 207 } 208 } 209 210 static int aqr_config_aneg(struct phy_device *phydev) 211 { 212 bool changed = false; 213 u16 reg; 214 int ret; 215 216 if (phydev->autoneg == AUTONEG_DISABLE) 217 return genphy_c45_pma_setup_forced(phydev); 218 219 ret = genphy_c45_an_config_aneg(phydev); 220 if (ret < 0) 221 return ret; 222 if (ret > 0) 223 changed = true; 224 225 /* Clause 45 has no standardized support for 1000BaseT, therefore 226 * use vendor registers for this mode. 227 */ 228 reg = 0; 229 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 230 phydev->advertising)) 231 reg |= MDIO_AN_VEND_PROV_1000BASET_FULL; 232 233 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, 234 phydev->advertising)) 235 reg |= MDIO_AN_VEND_PROV_1000BASET_HALF; 236 237 /* Handle the case when the 2.5G and 5G speeds are not advertised */ 238 if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 239 phydev->advertising)) 240 reg |= MDIO_AN_VEND_PROV_2500BASET_FULL; 241 242 if (linkmode_test_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 243 phydev->advertising)) 244 reg |= MDIO_AN_VEND_PROV_5000BASET_FULL; 245 246 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV, 247 MDIO_AN_VEND_PROV_1000BASET_HALF | 248 MDIO_AN_VEND_PROV_1000BASET_FULL | 249 MDIO_AN_VEND_PROV_2500BASET_FULL | 250 MDIO_AN_VEND_PROV_5000BASET_FULL, reg); 251 if (ret < 0) 252 return ret; 253 if (ret > 0) 254 changed = true; 255 256 return genphy_c45_check_and_restart_aneg(phydev, changed); 257 } 258 259 static int aqr_config_intr(struct phy_device *phydev) 260 { 261 bool en = phydev->interrupts == PHY_INTERRUPT_ENABLED; 262 int err; 263 264 if (en) { 265 /* Clear any pending interrupts before enabling them */ 266 err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2); 267 if (err < 0) 268 return err; 269 } 270 271 err = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_MASK2, 272 en ? MDIO_AN_TX_VEND_INT_MASK2_LINK : 0); 273 if (err < 0) 274 return err; 275 276 err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_STD_MASK, 277 en ? VEND1_GLOBAL_INT_STD_MASK_ALL : 0); 278 if (err < 0) 279 return err; 280 281 err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_VEND_MASK, 282 en ? VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 | 283 VEND1_GLOBAL_INT_VEND_MASK_AN : 0); 284 if (err < 0) 285 return err; 286 287 if (!en) { 288 /* Clear any pending interrupts after we have disabled them */ 289 err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2); 290 if (err < 0) 291 return err; 292 } 293 294 return 0; 295 } 296 297 static irqreturn_t aqr_handle_interrupt(struct phy_device *phydev) 298 { 299 int irq_status; 300 301 irq_status = phy_read_mmd(phydev, MDIO_MMD_AN, 302 MDIO_AN_TX_VEND_INT_STATUS2); 303 if (irq_status < 0) { 304 phy_error(phydev); 305 return IRQ_NONE; 306 } 307 308 if (!(irq_status & MDIO_AN_TX_VEND_INT_STATUS2_MASK)) 309 return IRQ_NONE; 310 311 phy_trigger_machine(phydev); 312 313 return IRQ_HANDLED; 314 } 315 316 static int aqr_read_status(struct phy_device *phydev) 317 { 318 int val; 319 320 if (phydev->autoneg == AUTONEG_ENABLE) { 321 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1); 322 if (val < 0) 323 return val; 324 325 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 326 phydev->lp_advertising, 327 val & MDIO_AN_RX_LP_STAT1_1000BASET_FULL); 328 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, 329 phydev->lp_advertising, 330 val & MDIO_AN_RX_LP_STAT1_1000BASET_HALF); 331 } 332 333 return genphy_c45_read_status(phydev); 334 } 335 336 static int aqr107_read_rate(struct phy_device *phydev) 337 { 338 int val; 339 340 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_STATUS1); 341 if (val < 0) 342 return val; 343 344 switch (FIELD_GET(MDIO_AN_TX_VEND_STATUS1_RATE_MASK, val)) { 345 case MDIO_AN_TX_VEND_STATUS1_10BASET: 346 phydev->speed = SPEED_10; 347 break; 348 case MDIO_AN_TX_VEND_STATUS1_100BASETX: 349 phydev->speed = SPEED_100; 350 break; 351 case MDIO_AN_TX_VEND_STATUS1_1000BASET: 352 phydev->speed = SPEED_1000; 353 break; 354 case MDIO_AN_TX_VEND_STATUS1_2500BASET: 355 phydev->speed = SPEED_2500; 356 break; 357 case MDIO_AN_TX_VEND_STATUS1_5000BASET: 358 phydev->speed = SPEED_5000; 359 break; 360 case MDIO_AN_TX_VEND_STATUS1_10GBASET: 361 phydev->speed = SPEED_10000; 362 break; 363 default: 364 phydev->speed = SPEED_UNKNOWN; 365 break; 366 } 367 368 if (val & MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX) 369 phydev->duplex = DUPLEX_FULL; 370 else 371 phydev->duplex = DUPLEX_HALF; 372 373 return 0; 374 } 375 376 static int aqr107_read_status(struct phy_device *phydev) 377 { 378 int val, ret; 379 380 ret = aqr_read_status(phydev); 381 if (ret) 382 return ret; 383 384 if (!phydev->link || phydev->autoneg == AUTONEG_DISABLE) 385 return 0; 386 387 val = phy_read_mmd(phydev, MDIO_MMD_PHYXS, MDIO_PHYXS_VEND_IF_STATUS); 388 if (val < 0) 389 return val; 390 391 switch (FIELD_GET(MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK, val)) { 392 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR: 393 phydev->interface = PHY_INTERFACE_MODE_10GKR; 394 break; 395 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI: 396 phydev->interface = PHY_INTERFACE_MODE_10GBASER; 397 break; 398 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII: 399 phydev->interface = PHY_INTERFACE_MODE_USXGMII; 400 break; 401 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII: 402 phydev->interface = PHY_INTERFACE_MODE_SGMII; 403 break; 404 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII: 405 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 406 break; 407 default: 408 phydev->interface = PHY_INTERFACE_MODE_NA; 409 break; 410 } 411 412 /* Read possibly downshifted rate from vendor register */ 413 return aqr107_read_rate(phydev); 414 } 415 416 static int aqr107_get_downshift(struct phy_device *phydev, u8 *data) 417 { 418 int val, cnt, enable; 419 420 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV); 421 if (val < 0) 422 return val; 423 424 enable = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_EN, val); 425 cnt = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val); 426 427 *data = enable && cnt ? cnt : DOWNSHIFT_DEV_DISABLE; 428 429 return 0; 430 } 431 432 static int aqr107_set_downshift(struct phy_device *phydev, u8 cnt) 433 { 434 int val = 0; 435 436 if (!FIELD_FIT(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt)) 437 return -E2BIG; 438 439 if (cnt != DOWNSHIFT_DEV_DISABLE) { 440 val = MDIO_AN_VEND_PROV_DOWNSHIFT_EN; 441 val |= FIELD_PREP(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt); 442 } 443 444 return phy_modify_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV, 445 MDIO_AN_VEND_PROV_DOWNSHIFT_EN | 446 MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val); 447 } 448 449 static int aqr107_get_tunable(struct phy_device *phydev, 450 struct ethtool_tunable *tuna, void *data) 451 { 452 switch (tuna->id) { 453 case ETHTOOL_PHY_DOWNSHIFT: 454 return aqr107_get_downshift(phydev, data); 455 default: 456 return -EOPNOTSUPP; 457 } 458 } 459 460 static int aqr107_set_tunable(struct phy_device *phydev, 461 struct ethtool_tunable *tuna, const void *data) 462 { 463 switch (tuna->id) { 464 case ETHTOOL_PHY_DOWNSHIFT: 465 return aqr107_set_downshift(phydev, *(const u8 *)data); 466 default: 467 return -EOPNOTSUPP; 468 } 469 } 470 471 /* If we configure settings whilst firmware is still initializing the chip, 472 * then these settings may be overwritten. Therefore make sure chip 473 * initialization has completed. Use presence of the firmware ID as 474 * indicator for initialization having completed. 475 * The chip also provides a "reset completed" bit, but it's cleared after 476 * read. Therefore function would time out if called again. 477 */ 478 static int aqr107_wait_reset_complete(struct phy_device *phydev) 479 { 480 int val; 481 482 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, 483 VEND1_GLOBAL_FW_ID, val, val != 0, 484 20000, 2000000, false); 485 } 486 487 static void aqr107_chip_info(struct phy_device *phydev) 488 { 489 u8 fw_major, fw_minor, build_id, prov_id; 490 int val; 491 492 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_FW_ID); 493 if (val < 0) 494 return; 495 496 fw_major = FIELD_GET(VEND1_GLOBAL_FW_ID_MAJOR, val); 497 fw_minor = FIELD_GET(VEND1_GLOBAL_FW_ID_MINOR, val); 498 499 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT1); 500 if (val < 0) 501 return; 502 503 build_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID, val); 504 prov_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_PROV_ID, val); 505 506 phydev_dbg(phydev, "FW %u.%u, Build %u, Provisioning %u\n", 507 fw_major, fw_minor, build_id, prov_id); 508 } 509 510 static int aqr107_config_init(struct phy_device *phydev) 511 { 512 int ret; 513 514 /* Check that the PHY interface type is compatible */ 515 if (phydev->interface != PHY_INTERFACE_MODE_SGMII && 516 phydev->interface != PHY_INTERFACE_MODE_2500BASEX && 517 phydev->interface != PHY_INTERFACE_MODE_XGMII && 518 phydev->interface != PHY_INTERFACE_MODE_USXGMII && 519 phydev->interface != PHY_INTERFACE_MODE_10GKR && 520 phydev->interface != PHY_INTERFACE_MODE_10GBASER) 521 return -ENODEV; 522 523 WARN(phydev->interface == PHY_INTERFACE_MODE_XGMII, 524 "Your devicetree is out of date, please update it. The AQR107 family doesn't support XGMII, maybe you mean USXGMII.\n"); 525 526 ret = aqr107_wait_reset_complete(phydev); 527 if (!ret) 528 aqr107_chip_info(phydev); 529 530 return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT); 531 } 532 533 static int aqcs109_config_init(struct phy_device *phydev) 534 { 535 int ret; 536 537 /* Check that the PHY interface type is compatible */ 538 if (phydev->interface != PHY_INTERFACE_MODE_SGMII && 539 phydev->interface != PHY_INTERFACE_MODE_2500BASEX) 540 return -ENODEV; 541 542 ret = aqr107_wait_reset_complete(phydev); 543 if (!ret) 544 aqr107_chip_info(phydev); 545 546 /* AQCS109 belongs to a chip family partially supporting 10G and 5G. 547 * PMA speed ability bits are the same for all members of the family, 548 * AQCS109 however supports speeds up to 2.5G only. 549 */ 550 phy_set_max_speed(phydev, SPEED_2500); 551 552 return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT); 553 } 554 555 static void aqr107_link_change_notify(struct phy_device *phydev) 556 { 557 u8 fw_major, fw_minor; 558 bool downshift, short_reach, afr; 559 int mode, val; 560 561 if (phydev->state != PHY_RUNNING || phydev->autoneg == AUTONEG_DISABLE) 562 return; 563 564 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1); 565 /* call failed or link partner is no Aquantia PHY */ 566 if (val < 0 || !(val & MDIO_AN_RX_LP_STAT1_AQ_PHY)) 567 return; 568 569 short_reach = val & MDIO_AN_RX_LP_STAT1_SHORT_REACH; 570 downshift = val & MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT; 571 572 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT4); 573 if (val < 0) 574 return; 575 576 fw_major = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MAJOR, val); 577 fw_minor = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MINOR, val); 578 579 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_VEND_STAT3); 580 if (val < 0) 581 return; 582 583 afr = val & MDIO_AN_RX_VEND_STAT3_AFR; 584 585 phydev_dbg(phydev, "Link partner is Aquantia PHY, FW %u.%u%s%s%s\n", 586 fw_major, fw_minor, 587 short_reach ? ", short reach mode" : "", 588 downshift ? ", fast-retrain downshift advertised" : "", 589 afr ? ", fast reframe advertised" : ""); 590 591 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT9); 592 if (val < 0) 593 return; 594 595 mode = FIELD_GET(VEND1_GLOBAL_RSVD_STAT9_MODE, val); 596 if (mode == VEND1_GLOBAL_RSVD_STAT9_1000BT2) 597 phydev_info(phydev, "Aquantia 1000Base-T2 mode active\n"); 598 } 599 600 static int aqr107_suspend(struct phy_device *phydev) 601 { 602 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1, 603 MDIO_CTRL1_LPOWER); 604 } 605 606 static int aqr107_resume(struct phy_device *phydev) 607 { 608 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1, 609 MDIO_CTRL1_LPOWER); 610 } 611 612 static int aqr107_probe(struct phy_device *phydev) 613 { 614 phydev->priv = devm_kzalloc(&phydev->mdio.dev, 615 sizeof(struct aqr107_priv), GFP_KERNEL); 616 if (!phydev->priv) 617 return -ENOMEM; 618 619 return aqr_hwmon_probe(phydev); 620 } 621 622 static struct phy_driver aqr_driver[] = { 623 { 624 PHY_ID_MATCH_MODEL(PHY_ID_AQ1202), 625 .name = "Aquantia AQ1202", 626 .config_aneg = aqr_config_aneg, 627 .config_intr = aqr_config_intr, 628 .handle_interrupt = aqr_handle_interrupt, 629 .read_status = aqr_read_status, 630 }, 631 { 632 PHY_ID_MATCH_MODEL(PHY_ID_AQ2104), 633 .name = "Aquantia AQ2104", 634 .config_aneg = aqr_config_aneg, 635 .config_intr = aqr_config_intr, 636 .handle_interrupt = aqr_handle_interrupt, 637 .read_status = aqr_read_status, 638 }, 639 { 640 PHY_ID_MATCH_MODEL(PHY_ID_AQR105), 641 .name = "Aquantia AQR105", 642 .config_aneg = aqr_config_aneg, 643 .config_intr = aqr_config_intr, 644 .handle_interrupt = aqr_handle_interrupt, 645 .read_status = aqr_read_status, 646 .suspend = aqr107_suspend, 647 .resume = aqr107_resume, 648 }, 649 { 650 PHY_ID_MATCH_MODEL(PHY_ID_AQR106), 651 .name = "Aquantia AQR106", 652 .config_aneg = aqr_config_aneg, 653 .config_intr = aqr_config_intr, 654 .handle_interrupt = aqr_handle_interrupt, 655 .read_status = aqr_read_status, 656 }, 657 { 658 PHY_ID_MATCH_MODEL(PHY_ID_AQR107), 659 .name = "Aquantia AQR107", 660 .probe = aqr107_probe, 661 .config_init = aqr107_config_init, 662 .config_aneg = aqr_config_aneg, 663 .config_intr = aqr_config_intr, 664 .handle_interrupt = aqr_handle_interrupt, 665 .read_status = aqr107_read_status, 666 .get_tunable = aqr107_get_tunable, 667 .set_tunable = aqr107_set_tunable, 668 .suspend = aqr107_suspend, 669 .resume = aqr107_resume, 670 .get_sset_count = aqr107_get_sset_count, 671 .get_strings = aqr107_get_strings, 672 .get_stats = aqr107_get_stats, 673 .link_change_notify = aqr107_link_change_notify, 674 }, 675 { 676 PHY_ID_MATCH_MODEL(PHY_ID_AQCS109), 677 .name = "Aquantia AQCS109", 678 .probe = aqr107_probe, 679 .config_init = aqcs109_config_init, 680 .config_aneg = aqr_config_aneg, 681 .config_intr = aqr_config_intr, 682 .handle_interrupt = aqr_handle_interrupt, 683 .read_status = aqr107_read_status, 684 .get_tunable = aqr107_get_tunable, 685 .set_tunable = aqr107_set_tunable, 686 .suspend = aqr107_suspend, 687 .resume = aqr107_resume, 688 .get_sset_count = aqr107_get_sset_count, 689 .get_strings = aqr107_get_strings, 690 .get_stats = aqr107_get_stats, 691 .link_change_notify = aqr107_link_change_notify, 692 }, 693 { 694 PHY_ID_MATCH_MODEL(PHY_ID_AQR405), 695 .name = "Aquantia AQR405", 696 .config_aneg = aqr_config_aneg, 697 .config_intr = aqr_config_intr, 698 .handle_interrupt = aqr_handle_interrupt, 699 .read_status = aqr_read_status, 700 }, 701 { 702 PHY_ID_MATCH_MODEL(PHY_ID_AQR113C), 703 .name = "Aquantia AQR113C", 704 .probe = aqr107_probe, 705 .config_init = aqr107_config_init, 706 .config_aneg = aqr_config_aneg, 707 .config_intr = aqr_config_intr, 708 .handle_interrupt = aqr_handle_interrupt, 709 .read_status = aqr107_read_status, 710 .get_tunable = aqr107_get_tunable, 711 .set_tunable = aqr107_set_tunable, 712 .suspend = aqr107_suspend, 713 .resume = aqr107_resume, 714 .get_sset_count = aqr107_get_sset_count, 715 .get_strings = aqr107_get_strings, 716 .get_stats = aqr107_get_stats, 717 .link_change_notify = aqr107_link_change_notify, 718 }, 719 }; 720 721 module_phy_driver(aqr_driver); 722 723 static struct mdio_device_id __maybe_unused aqr_tbl[] = { 724 { PHY_ID_MATCH_MODEL(PHY_ID_AQ1202) }, 725 { PHY_ID_MATCH_MODEL(PHY_ID_AQ2104) }, 726 { PHY_ID_MATCH_MODEL(PHY_ID_AQR105) }, 727 { PHY_ID_MATCH_MODEL(PHY_ID_AQR106) }, 728 { PHY_ID_MATCH_MODEL(PHY_ID_AQR107) }, 729 { PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) }, 730 { PHY_ID_MATCH_MODEL(PHY_ID_AQR405) }, 731 { PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) }, 732 { } 733 }; 734 735 MODULE_DEVICE_TABLE(mdio, aqr_tbl); 736 737 MODULE_DESCRIPTION("Aquantia PHY driver"); 738 MODULE_AUTHOR("Shaohui Xie <Shaohui.Xie@freescale.com>"); 739 MODULE_LICENSE("GPL v2"); 740