1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for Aquantia PHY 4 * 5 * Author: Shaohui Xie <Shaohui.Xie@freescale.com> 6 * 7 * Copyright 2015 Freescale Semiconductor, Inc. 8 */ 9 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/delay.h> 13 #include <linux/bitfield.h> 14 #include <linux/phy.h> 15 16 #include "aquantia.h" 17 18 #define PHY_ID_AQ1202 0x03a1b445 19 #define PHY_ID_AQ2104 0x03a1b460 20 #define PHY_ID_AQR105 0x03a1b4a2 21 #define PHY_ID_AQR106 0x03a1b4d0 22 #define PHY_ID_AQR107 0x03a1b4e0 23 #define PHY_ID_AQCS109 0x03a1b5c2 24 #define PHY_ID_AQR405 0x03a1b4b0 25 #define PHY_ID_AQR113C 0x31c31c12 26 27 #define MDIO_PHYXS_VEND_IF_STATUS 0xe812 28 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK GENMASK(7, 3) 29 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR 0 30 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI 2 31 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII 3 32 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII 6 33 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII 10 34 35 #define MDIO_AN_VEND_PROV 0xc400 36 #define MDIO_AN_VEND_PROV_1000BASET_FULL BIT(15) 37 #define MDIO_AN_VEND_PROV_1000BASET_HALF BIT(14) 38 #define MDIO_AN_VEND_PROV_5000BASET_FULL BIT(11) 39 #define MDIO_AN_VEND_PROV_2500BASET_FULL BIT(10) 40 #define MDIO_AN_VEND_PROV_DOWNSHIFT_EN BIT(4) 41 #define MDIO_AN_VEND_PROV_DOWNSHIFT_MASK GENMASK(3, 0) 42 #define MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT 4 43 44 #define MDIO_AN_TX_VEND_STATUS1 0xc800 45 #define MDIO_AN_TX_VEND_STATUS1_RATE_MASK GENMASK(3, 1) 46 #define MDIO_AN_TX_VEND_STATUS1_10BASET 0 47 #define MDIO_AN_TX_VEND_STATUS1_100BASETX 1 48 #define MDIO_AN_TX_VEND_STATUS1_1000BASET 2 49 #define MDIO_AN_TX_VEND_STATUS1_10GBASET 3 50 #define MDIO_AN_TX_VEND_STATUS1_2500BASET 4 51 #define MDIO_AN_TX_VEND_STATUS1_5000BASET 5 52 #define MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX BIT(0) 53 54 #define MDIO_AN_TX_VEND_INT_STATUS1 0xcc00 55 #define MDIO_AN_TX_VEND_INT_STATUS1_DOWNSHIFT BIT(1) 56 57 #define MDIO_AN_TX_VEND_INT_STATUS2 0xcc01 58 #define MDIO_AN_TX_VEND_INT_STATUS2_MASK BIT(0) 59 60 #define MDIO_AN_TX_VEND_INT_MASK2 0xd401 61 #define MDIO_AN_TX_VEND_INT_MASK2_LINK BIT(0) 62 63 #define MDIO_AN_RX_LP_STAT1 0xe820 64 #define MDIO_AN_RX_LP_STAT1_1000BASET_FULL BIT(15) 65 #define MDIO_AN_RX_LP_STAT1_1000BASET_HALF BIT(14) 66 #define MDIO_AN_RX_LP_STAT1_SHORT_REACH BIT(13) 67 #define MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT BIT(12) 68 #define MDIO_AN_RX_LP_STAT1_AQ_PHY BIT(2) 69 70 #define MDIO_AN_RX_LP_STAT4 0xe823 71 #define MDIO_AN_RX_LP_STAT4_FW_MAJOR GENMASK(15, 8) 72 #define MDIO_AN_RX_LP_STAT4_FW_MINOR GENMASK(7, 0) 73 74 #define MDIO_AN_RX_VEND_STAT3 0xe832 75 #define MDIO_AN_RX_VEND_STAT3_AFR BIT(0) 76 77 /* MDIO_MMD_C22EXT */ 78 #define MDIO_C22EXT_STAT_SGMII_RX_GOOD_FRAMES 0xd292 79 #define MDIO_C22EXT_STAT_SGMII_RX_BAD_FRAMES 0xd294 80 #define MDIO_C22EXT_STAT_SGMII_RX_FALSE_CARRIER 0xd297 81 #define MDIO_C22EXT_STAT_SGMII_TX_GOOD_FRAMES 0xd313 82 #define MDIO_C22EXT_STAT_SGMII_TX_BAD_FRAMES 0xd315 83 #define MDIO_C22EXT_STAT_SGMII_TX_FALSE_CARRIER 0xd317 84 #define MDIO_C22EXT_STAT_SGMII_TX_COLLISIONS 0xd318 85 #define MDIO_C22EXT_STAT_SGMII_TX_LINE_COLLISIONS 0xd319 86 #define MDIO_C22EXT_STAT_SGMII_TX_FRAME_ALIGN_ERR 0xd31a 87 #define MDIO_C22EXT_STAT_SGMII_TX_RUNT_FRAMES 0xd31b 88 89 /* Vendor specific 1, MDIO_MMD_VEND1 */ 90 #define VEND1_GLOBAL_FW_ID 0x0020 91 #define VEND1_GLOBAL_FW_ID_MAJOR GENMASK(15, 8) 92 #define VEND1_GLOBAL_FW_ID_MINOR GENMASK(7, 0) 93 94 #define VEND1_GLOBAL_GEN_STAT2 0xc831 95 #define VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG BIT(15) 96 97 #define VEND1_GLOBAL_RSVD_STAT1 0xc885 98 #define VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID GENMASK(7, 4) 99 #define VEND1_GLOBAL_RSVD_STAT1_PROV_ID GENMASK(3, 0) 100 101 #define VEND1_GLOBAL_RSVD_STAT9 0xc88d 102 #define VEND1_GLOBAL_RSVD_STAT9_MODE GENMASK(7, 0) 103 #define VEND1_GLOBAL_RSVD_STAT9_1000BT2 0x23 104 105 #define VEND1_GLOBAL_INT_STD_STATUS 0xfc00 106 #define VEND1_GLOBAL_INT_VEND_STATUS 0xfc01 107 108 #define VEND1_GLOBAL_INT_STD_MASK 0xff00 109 #define VEND1_GLOBAL_INT_STD_MASK_PMA1 BIT(15) 110 #define VEND1_GLOBAL_INT_STD_MASK_PMA2 BIT(14) 111 #define VEND1_GLOBAL_INT_STD_MASK_PCS1 BIT(13) 112 #define VEND1_GLOBAL_INT_STD_MASK_PCS2 BIT(12) 113 #define VEND1_GLOBAL_INT_STD_MASK_PCS3 BIT(11) 114 #define VEND1_GLOBAL_INT_STD_MASK_PHY_XS1 BIT(10) 115 #define VEND1_GLOBAL_INT_STD_MASK_PHY_XS2 BIT(9) 116 #define VEND1_GLOBAL_INT_STD_MASK_AN1 BIT(8) 117 #define VEND1_GLOBAL_INT_STD_MASK_AN2 BIT(7) 118 #define VEND1_GLOBAL_INT_STD_MASK_GBE BIT(6) 119 #define VEND1_GLOBAL_INT_STD_MASK_ALL BIT(0) 120 121 #define VEND1_GLOBAL_INT_VEND_MASK 0xff01 122 #define VEND1_GLOBAL_INT_VEND_MASK_PMA BIT(15) 123 #define VEND1_GLOBAL_INT_VEND_MASK_PCS BIT(14) 124 #define VEND1_GLOBAL_INT_VEND_MASK_PHY_XS BIT(13) 125 #define VEND1_GLOBAL_INT_VEND_MASK_AN BIT(12) 126 #define VEND1_GLOBAL_INT_VEND_MASK_GBE BIT(11) 127 #define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL1 BIT(2) 128 #define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL2 BIT(1) 129 #define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 BIT(0) 130 131 /* Sleep and timeout for checking if the Processor-Intensive 132 * MDIO operation is finished 133 */ 134 #define AQR107_OP_IN_PROG_SLEEP 1000 135 #define AQR107_OP_IN_PROG_TIMEOUT 100000 136 137 struct aqr107_hw_stat { 138 const char *name; 139 int reg; 140 int size; 141 }; 142 143 #define SGMII_STAT(n, r, s) { n, MDIO_C22EXT_STAT_SGMII_ ## r, s } 144 static const struct aqr107_hw_stat aqr107_hw_stats[] = { 145 SGMII_STAT("sgmii_rx_good_frames", RX_GOOD_FRAMES, 26), 146 SGMII_STAT("sgmii_rx_bad_frames", RX_BAD_FRAMES, 26), 147 SGMII_STAT("sgmii_rx_false_carrier_events", RX_FALSE_CARRIER, 8), 148 SGMII_STAT("sgmii_tx_good_frames", TX_GOOD_FRAMES, 26), 149 SGMII_STAT("sgmii_tx_bad_frames", TX_BAD_FRAMES, 26), 150 SGMII_STAT("sgmii_tx_false_carrier_events", TX_FALSE_CARRIER, 8), 151 SGMII_STAT("sgmii_tx_collisions", TX_COLLISIONS, 8), 152 SGMII_STAT("sgmii_tx_line_collisions", TX_LINE_COLLISIONS, 8), 153 SGMII_STAT("sgmii_tx_frame_alignment_err", TX_FRAME_ALIGN_ERR, 16), 154 SGMII_STAT("sgmii_tx_runt_frames", TX_RUNT_FRAMES, 22), 155 }; 156 #define AQR107_SGMII_STAT_SZ ARRAY_SIZE(aqr107_hw_stats) 157 158 struct aqr107_priv { 159 u64 sgmii_stats[AQR107_SGMII_STAT_SZ]; 160 }; 161 162 static int aqr107_get_sset_count(struct phy_device *phydev) 163 { 164 return AQR107_SGMII_STAT_SZ; 165 } 166 167 static void aqr107_get_strings(struct phy_device *phydev, u8 *data) 168 { 169 int i; 170 171 for (i = 0; i < AQR107_SGMII_STAT_SZ; i++) 172 strscpy(data + i * ETH_GSTRING_LEN, aqr107_hw_stats[i].name, 173 ETH_GSTRING_LEN); 174 } 175 176 static u64 aqr107_get_stat(struct phy_device *phydev, int index) 177 { 178 const struct aqr107_hw_stat *stat = aqr107_hw_stats + index; 179 int len_l = min(stat->size, 16); 180 int len_h = stat->size - len_l; 181 u64 ret; 182 int val; 183 184 val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg); 185 if (val < 0) 186 return U64_MAX; 187 188 ret = val & GENMASK(len_l - 1, 0); 189 if (len_h) { 190 val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg + 1); 191 if (val < 0) 192 return U64_MAX; 193 194 ret += (val & GENMASK(len_h - 1, 0)) << 16; 195 } 196 197 return ret; 198 } 199 200 static void aqr107_get_stats(struct phy_device *phydev, 201 struct ethtool_stats *stats, u64 *data) 202 { 203 struct aqr107_priv *priv = phydev->priv; 204 u64 val; 205 int i; 206 207 for (i = 0; i < AQR107_SGMII_STAT_SZ; i++) { 208 val = aqr107_get_stat(phydev, i); 209 if (val == U64_MAX) 210 phydev_err(phydev, "Reading HW Statistics failed for %s\n", 211 aqr107_hw_stats[i].name); 212 else 213 priv->sgmii_stats[i] += val; 214 215 data[i] = priv->sgmii_stats[i]; 216 } 217 } 218 219 static int aqr_config_aneg(struct phy_device *phydev) 220 { 221 bool changed = false; 222 u16 reg; 223 int ret; 224 225 if (phydev->autoneg == AUTONEG_DISABLE) 226 return genphy_c45_pma_setup_forced(phydev); 227 228 ret = genphy_c45_an_config_aneg(phydev); 229 if (ret < 0) 230 return ret; 231 if (ret > 0) 232 changed = true; 233 234 /* Clause 45 has no standardized support for 1000BaseT, therefore 235 * use vendor registers for this mode. 236 */ 237 reg = 0; 238 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 239 phydev->advertising)) 240 reg |= MDIO_AN_VEND_PROV_1000BASET_FULL; 241 242 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, 243 phydev->advertising)) 244 reg |= MDIO_AN_VEND_PROV_1000BASET_HALF; 245 246 /* Handle the case when the 2.5G and 5G speeds are not advertised */ 247 if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 248 phydev->advertising)) 249 reg |= MDIO_AN_VEND_PROV_2500BASET_FULL; 250 251 if (linkmode_test_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 252 phydev->advertising)) 253 reg |= MDIO_AN_VEND_PROV_5000BASET_FULL; 254 255 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV, 256 MDIO_AN_VEND_PROV_1000BASET_HALF | 257 MDIO_AN_VEND_PROV_1000BASET_FULL | 258 MDIO_AN_VEND_PROV_2500BASET_FULL | 259 MDIO_AN_VEND_PROV_5000BASET_FULL, reg); 260 if (ret < 0) 261 return ret; 262 if (ret > 0) 263 changed = true; 264 265 return genphy_c45_check_and_restart_aneg(phydev, changed); 266 } 267 268 static int aqr_config_intr(struct phy_device *phydev) 269 { 270 bool en = phydev->interrupts == PHY_INTERRUPT_ENABLED; 271 int err; 272 273 if (en) { 274 /* Clear any pending interrupts before enabling them */ 275 err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2); 276 if (err < 0) 277 return err; 278 } 279 280 err = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_MASK2, 281 en ? MDIO_AN_TX_VEND_INT_MASK2_LINK : 0); 282 if (err < 0) 283 return err; 284 285 err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_STD_MASK, 286 en ? VEND1_GLOBAL_INT_STD_MASK_ALL : 0); 287 if (err < 0) 288 return err; 289 290 err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_VEND_MASK, 291 en ? VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 | 292 VEND1_GLOBAL_INT_VEND_MASK_AN : 0); 293 if (err < 0) 294 return err; 295 296 if (!en) { 297 /* Clear any pending interrupts after we have disabled them */ 298 err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2); 299 if (err < 0) 300 return err; 301 } 302 303 return 0; 304 } 305 306 static irqreturn_t aqr_handle_interrupt(struct phy_device *phydev) 307 { 308 int irq_status; 309 310 irq_status = phy_read_mmd(phydev, MDIO_MMD_AN, 311 MDIO_AN_TX_VEND_INT_STATUS2); 312 if (irq_status < 0) { 313 phy_error(phydev); 314 return IRQ_NONE; 315 } 316 317 if (!(irq_status & MDIO_AN_TX_VEND_INT_STATUS2_MASK)) 318 return IRQ_NONE; 319 320 phy_trigger_machine(phydev); 321 322 return IRQ_HANDLED; 323 } 324 325 static int aqr_read_status(struct phy_device *phydev) 326 { 327 int val; 328 329 if (phydev->autoneg == AUTONEG_ENABLE) { 330 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1); 331 if (val < 0) 332 return val; 333 334 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 335 phydev->lp_advertising, 336 val & MDIO_AN_RX_LP_STAT1_1000BASET_FULL); 337 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, 338 phydev->lp_advertising, 339 val & MDIO_AN_RX_LP_STAT1_1000BASET_HALF); 340 } 341 342 return genphy_c45_read_status(phydev); 343 } 344 345 static int aqr107_read_rate(struct phy_device *phydev) 346 { 347 int val; 348 349 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_STATUS1); 350 if (val < 0) 351 return val; 352 353 switch (FIELD_GET(MDIO_AN_TX_VEND_STATUS1_RATE_MASK, val)) { 354 case MDIO_AN_TX_VEND_STATUS1_10BASET: 355 phydev->speed = SPEED_10; 356 break; 357 case MDIO_AN_TX_VEND_STATUS1_100BASETX: 358 phydev->speed = SPEED_100; 359 break; 360 case MDIO_AN_TX_VEND_STATUS1_1000BASET: 361 phydev->speed = SPEED_1000; 362 break; 363 case MDIO_AN_TX_VEND_STATUS1_2500BASET: 364 phydev->speed = SPEED_2500; 365 break; 366 case MDIO_AN_TX_VEND_STATUS1_5000BASET: 367 phydev->speed = SPEED_5000; 368 break; 369 case MDIO_AN_TX_VEND_STATUS1_10GBASET: 370 phydev->speed = SPEED_10000; 371 break; 372 default: 373 phydev->speed = SPEED_UNKNOWN; 374 break; 375 } 376 377 if (val & MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX) 378 phydev->duplex = DUPLEX_FULL; 379 else 380 phydev->duplex = DUPLEX_HALF; 381 382 return 0; 383 } 384 385 static int aqr107_read_status(struct phy_device *phydev) 386 { 387 int val, ret; 388 389 ret = aqr_read_status(phydev); 390 if (ret) 391 return ret; 392 393 if (!phydev->link || phydev->autoneg == AUTONEG_DISABLE) 394 return 0; 395 396 val = phy_read_mmd(phydev, MDIO_MMD_PHYXS, MDIO_PHYXS_VEND_IF_STATUS); 397 if (val < 0) 398 return val; 399 400 switch (FIELD_GET(MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK, val)) { 401 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR: 402 phydev->interface = PHY_INTERFACE_MODE_10GKR; 403 break; 404 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI: 405 phydev->interface = PHY_INTERFACE_MODE_10GBASER; 406 break; 407 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII: 408 phydev->interface = PHY_INTERFACE_MODE_USXGMII; 409 break; 410 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII: 411 phydev->interface = PHY_INTERFACE_MODE_SGMII; 412 break; 413 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII: 414 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 415 break; 416 default: 417 phydev->interface = PHY_INTERFACE_MODE_NA; 418 break; 419 } 420 421 /* Read possibly downshifted rate from vendor register */ 422 return aqr107_read_rate(phydev); 423 } 424 425 static int aqr107_get_downshift(struct phy_device *phydev, u8 *data) 426 { 427 int val, cnt, enable; 428 429 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV); 430 if (val < 0) 431 return val; 432 433 enable = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_EN, val); 434 cnt = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val); 435 436 *data = enable && cnt ? cnt : DOWNSHIFT_DEV_DISABLE; 437 438 return 0; 439 } 440 441 static int aqr107_set_downshift(struct phy_device *phydev, u8 cnt) 442 { 443 int val = 0; 444 445 if (!FIELD_FIT(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt)) 446 return -E2BIG; 447 448 if (cnt != DOWNSHIFT_DEV_DISABLE) { 449 val = MDIO_AN_VEND_PROV_DOWNSHIFT_EN; 450 val |= FIELD_PREP(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt); 451 } 452 453 return phy_modify_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV, 454 MDIO_AN_VEND_PROV_DOWNSHIFT_EN | 455 MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val); 456 } 457 458 static int aqr107_get_tunable(struct phy_device *phydev, 459 struct ethtool_tunable *tuna, void *data) 460 { 461 switch (tuna->id) { 462 case ETHTOOL_PHY_DOWNSHIFT: 463 return aqr107_get_downshift(phydev, data); 464 default: 465 return -EOPNOTSUPP; 466 } 467 } 468 469 static int aqr107_set_tunable(struct phy_device *phydev, 470 struct ethtool_tunable *tuna, const void *data) 471 { 472 switch (tuna->id) { 473 case ETHTOOL_PHY_DOWNSHIFT: 474 return aqr107_set_downshift(phydev, *(const u8 *)data); 475 default: 476 return -EOPNOTSUPP; 477 } 478 } 479 480 /* If we configure settings whilst firmware is still initializing the chip, 481 * then these settings may be overwritten. Therefore make sure chip 482 * initialization has completed. Use presence of the firmware ID as 483 * indicator for initialization having completed. 484 * The chip also provides a "reset completed" bit, but it's cleared after 485 * read. Therefore function would time out if called again. 486 */ 487 static int aqr107_wait_reset_complete(struct phy_device *phydev) 488 { 489 int val; 490 491 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, 492 VEND1_GLOBAL_FW_ID, val, val != 0, 493 20000, 2000000, false); 494 } 495 496 static void aqr107_chip_info(struct phy_device *phydev) 497 { 498 u8 fw_major, fw_minor, build_id, prov_id; 499 int val; 500 501 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_FW_ID); 502 if (val < 0) 503 return; 504 505 fw_major = FIELD_GET(VEND1_GLOBAL_FW_ID_MAJOR, val); 506 fw_minor = FIELD_GET(VEND1_GLOBAL_FW_ID_MINOR, val); 507 508 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT1); 509 if (val < 0) 510 return; 511 512 build_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID, val); 513 prov_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_PROV_ID, val); 514 515 phydev_dbg(phydev, "FW %u.%u, Build %u, Provisioning %u\n", 516 fw_major, fw_minor, build_id, prov_id); 517 } 518 519 static int aqr107_config_init(struct phy_device *phydev) 520 { 521 int ret; 522 523 /* Check that the PHY interface type is compatible */ 524 if (phydev->interface != PHY_INTERFACE_MODE_SGMII && 525 phydev->interface != PHY_INTERFACE_MODE_2500BASEX && 526 phydev->interface != PHY_INTERFACE_MODE_XGMII && 527 phydev->interface != PHY_INTERFACE_MODE_USXGMII && 528 phydev->interface != PHY_INTERFACE_MODE_10GKR && 529 phydev->interface != PHY_INTERFACE_MODE_10GBASER) 530 return -ENODEV; 531 532 WARN(phydev->interface == PHY_INTERFACE_MODE_XGMII, 533 "Your devicetree is out of date, please update it. The AQR107 family doesn't support XGMII, maybe you mean USXGMII.\n"); 534 535 ret = aqr107_wait_reset_complete(phydev); 536 if (!ret) 537 aqr107_chip_info(phydev); 538 539 return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT); 540 } 541 542 static int aqcs109_config_init(struct phy_device *phydev) 543 { 544 int ret; 545 546 /* Check that the PHY interface type is compatible */ 547 if (phydev->interface != PHY_INTERFACE_MODE_SGMII && 548 phydev->interface != PHY_INTERFACE_MODE_2500BASEX) 549 return -ENODEV; 550 551 ret = aqr107_wait_reset_complete(phydev); 552 if (!ret) 553 aqr107_chip_info(phydev); 554 555 /* AQCS109 belongs to a chip family partially supporting 10G and 5G. 556 * PMA speed ability bits are the same for all members of the family, 557 * AQCS109 however supports speeds up to 2.5G only. 558 */ 559 phy_set_max_speed(phydev, SPEED_2500); 560 561 return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT); 562 } 563 564 static void aqr107_link_change_notify(struct phy_device *phydev) 565 { 566 u8 fw_major, fw_minor; 567 bool downshift, short_reach, afr; 568 int mode, val; 569 570 if (phydev->state != PHY_RUNNING || phydev->autoneg == AUTONEG_DISABLE) 571 return; 572 573 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1); 574 /* call failed or link partner is no Aquantia PHY */ 575 if (val < 0 || !(val & MDIO_AN_RX_LP_STAT1_AQ_PHY)) 576 return; 577 578 short_reach = val & MDIO_AN_RX_LP_STAT1_SHORT_REACH; 579 downshift = val & MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT; 580 581 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT4); 582 if (val < 0) 583 return; 584 585 fw_major = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MAJOR, val); 586 fw_minor = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MINOR, val); 587 588 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_VEND_STAT3); 589 if (val < 0) 590 return; 591 592 afr = val & MDIO_AN_RX_VEND_STAT3_AFR; 593 594 phydev_dbg(phydev, "Link partner is Aquantia PHY, FW %u.%u%s%s%s\n", 595 fw_major, fw_minor, 596 short_reach ? ", short reach mode" : "", 597 downshift ? ", fast-retrain downshift advertised" : "", 598 afr ? ", fast reframe advertised" : ""); 599 600 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT9); 601 if (val < 0) 602 return; 603 604 mode = FIELD_GET(VEND1_GLOBAL_RSVD_STAT9_MODE, val); 605 if (mode == VEND1_GLOBAL_RSVD_STAT9_1000BT2) 606 phydev_info(phydev, "Aquantia 1000Base-T2 mode active\n"); 607 } 608 609 static int aqr107_wait_processor_intensive_op(struct phy_device *phydev) 610 { 611 int val, err; 612 613 /* The datasheet notes to wait at least 1ms after issuing a 614 * processor intensive operation before checking. 615 * We cannot use the 'sleep_before_read' parameter of read_poll_timeout 616 * because that just determines the maximum time slept, not the minimum. 617 */ 618 usleep_range(1000, 5000); 619 620 err = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, 621 VEND1_GLOBAL_GEN_STAT2, val, 622 !(val & VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG), 623 AQR107_OP_IN_PROG_SLEEP, 624 AQR107_OP_IN_PROG_TIMEOUT, false); 625 if (err) { 626 phydev_err(phydev, "timeout: processor-intensive MDIO operation\n"); 627 return err; 628 } 629 630 return 0; 631 } 632 633 static int aqr107_suspend(struct phy_device *phydev) 634 { 635 int err; 636 637 err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1, 638 MDIO_CTRL1_LPOWER); 639 if (err) 640 return err; 641 642 return aqr107_wait_processor_intensive_op(phydev); 643 } 644 645 static int aqr107_resume(struct phy_device *phydev) 646 { 647 int err; 648 649 err = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1, 650 MDIO_CTRL1_LPOWER); 651 if (err) 652 return err; 653 654 return aqr107_wait_processor_intensive_op(phydev); 655 } 656 657 static int aqr107_probe(struct phy_device *phydev) 658 { 659 phydev->priv = devm_kzalloc(&phydev->mdio.dev, 660 sizeof(struct aqr107_priv), GFP_KERNEL); 661 if (!phydev->priv) 662 return -ENOMEM; 663 664 return aqr_hwmon_probe(phydev); 665 } 666 667 static struct phy_driver aqr_driver[] = { 668 { 669 PHY_ID_MATCH_MODEL(PHY_ID_AQ1202), 670 .name = "Aquantia AQ1202", 671 .config_aneg = aqr_config_aneg, 672 .config_intr = aqr_config_intr, 673 .handle_interrupt = aqr_handle_interrupt, 674 .read_status = aqr_read_status, 675 }, 676 { 677 PHY_ID_MATCH_MODEL(PHY_ID_AQ2104), 678 .name = "Aquantia AQ2104", 679 .config_aneg = aqr_config_aneg, 680 .config_intr = aqr_config_intr, 681 .handle_interrupt = aqr_handle_interrupt, 682 .read_status = aqr_read_status, 683 }, 684 { 685 PHY_ID_MATCH_MODEL(PHY_ID_AQR105), 686 .name = "Aquantia AQR105", 687 .config_aneg = aqr_config_aneg, 688 .config_intr = aqr_config_intr, 689 .handle_interrupt = aqr_handle_interrupt, 690 .read_status = aqr_read_status, 691 .suspend = aqr107_suspend, 692 .resume = aqr107_resume, 693 }, 694 { 695 PHY_ID_MATCH_MODEL(PHY_ID_AQR106), 696 .name = "Aquantia AQR106", 697 .config_aneg = aqr_config_aneg, 698 .config_intr = aqr_config_intr, 699 .handle_interrupt = aqr_handle_interrupt, 700 .read_status = aqr_read_status, 701 }, 702 { 703 PHY_ID_MATCH_MODEL(PHY_ID_AQR107), 704 .name = "Aquantia AQR107", 705 .probe = aqr107_probe, 706 .config_init = aqr107_config_init, 707 .config_aneg = aqr_config_aneg, 708 .config_intr = aqr_config_intr, 709 .handle_interrupt = aqr_handle_interrupt, 710 .read_status = aqr107_read_status, 711 .get_tunable = aqr107_get_tunable, 712 .set_tunable = aqr107_set_tunable, 713 .suspend = aqr107_suspend, 714 .resume = aqr107_resume, 715 .get_sset_count = aqr107_get_sset_count, 716 .get_strings = aqr107_get_strings, 717 .get_stats = aqr107_get_stats, 718 .link_change_notify = aqr107_link_change_notify, 719 }, 720 { 721 PHY_ID_MATCH_MODEL(PHY_ID_AQCS109), 722 .name = "Aquantia AQCS109", 723 .probe = aqr107_probe, 724 .config_init = aqcs109_config_init, 725 .config_aneg = aqr_config_aneg, 726 .config_intr = aqr_config_intr, 727 .handle_interrupt = aqr_handle_interrupt, 728 .read_status = aqr107_read_status, 729 .get_tunable = aqr107_get_tunable, 730 .set_tunable = aqr107_set_tunable, 731 .suspend = aqr107_suspend, 732 .resume = aqr107_resume, 733 .get_sset_count = aqr107_get_sset_count, 734 .get_strings = aqr107_get_strings, 735 .get_stats = aqr107_get_stats, 736 .link_change_notify = aqr107_link_change_notify, 737 }, 738 { 739 PHY_ID_MATCH_MODEL(PHY_ID_AQR405), 740 .name = "Aquantia AQR405", 741 .config_aneg = aqr_config_aneg, 742 .config_intr = aqr_config_intr, 743 .handle_interrupt = aqr_handle_interrupt, 744 .read_status = aqr_read_status, 745 }, 746 { 747 PHY_ID_MATCH_MODEL(PHY_ID_AQR113C), 748 .name = "Aquantia AQR113C", 749 .probe = aqr107_probe, 750 .config_init = aqr107_config_init, 751 .config_aneg = aqr_config_aneg, 752 .config_intr = aqr_config_intr, 753 .handle_interrupt = aqr_handle_interrupt, 754 .read_status = aqr107_read_status, 755 .get_tunable = aqr107_get_tunable, 756 .set_tunable = aqr107_set_tunable, 757 .suspend = aqr107_suspend, 758 .resume = aqr107_resume, 759 .get_sset_count = aqr107_get_sset_count, 760 .get_strings = aqr107_get_strings, 761 .get_stats = aqr107_get_stats, 762 .link_change_notify = aqr107_link_change_notify, 763 }, 764 }; 765 766 module_phy_driver(aqr_driver); 767 768 static struct mdio_device_id __maybe_unused aqr_tbl[] = { 769 { PHY_ID_MATCH_MODEL(PHY_ID_AQ1202) }, 770 { PHY_ID_MATCH_MODEL(PHY_ID_AQ2104) }, 771 { PHY_ID_MATCH_MODEL(PHY_ID_AQR105) }, 772 { PHY_ID_MATCH_MODEL(PHY_ID_AQR106) }, 773 { PHY_ID_MATCH_MODEL(PHY_ID_AQR107) }, 774 { PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) }, 775 { PHY_ID_MATCH_MODEL(PHY_ID_AQR405) }, 776 { PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) }, 777 { } 778 }; 779 780 MODULE_DEVICE_TABLE(mdio, aqr_tbl); 781 782 MODULE_DESCRIPTION("Aquantia PHY driver"); 783 MODULE_AUTHOR("Shaohui Xie <Shaohui.Xie@freescale.com>"); 784 MODULE_LICENSE("GPL v2"); 785