1 // SPDX-License-Identifier: GPL-2.0+ 2 /** 3 * Driver for Analog Devices Industrial Ethernet PHYs 4 * 5 * Copyright 2019 Analog Devices Inc. 6 */ 7 #include <linux/kernel.h> 8 #include <linux/bitfield.h> 9 #include <linux/delay.h> 10 #include <linux/errno.h> 11 #include <linux/init.h> 12 #include <linux/module.h> 13 #include <linux/mii.h> 14 #include <linux/phy.h> 15 #include <linux/property.h> 16 17 #define PHY_ID_ADIN1200 0x0283bc20 18 #define PHY_ID_ADIN1300 0x0283bc30 19 20 #define ADIN1300_MII_EXT_REG_PTR 0x0010 21 #define ADIN1300_MII_EXT_REG_DATA 0x0011 22 23 #define ADIN1300_PHY_CTRL1 0x0012 24 #define ADIN1300_AUTO_MDI_EN BIT(10) 25 #define ADIN1300_MAN_MDIX_EN BIT(9) 26 27 #define ADIN1300_INT_MASK_REG 0x0018 28 #define ADIN1300_INT_MDIO_SYNC_EN BIT(9) 29 #define ADIN1300_INT_ANEG_STAT_CHNG_EN BIT(8) 30 #define ADIN1300_INT_ANEG_PAGE_RX_EN BIT(6) 31 #define ADIN1300_INT_IDLE_ERR_CNT_EN BIT(5) 32 #define ADIN1300_INT_MAC_FIFO_OU_EN BIT(4) 33 #define ADIN1300_INT_RX_STAT_CHNG_EN BIT(3) 34 #define ADIN1300_INT_LINK_STAT_CHNG_EN BIT(2) 35 #define ADIN1300_INT_SPEED_CHNG_EN BIT(1) 36 #define ADIN1300_INT_HW_IRQ_EN BIT(0) 37 #define ADIN1300_INT_MASK_EN \ 38 (ADIN1300_INT_LINK_STAT_CHNG_EN | ADIN1300_INT_HW_IRQ_EN) 39 #define ADIN1300_INT_STATUS_REG 0x0019 40 41 #define ADIN1300_PHY_STATUS1 0x001a 42 #define ADIN1300_PAIR_01_SWAP BIT(11) 43 44 /* EEE register addresses, accessible via Clause 22 access using 45 * ADIN1300_MII_EXT_REG_PTR & ADIN1300_MII_EXT_REG_DATA. 46 * The bit-fields are the same as specified by IEEE for EEE. 47 */ 48 #define ADIN1300_EEE_CAP_REG 0x8000 49 #define ADIN1300_EEE_ADV_REG 0x8001 50 #define ADIN1300_EEE_LPABLE_REG 0x8002 51 #define ADIN1300_CLOCK_STOP_REG 0x9400 52 #define ADIN1300_LPI_WAKE_ERR_CNT_REG 0xa000 53 54 #define ADIN1300_GE_SOFT_RESET_REG 0xff0c 55 #define ADIN1300_GE_SOFT_RESET BIT(0) 56 57 #define ADIN1300_GE_RGMII_CFG_REG 0xff23 58 #define ADIN1300_GE_RGMII_RX_MSK GENMASK(8, 6) 59 #define ADIN1300_GE_RGMII_RX_SEL(x) \ 60 FIELD_PREP(ADIN1300_GE_RGMII_RX_MSK, x) 61 #define ADIN1300_GE_RGMII_GTX_MSK GENMASK(5, 3) 62 #define ADIN1300_GE_RGMII_GTX_SEL(x) \ 63 FIELD_PREP(ADIN1300_GE_RGMII_GTX_MSK, x) 64 #define ADIN1300_GE_RGMII_RXID_EN BIT(2) 65 #define ADIN1300_GE_RGMII_TXID_EN BIT(1) 66 #define ADIN1300_GE_RGMII_EN BIT(0) 67 68 /* RGMII internal delay settings for rx and tx for ADIN1300 */ 69 #define ADIN1300_RGMII_1_60_NS 0x0001 70 #define ADIN1300_RGMII_1_80_NS 0x0002 71 #define ADIN1300_RGMII_2_00_NS 0x0000 72 #define ADIN1300_RGMII_2_20_NS 0x0006 73 #define ADIN1300_RGMII_2_40_NS 0x0007 74 75 #define ADIN1300_GE_RMII_CFG_REG 0xff24 76 #define ADIN1300_GE_RMII_FIFO_DEPTH_MSK GENMASK(6, 4) 77 #define ADIN1300_GE_RMII_FIFO_DEPTH_SEL(x) \ 78 FIELD_PREP(ADIN1300_GE_RMII_FIFO_DEPTH_MSK, x) 79 #define ADIN1300_GE_RMII_EN BIT(0) 80 81 /* RMII fifo depth values */ 82 #define ADIN1300_RMII_4_BITS 0x0000 83 #define ADIN1300_RMII_8_BITS 0x0001 84 #define ADIN1300_RMII_12_BITS 0x0002 85 #define ADIN1300_RMII_16_BITS 0x0003 86 #define ADIN1300_RMII_20_BITS 0x0004 87 #define ADIN1300_RMII_24_BITS 0x0005 88 89 /** 90 * struct adin_cfg_reg_map - map a config value to aregister value 91 * @cfg value in device configuration 92 * @reg value in the register 93 */ 94 struct adin_cfg_reg_map { 95 int cfg; 96 int reg; 97 }; 98 99 static const struct adin_cfg_reg_map adin_rgmii_delays[] = { 100 { 1600, ADIN1300_RGMII_1_60_NS }, 101 { 1800, ADIN1300_RGMII_1_80_NS }, 102 { 2000, ADIN1300_RGMII_2_00_NS }, 103 { 2200, ADIN1300_RGMII_2_20_NS }, 104 { 2400, ADIN1300_RGMII_2_40_NS }, 105 { }, 106 }; 107 108 static const struct adin_cfg_reg_map adin_rmii_fifo_depths[] = { 109 { 4, ADIN1300_RMII_4_BITS }, 110 { 8, ADIN1300_RMII_8_BITS }, 111 { 12, ADIN1300_RMII_12_BITS }, 112 { 16, ADIN1300_RMII_16_BITS }, 113 { 20, ADIN1300_RMII_20_BITS }, 114 { 24, ADIN1300_RMII_24_BITS }, 115 { }, 116 }; 117 118 /** 119 * struct adin_clause45_mmd_map - map to convert Clause 45 regs to Clause 22 120 * @devad device address used in Clause 45 access 121 * @cl45_regnum register address defined by Clause 45 122 * @adin_regnum equivalent register address accessible via Clause 22 123 */ 124 struct adin_clause45_mmd_map { 125 int devad; 126 u16 cl45_regnum; 127 u16 adin_regnum; 128 }; 129 130 static struct adin_clause45_mmd_map adin_clause45_mmd_map[] = { 131 { MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE, ADIN1300_EEE_CAP_REG }, 132 { MDIO_MMD_AN, MDIO_AN_EEE_LPABLE, ADIN1300_EEE_LPABLE_REG }, 133 { MDIO_MMD_AN, MDIO_AN_EEE_ADV, ADIN1300_EEE_ADV_REG }, 134 { MDIO_MMD_PCS, MDIO_CTRL1, ADIN1300_CLOCK_STOP_REG }, 135 { MDIO_MMD_PCS, MDIO_PCS_EEE_WK_ERR, ADIN1300_LPI_WAKE_ERR_CNT_REG }, 136 }; 137 138 static int adin_lookup_reg_value(const struct adin_cfg_reg_map *tbl, int cfg) 139 { 140 size_t i; 141 142 for (i = 0; tbl[i].cfg; i++) { 143 if (tbl[i].cfg == cfg) 144 return tbl[i].reg; 145 } 146 147 return -EINVAL; 148 } 149 150 static u32 adin_get_reg_value(struct phy_device *phydev, 151 const char *prop_name, 152 const struct adin_cfg_reg_map *tbl, 153 u32 dflt) 154 { 155 struct device *dev = &phydev->mdio.dev; 156 u32 val; 157 int rc; 158 159 if (device_property_read_u32(dev, prop_name, &val)) 160 return dflt; 161 162 rc = adin_lookup_reg_value(tbl, val); 163 if (rc < 0) { 164 phydev_warn(phydev, 165 "Unsupported value %u for %s using default (%u)\n", 166 val, prop_name, dflt); 167 return dflt; 168 } 169 170 return rc; 171 } 172 173 static int adin_config_rgmii_mode(struct phy_device *phydev) 174 { 175 u32 val; 176 int reg; 177 178 if (!phy_interface_is_rgmii(phydev)) 179 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 180 ADIN1300_GE_RGMII_CFG_REG, 181 ADIN1300_GE_RGMII_EN); 182 183 reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_GE_RGMII_CFG_REG); 184 if (reg < 0) 185 return reg; 186 187 reg |= ADIN1300_GE_RGMII_EN; 188 189 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 190 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) { 191 reg |= ADIN1300_GE_RGMII_RXID_EN; 192 193 val = adin_get_reg_value(phydev, "adi,rx-internal-delay-ps", 194 adin_rgmii_delays, 195 ADIN1300_RGMII_2_00_NS); 196 reg &= ~ADIN1300_GE_RGMII_RX_MSK; 197 reg |= ADIN1300_GE_RGMII_RX_SEL(val); 198 } else { 199 reg &= ~ADIN1300_GE_RGMII_RXID_EN; 200 } 201 202 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 203 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) { 204 reg |= ADIN1300_GE_RGMII_TXID_EN; 205 206 val = adin_get_reg_value(phydev, "adi,tx-internal-delay-ps", 207 adin_rgmii_delays, 208 ADIN1300_RGMII_2_00_NS); 209 reg &= ~ADIN1300_GE_RGMII_GTX_MSK; 210 reg |= ADIN1300_GE_RGMII_GTX_SEL(val); 211 } else { 212 reg &= ~ADIN1300_GE_RGMII_TXID_EN; 213 } 214 215 return phy_write_mmd(phydev, MDIO_MMD_VEND1, 216 ADIN1300_GE_RGMII_CFG_REG, reg); 217 } 218 219 static int adin_config_rmii_mode(struct phy_device *phydev) 220 { 221 u32 val; 222 int reg; 223 224 if (phydev->interface != PHY_INTERFACE_MODE_RMII) 225 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 226 ADIN1300_GE_RMII_CFG_REG, 227 ADIN1300_GE_RMII_EN); 228 229 reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_GE_RMII_CFG_REG); 230 if (reg < 0) 231 return reg; 232 233 reg |= ADIN1300_GE_RMII_EN; 234 235 val = adin_get_reg_value(phydev, "adi,fifo-depth-bits", 236 adin_rmii_fifo_depths, 237 ADIN1300_RMII_8_BITS); 238 239 reg &= ~ADIN1300_GE_RMII_FIFO_DEPTH_MSK; 240 reg |= ADIN1300_GE_RMII_FIFO_DEPTH_SEL(val); 241 242 return phy_write_mmd(phydev, MDIO_MMD_VEND1, 243 ADIN1300_GE_RMII_CFG_REG, reg); 244 } 245 246 static int adin_config_init(struct phy_device *phydev) 247 { 248 int rc; 249 250 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; 251 252 rc = genphy_config_init(phydev); 253 if (rc < 0) 254 return rc; 255 256 rc = adin_config_rgmii_mode(phydev); 257 if (rc < 0) 258 return rc; 259 260 rc = adin_config_rmii_mode(phydev); 261 if (rc < 0) 262 return rc; 263 264 phydev_dbg(phydev, "PHY is using mode '%s'\n", 265 phy_modes(phydev->interface)); 266 267 return 0; 268 } 269 270 static int adin_phy_ack_intr(struct phy_device *phydev) 271 { 272 /* Clear pending interrupts */ 273 int rc = phy_read(phydev, ADIN1300_INT_STATUS_REG); 274 275 return rc < 0 ? rc : 0; 276 } 277 278 static int adin_phy_config_intr(struct phy_device *phydev) 279 { 280 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) 281 return phy_set_bits(phydev, ADIN1300_INT_MASK_REG, 282 ADIN1300_INT_MASK_EN); 283 284 return phy_clear_bits(phydev, ADIN1300_INT_MASK_REG, 285 ADIN1300_INT_MASK_EN); 286 } 287 288 static int adin_cl45_to_adin_reg(struct phy_device *phydev, int devad, 289 u16 cl45_regnum) 290 { 291 struct adin_clause45_mmd_map *m; 292 int i; 293 294 if (devad == MDIO_MMD_VEND1) 295 return cl45_regnum; 296 297 for (i = 0; i < ARRAY_SIZE(adin_clause45_mmd_map); i++) { 298 m = &adin_clause45_mmd_map[i]; 299 if (m->devad == devad && m->cl45_regnum == cl45_regnum) 300 return m->adin_regnum; 301 } 302 303 phydev_err(phydev, 304 "No translation available for devad: %d reg: %04x\n", 305 devad, cl45_regnum); 306 307 return -EINVAL; 308 } 309 310 static int adin_read_mmd(struct phy_device *phydev, int devad, u16 regnum) 311 { 312 struct mii_bus *bus = phydev->mdio.bus; 313 int phy_addr = phydev->mdio.addr; 314 int adin_regnum; 315 int err; 316 317 adin_regnum = adin_cl45_to_adin_reg(phydev, devad, regnum); 318 if (adin_regnum < 0) 319 return adin_regnum; 320 321 err = __mdiobus_write(bus, phy_addr, ADIN1300_MII_EXT_REG_PTR, 322 adin_regnum); 323 if (err) 324 return err; 325 326 return __mdiobus_read(bus, phy_addr, ADIN1300_MII_EXT_REG_DATA); 327 } 328 329 static int adin_write_mmd(struct phy_device *phydev, int devad, u16 regnum, 330 u16 val) 331 { 332 struct mii_bus *bus = phydev->mdio.bus; 333 int phy_addr = phydev->mdio.addr; 334 int adin_regnum; 335 int err; 336 337 adin_regnum = adin_cl45_to_adin_reg(phydev, devad, regnum); 338 if (adin_regnum < 0) 339 return adin_regnum; 340 341 err = __mdiobus_write(bus, phy_addr, ADIN1300_MII_EXT_REG_PTR, 342 adin_regnum); 343 if (err) 344 return err; 345 346 return __mdiobus_write(bus, phy_addr, ADIN1300_MII_EXT_REG_DATA, val); 347 } 348 349 static int adin_config_mdix(struct phy_device *phydev) 350 { 351 bool auto_en, mdix_en; 352 int reg; 353 354 mdix_en = false; 355 auto_en = false; 356 switch (phydev->mdix_ctrl) { 357 case ETH_TP_MDI: 358 break; 359 case ETH_TP_MDI_X: 360 mdix_en = true; 361 break; 362 case ETH_TP_MDI_AUTO: 363 auto_en = true; 364 break; 365 default: 366 return -EINVAL; 367 } 368 369 reg = phy_read(phydev, ADIN1300_PHY_CTRL1); 370 if (reg < 0) 371 return reg; 372 373 if (mdix_en) 374 reg |= ADIN1300_MAN_MDIX_EN; 375 else 376 reg &= ~ADIN1300_MAN_MDIX_EN; 377 378 if (auto_en) 379 reg |= ADIN1300_AUTO_MDI_EN; 380 else 381 reg &= ~ADIN1300_AUTO_MDI_EN; 382 383 return phy_write(phydev, ADIN1300_PHY_CTRL1, reg); 384 } 385 386 static int adin_config_aneg(struct phy_device *phydev) 387 { 388 int ret; 389 390 ret = adin_config_mdix(phydev); 391 if (ret) 392 return ret; 393 394 return genphy_config_aneg(phydev); 395 } 396 397 static int adin_mdix_update(struct phy_device *phydev) 398 { 399 bool auto_en, mdix_en; 400 bool swapped; 401 int reg; 402 403 reg = phy_read(phydev, ADIN1300_PHY_CTRL1); 404 if (reg < 0) 405 return reg; 406 407 auto_en = !!(reg & ADIN1300_AUTO_MDI_EN); 408 mdix_en = !!(reg & ADIN1300_MAN_MDIX_EN); 409 410 /* If MDI/MDIX is forced, just read it from the control reg */ 411 if (!auto_en) { 412 if (mdix_en) 413 phydev->mdix = ETH_TP_MDI_X; 414 else 415 phydev->mdix = ETH_TP_MDI; 416 return 0; 417 } 418 419 /** 420 * Otherwise, we need to deduce it from the PHY status2 reg. 421 * When Auto-MDI is enabled, the ADIN1300_MAN_MDIX_EN bit implies 422 * a preference for MDIX when it is set. 423 */ 424 reg = phy_read(phydev, ADIN1300_PHY_STATUS1); 425 if (reg < 0) 426 return reg; 427 428 swapped = !!(reg & ADIN1300_PAIR_01_SWAP); 429 430 if (mdix_en != swapped) 431 phydev->mdix = ETH_TP_MDI_X; 432 else 433 phydev->mdix = ETH_TP_MDI; 434 435 return 0; 436 } 437 438 static int adin_read_status(struct phy_device *phydev) 439 { 440 int ret; 441 442 ret = adin_mdix_update(phydev); 443 if (ret < 0) 444 return ret; 445 446 return genphy_read_status(phydev); 447 } 448 449 static int adin_soft_reset(struct phy_device *phydev) 450 { 451 int rc; 452 453 /* The reset bit is self-clearing, set it and wait */ 454 rc = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, 455 ADIN1300_GE_SOFT_RESET_REG, 456 ADIN1300_GE_SOFT_RESET); 457 if (rc < 0) 458 return rc; 459 460 msleep(10); 461 462 /* If we get a read error something may be wrong */ 463 rc = phy_read_mmd(phydev, MDIO_MMD_VEND1, 464 ADIN1300_GE_SOFT_RESET_REG); 465 466 return rc < 0 ? rc : 0; 467 } 468 469 static struct phy_driver adin_driver[] = { 470 { 471 PHY_ID_MATCH_MODEL(PHY_ID_ADIN1200), 472 .name = "ADIN1200", 473 .config_init = adin_config_init, 474 .soft_reset = adin_soft_reset, 475 .config_aneg = adin_config_aneg, 476 .read_status = adin_read_status, 477 .ack_interrupt = adin_phy_ack_intr, 478 .config_intr = adin_phy_config_intr, 479 .resume = genphy_resume, 480 .suspend = genphy_suspend, 481 .read_mmd = adin_read_mmd, 482 .write_mmd = adin_write_mmd, 483 }, 484 { 485 PHY_ID_MATCH_MODEL(PHY_ID_ADIN1300), 486 .name = "ADIN1300", 487 .config_init = adin_config_init, 488 .soft_reset = adin_soft_reset, 489 .config_aneg = adin_config_aneg, 490 .read_status = adin_read_status, 491 .ack_interrupt = adin_phy_ack_intr, 492 .config_intr = adin_phy_config_intr, 493 .resume = genphy_resume, 494 .suspend = genphy_suspend, 495 .read_mmd = adin_read_mmd, 496 .write_mmd = adin_write_mmd, 497 }, 498 }; 499 500 module_phy_driver(adin_driver); 501 502 static struct mdio_device_id __maybe_unused adin_tbl[] = { 503 { PHY_ID_MATCH_MODEL(PHY_ID_ADIN1200) }, 504 { PHY_ID_MATCH_MODEL(PHY_ID_ADIN1300) }, 505 { } 506 }; 507 508 MODULE_DEVICE_TABLE(mdio, adin_tbl); 509 MODULE_DESCRIPTION("Analog Devices Industrial Ethernet PHY driver"); 510 MODULE_LICENSE("GPL"); 511