1 // SPDX-License-Identifier: GPL-2.0+ 2 /** 3 * Driver for Analog Devices Industrial Ethernet PHYs 4 * 5 * Copyright 2019 Analog Devices Inc. 6 */ 7 #include <linux/kernel.h> 8 #include <linux/bitfield.h> 9 #include <linux/delay.h> 10 #include <linux/errno.h> 11 #include <linux/ethtool_netlink.h> 12 #include <linux/init.h> 13 #include <linux/module.h> 14 #include <linux/mii.h> 15 #include <linux/phy.h> 16 #include <linux/property.h> 17 18 #define PHY_ID_ADIN1200 0x0283bc20 19 #define PHY_ID_ADIN1300 0x0283bc30 20 21 #define ADIN1300_MII_EXT_REG_PTR 0x0010 22 #define ADIN1300_MII_EXT_REG_DATA 0x0011 23 24 #define ADIN1300_PHY_CTRL1 0x0012 25 #define ADIN1300_AUTO_MDI_EN BIT(10) 26 #define ADIN1300_MAN_MDIX_EN BIT(9) 27 #define ADIN1300_DIAG_CLK_EN BIT(2) 28 29 #define ADIN1300_RX_ERR_CNT 0x0014 30 31 #define ADIN1300_PHY_CTRL_STATUS2 0x0015 32 #define ADIN1300_NRG_PD_EN BIT(3) 33 #define ADIN1300_NRG_PD_TX_EN BIT(2) 34 #define ADIN1300_NRG_PD_STATUS BIT(1) 35 36 #define ADIN1300_PHY_CTRL2 0x0016 37 #define ADIN1300_DOWNSPEED_AN_100_EN BIT(11) 38 #define ADIN1300_DOWNSPEED_AN_10_EN BIT(10) 39 #define ADIN1300_GROUP_MDIO_EN BIT(6) 40 #define ADIN1300_DOWNSPEEDS_EN \ 41 (ADIN1300_DOWNSPEED_AN_100_EN | ADIN1300_DOWNSPEED_AN_10_EN) 42 43 #define ADIN1300_PHY_CTRL3 0x0017 44 #define ADIN1300_LINKING_EN BIT(13) 45 #define ADIN1300_DOWNSPEED_RETRIES_MSK GENMASK(12, 10) 46 47 #define ADIN1300_INT_MASK_REG 0x0018 48 #define ADIN1300_INT_MDIO_SYNC_EN BIT(9) 49 #define ADIN1300_INT_ANEG_STAT_CHNG_EN BIT(8) 50 #define ADIN1300_INT_ANEG_PAGE_RX_EN BIT(6) 51 #define ADIN1300_INT_IDLE_ERR_CNT_EN BIT(5) 52 #define ADIN1300_INT_MAC_FIFO_OU_EN BIT(4) 53 #define ADIN1300_INT_RX_STAT_CHNG_EN BIT(3) 54 #define ADIN1300_INT_LINK_STAT_CHNG_EN BIT(2) 55 #define ADIN1300_INT_SPEED_CHNG_EN BIT(1) 56 #define ADIN1300_INT_HW_IRQ_EN BIT(0) 57 #define ADIN1300_INT_MASK_EN \ 58 (ADIN1300_INT_LINK_STAT_CHNG_EN | ADIN1300_INT_HW_IRQ_EN) 59 #define ADIN1300_INT_STATUS_REG 0x0019 60 61 #define ADIN1300_PHY_STATUS1 0x001a 62 #define ADIN1300_PAIR_01_SWAP BIT(11) 63 64 /* EEE register addresses, accessible via Clause 22 access using 65 * ADIN1300_MII_EXT_REG_PTR & ADIN1300_MII_EXT_REG_DATA. 66 * The bit-fields are the same as specified by IEEE for EEE. 67 */ 68 #define ADIN1300_EEE_CAP_REG 0x8000 69 #define ADIN1300_EEE_ADV_REG 0x8001 70 #define ADIN1300_EEE_LPABLE_REG 0x8002 71 #define ADIN1300_CLOCK_STOP_REG 0x9400 72 #define ADIN1300_LPI_WAKE_ERR_CNT_REG 0xa000 73 74 #define ADIN1300_CDIAG_RUN 0xba1b 75 #define ADIN1300_CDIAG_RUN_EN BIT(0) 76 77 /* 78 * The XSIM3/2/1 and XSHRT3/2/1 are actually relative. 79 * For CDIAG_DTLD_RSLTS(0) it's ADIN1300_CDIAG_RSLT_XSIM3/2/1 80 * For CDIAG_DTLD_RSLTS(1) it's ADIN1300_CDIAG_RSLT_XSIM3/2/0 81 * For CDIAG_DTLD_RSLTS(2) it's ADIN1300_CDIAG_RSLT_XSIM3/1/0 82 * For CDIAG_DTLD_RSLTS(3) it's ADIN1300_CDIAG_RSLT_XSIM2/1/0 83 */ 84 #define ADIN1300_CDIAG_DTLD_RSLTS(x) (0xba1d + (x)) 85 #define ADIN1300_CDIAG_RSLT_BUSY BIT(10) 86 #define ADIN1300_CDIAG_RSLT_XSIM3 BIT(9) 87 #define ADIN1300_CDIAG_RSLT_XSIM2 BIT(8) 88 #define ADIN1300_CDIAG_RSLT_XSIM1 BIT(7) 89 #define ADIN1300_CDIAG_RSLT_SIM BIT(6) 90 #define ADIN1300_CDIAG_RSLT_XSHRT3 BIT(5) 91 #define ADIN1300_CDIAG_RSLT_XSHRT2 BIT(4) 92 #define ADIN1300_CDIAG_RSLT_XSHRT1 BIT(3) 93 #define ADIN1300_CDIAG_RSLT_SHRT BIT(2) 94 #define ADIN1300_CDIAG_RSLT_OPEN BIT(1) 95 #define ADIN1300_CDIAG_RSLT_GOOD BIT(0) 96 97 #define ADIN1300_CDIAG_FLT_DIST(x) (0xba21 + (x)) 98 99 #define ADIN1300_GE_SOFT_RESET_REG 0xff0c 100 #define ADIN1300_GE_SOFT_RESET BIT(0) 101 102 #define ADIN1300_GE_RGMII_CFG_REG 0xff23 103 #define ADIN1300_GE_RGMII_RX_MSK GENMASK(8, 6) 104 #define ADIN1300_GE_RGMII_RX_SEL(x) \ 105 FIELD_PREP(ADIN1300_GE_RGMII_RX_MSK, x) 106 #define ADIN1300_GE_RGMII_GTX_MSK GENMASK(5, 3) 107 #define ADIN1300_GE_RGMII_GTX_SEL(x) \ 108 FIELD_PREP(ADIN1300_GE_RGMII_GTX_MSK, x) 109 #define ADIN1300_GE_RGMII_RXID_EN BIT(2) 110 #define ADIN1300_GE_RGMII_TXID_EN BIT(1) 111 #define ADIN1300_GE_RGMII_EN BIT(0) 112 113 /* RGMII internal delay settings for rx and tx for ADIN1300 */ 114 #define ADIN1300_RGMII_1_60_NS 0x0001 115 #define ADIN1300_RGMII_1_80_NS 0x0002 116 #define ADIN1300_RGMII_2_00_NS 0x0000 117 #define ADIN1300_RGMII_2_20_NS 0x0006 118 #define ADIN1300_RGMII_2_40_NS 0x0007 119 120 #define ADIN1300_GE_RMII_CFG_REG 0xff24 121 #define ADIN1300_GE_RMII_FIFO_DEPTH_MSK GENMASK(6, 4) 122 #define ADIN1300_GE_RMII_FIFO_DEPTH_SEL(x) \ 123 FIELD_PREP(ADIN1300_GE_RMII_FIFO_DEPTH_MSK, x) 124 #define ADIN1300_GE_RMII_EN BIT(0) 125 126 /* RMII fifo depth values */ 127 #define ADIN1300_RMII_4_BITS 0x0000 128 #define ADIN1300_RMII_8_BITS 0x0001 129 #define ADIN1300_RMII_12_BITS 0x0002 130 #define ADIN1300_RMII_16_BITS 0x0003 131 #define ADIN1300_RMII_20_BITS 0x0004 132 #define ADIN1300_RMII_24_BITS 0x0005 133 134 /** 135 * struct adin_cfg_reg_map - map a config value to aregister value 136 * @cfg: value in device configuration 137 * @reg: value in the register 138 */ 139 struct adin_cfg_reg_map { 140 int cfg; 141 int reg; 142 }; 143 144 static const struct adin_cfg_reg_map adin_rgmii_delays[] = { 145 { 1600, ADIN1300_RGMII_1_60_NS }, 146 { 1800, ADIN1300_RGMII_1_80_NS }, 147 { 2000, ADIN1300_RGMII_2_00_NS }, 148 { 2200, ADIN1300_RGMII_2_20_NS }, 149 { 2400, ADIN1300_RGMII_2_40_NS }, 150 { }, 151 }; 152 153 static const struct adin_cfg_reg_map adin_rmii_fifo_depths[] = { 154 { 4, ADIN1300_RMII_4_BITS }, 155 { 8, ADIN1300_RMII_8_BITS }, 156 { 12, ADIN1300_RMII_12_BITS }, 157 { 16, ADIN1300_RMII_16_BITS }, 158 { 20, ADIN1300_RMII_20_BITS }, 159 { 24, ADIN1300_RMII_24_BITS }, 160 { }, 161 }; 162 163 /** 164 * struct adin_clause45_mmd_map - map to convert Clause 45 regs to Clause 22 165 * @devad: device address used in Clause 45 access 166 * @cl45_regnum: register address defined by Clause 45 167 * @adin_regnum: equivalent register address accessible via Clause 22 168 */ 169 struct adin_clause45_mmd_map { 170 int devad; 171 u16 cl45_regnum; 172 u16 adin_regnum; 173 }; 174 175 static const struct adin_clause45_mmd_map adin_clause45_mmd_map[] = { 176 { MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE, ADIN1300_EEE_CAP_REG }, 177 { MDIO_MMD_AN, MDIO_AN_EEE_LPABLE, ADIN1300_EEE_LPABLE_REG }, 178 { MDIO_MMD_AN, MDIO_AN_EEE_ADV, ADIN1300_EEE_ADV_REG }, 179 { MDIO_MMD_PCS, MDIO_CTRL1, ADIN1300_CLOCK_STOP_REG }, 180 { MDIO_MMD_PCS, MDIO_PCS_EEE_WK_ERR, ADIN1300_LPI_WAKE_ERR_CNT_REG }, 181 }; 182 183 struct adin_hw_stat { 184 const char *string; 185 u16 reg1; 186 u16 reg2; 187 }; 188 189 static const struct adin_hw_stat adin_hw_stats[] = { 190 { "total_frames_checked_count", 0x940A, 0x940B }, /* hi + lo */ 191 { "length_error_frames_count", 0x940C }, 192 { "alignment_error_frames_count", 0x940D }, 193 { "symbol_error_count", 0x940E }, 194 { "oversized_frames_count", 0x940F }, 195 { "undersized_frames_count", 0x9410 }, 196 { "odd_nibble_frames_count", 0x9411 }, 197 { "odd_preamble_packet_count", 0x9412 }, 198 { "dribble_bits_frames_count", 0x9413 }, 199 { "false_carrier_events_count", 0x9414 }, 200 }; 201 202 /** 203 * struct adin_priv - ADIN PHY driver private data 204 * @stats: statistic counters for the PHY 205 */ 206 struct adin_priv { 207 u64 stats[ARRAY_SIZE(adin_hw_stats)]; 208 }; 209 210 static int adin_lookup_reg_value(const struct adin_cfg_reg_map *tbl, int cfg) 211 { 212 size_t i; 213 214 for (i = 0; tbl[i].cfg; i++) { 215 if (tbl[i].cfg == cfg) 216 return tbl[i].reg; 217 } 218 219 return -EINVAL; 220 } 221 222 static u32 adin_get_reg_value(struct phy_device *phydev, 223 const char *prop_name, 224 const struct adin_cfg_reg_map *tbl, 225 u32 dflt) 226 { 227 struct device *dev = &phydev->mdio.dev; 228 u32 val; 229 int rc; 230 231 if (device_property_read_u32(dev, prop_name, &val)) 232 return dflt; 233 234 rc = adin_lookup_reg_value(tbl, val); 235 if (rc < 0) { 236 phydev_warn(phydev, 237 "Unsupported value %u for %s using default (%u)\n", 238 val, prop_name, dflt); 239 return dflt; 240 } 241 242 return rc; 243 } 244 245 static int adin_config_rgmii_mode(struct phy_device *phydev) 246 { 247 u32 val; 248 int reg; 249 250 if (!phy_interface_is_rgmii(phydev)) 251 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 252 ADIN1300_GE_RGMII_CFG_REG, 253 ADIN1300_GE_RGMII_EN); 254 255 reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_GE_RGMII_CFG_REG); 256 if (reg < 0) 257 return reg; 258 259 reg |= ADIN1300_GE_RGMII_EN; 260 261 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 262 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) { 263 reg |= ADIN1300_GE_RGMII_RXID_EN; 264 265 val = adin_get_reg_value(phydev, "adi,rx-internal-delay-ps", 266 adin_rgmii_delays, 267 ADIN1300_RGMII_2_00_NS); 268 reg &= ~ADIN1300_GE_RGMII_RX_MSK; 269 reg |= ADIN1300_GE_RGMII_RX_SEL(val); 270 } else { 271 reg &= ~ADIN1300_GE_RGMII_RXID_EN; 272 } 273 274 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 275 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) { 276 reg |= ADIN1300_GE_RGMII_TXID_EN; 277 278 val = adin_get_reg_value(phydev, "adi,tx-internal-delay-ps", 279 adin_rgmii_delays, 280 ADIN1300_RGMII_2_00_NS); 281 reg &= ~ADIN1300_GE_RGMII_GTX_MSK; 282 reg |= ADIN1300_GE_RGMII_GTX_SEL(val); 283 } else { 284 reg &= ~ADIN1300_GE_RGMII_TXID_EN; 285 } 286 287 return phy_write_mmd(phydev, MDIO_MMD_VEND1, 288 ADIN1300_GE_RGMII_CFG_REG, reg); 289 } 290 291 static int adin_config_rmii_mode(struct phy_device *phydev) 292 { 293 u32 val; 294 int reg; 295 296 if (phydev->interface != PHY_INTERFACE_MODE_RMII) 297 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 298 ADIN1300_GE_RMII_CFG_REG, 299 ADIN1300_GE_RMII_EN); 300 301 reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_GE_RMII_CFG_REG); 302 if (reg < 0) 303 return reg; 304 305 reg |= ADIN1300_GE_RMII_EN; 306 307 val = adin_get_reg_value(phydev, "adi,fifo-depth-bits", 308 adin_rmii_fifo_depths, 309 ADIN1300_RMII_8_BITS); 310 311 reg &= ~ADIN1300_GE_RMII_FIFO_DEPTH_MSK; 312 reg |= ADIN1300_GE_RMII_FIFO_DEPTH_SEL(val); 313 314 return phy_write_mmd(phydev, MDIO_MMD_VEND1, 315 ADIN1300_GE_RMII_CFG_REG, reg); 316 } 317 318 static int adin_get_downshift(struct phy_device *phydev, u8 *data) 319 { 320 int val, cnt, enable; 321 322 val = phy_read(phydev, ADIN1300_PHY_CTRL2); 323 if (val < 0) 324 return val; 325 326 cnt = phy_read(phydev, ADIN1300_PHY_CTRL3); 327 if (cnt < 0) 328 return cnt; 329 330 enable = FIELD_GET(ADIN1300_DOWNSPEEDS_EN, val); 331 cnt = FIELD_GET(ADIN1300_DOWNSPEED_RETRIES_MSK, cnt); 332 333 *data = (enable && cnt) ? cnt : DOWNSHIFT_DEV_DISABLE; 334 335 return 0; 336 } 337 338 static int adin_set_downshift(struct phy_device *phydev, u8 cnt) 339 { 340 u16 val; 341 int rc; 342 343 if (cnt == DOWNSHIFT_DEV_DISABLE) 344 return phy_clear_bits(phydev, ADIN1300_PHY_CTRL2, 345 ADIN1300_DOWNSPEEDS_EN); 346 347 if (cnt > 7) 348 return -E2BIG; 349 350 val = FIELD_PREP(ADIN1300_DOWNSPEED_RETRIES_MSK, cnt); 351 352 rc = phy_modify(phydev, ADIN1300_PHY_CTRL3, 353 ADIN1300_DOWNSPEED_RETRIES_MSK, 354 val); 355 if (rc < 0) 356 return rc; 357 358 return phy_set_bits(phydev, ADIN1300_PHY_CTRL2, 359 ADIN1300_DOWNSPEEDS_EN); 360 } 361 362 static int adin_get_edpd(struct phy_device *phydev, u16 *tx_interval) 363 { 364 int val; 365 366 val = phy_read(phydev, ADIN1300_PHY_CTRL_STATUS2); 367 if (val < 0) 368 return val; 369 370 if (ADIN1300_NRG_PD_EN & val) { 371 if (val & ADIN1300_NRG_PD_TX_EN) 372 /* default is 1 second */ 373 *tx_interval = ETHTOOL_PHY_EDPD_DFLT_TX_MSECS; 374 else 375 *tx_interval = ETHTOOL_PHY_EDPD_NO_TX; 376 } else { 377 *tx_interval = ETHTOOL_PHY_EDPD_DISABLE; 378 } 379 380 return 0; 381 } 382 383 static int adin_set_edpd(struct phy_device *phydev, u16 tx_interval) 384 { 385 u16 val; 386 387 if (tx_interval == ETHTOOL_PHY_EDPD_DISABLE) 388 return phy_clear_bits(phydev, ADIN1300_PHY_CTRL_STATUS2, 389 (ADIN1300_NRG_PD_EN | ADIN1300_NRG_PD_TX_EN)); 390 391 val = ADIN1300_NRG_PD_EN; 392 393 switch (tx_interval) { 394 case 1000: /* 1 second */ 395 fallthrough; 396 case ETHTOOL_PHY_EDPD_DFLT_TX_MSECS: 397 val |= ADIN1300_NRG_PD_TX_EN; 398 fallthrough; 399 case ETHTOOL_PHY_EDPD_NO_TX: 400 break; 401 default: 402 return -EINVAL; 403 } 404 405 return phy_modify(phydev, ADIN1300_PHY_CTRL_STATUS2, 406 (ADIN1300_NRG_PD_EN | ADIN1300_NRG_PD_TX_EN), 407 val); 408 } 409 410 static int adin_get_tunable(struct phy_device *phydev, 411 struct ethtool_tunable *tuna, void *data) 412 { 413 switch (tuna->id) { 414 case ETHTOOL_PHY_DOWNSHIFT: 415 return adin_get_downshift(phydev, data); 416 case ETHTOOL_PHY_EDPD: 417 return adin_get_edpd(phydev, data); 418 default: 419 return -EOPNOTSUPP; 420 } 421 } 422 423 static int adin_set_tunable(struct phy_device *phydev, 424 struct ethtool_tunable *tuna, const void *data) 425 { 426 switch (tuna->id) { 427 case ETHTOOL_PHY_DOWNSHIFT: 428 return adin_set_downshift(phydev, *(const u8 *)data); 429 case ETHTOOL_PHY_EDPD: 430 return adin_set_edpd(phydev, *(const u16 *)data); 431 default: 432 return -EOPNOTSUPP; 433 } 434 } 435 436 static int adin_config_init(struct phy_device *phydev) 437 { 438 int rc; 439 440 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; 441 442 rc = adin_config_rgmii_mode(phydev); 443 if (rc < 0) 444 return rc; 445 446 rc = adin_config_rmii_mode(phydev); 447 if (rc < 0) 448 return rc; 449 450 rc = adin_set_downshift(phydev, 4); 451 if (rc < 0) 452 return rc; 453 454 rc = adin_set_edpd(phydev, ETHTOOL_PHY_EDPD_DFLT_TX_MSECS); 455 if (rc < 0) 456 return rc; 457 458 phydev_dbg(phydev, "PHY is using mode '%s'\n", 459 phy_modes(phydev->interface)); 460 461 return 0; 462 } 463 464 static int adin_phy_ack_intr(struct phy_device *phydev) 465 { 466 /* Clear pending interrupts */ 467 int rc = phy_read(phydev, ADIN1300_INT_STATUS_REG); 468 469 return rc < 0 ? rc : 0; 470 } 471 472 static int adin_phy_config_intr(struct phy_device *phydev) 473 { 474 int err; 475 476 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 477 err = adin_phy_ack_intr(phydev); 478 if (err) 479 return err; 480 481 err = phy_set_bits(phydev, ADIN1300_INT_MASK_REG, 482 ADIN1300_INT_MASK_EN); 483 } else { 484 err = phy_clear_bits(phydev, ADIN1300_INT_MASK_REG, 485 ADIN1300_INT_MASK_EN); 486 if (err) 487 return err; 488 489 err = adin_phy_ack_intr(phydev); 490 } 491 492 return err; 493 } 494 495 static irqreturn_t adin_phy_handle_interrupt(struct phy_device *phydev) 496 { 497 int irq_status; 498 499 irq_status = phy_read(phydev, ADIN1300_INT_STATUS_REG); 500 if (irq_status < 0) { 501 phy_error(phydev); 502 return IRQ_NONE; 503 } 504 505 if (!(irq_status & ADIN1300_INT_LINK_STAT_CHNG_EN)) 506 return IRQ_NONE; 507 508 phy_trigger_machine(phydev); 509 510 return IRQ_HANDLED; 511 } 512 513 static int adin_cl45_to_adin_reg(struct phy_device *phydev, int devad, 514 u16 cl45_regnum) 515 { 516 const struct adin_clause45_mmd_map *m; 517 int i; 518 519 if (devad == MDIO_MMD_VEND1) 520 return cl45_regnum; 521 522 for (i = 0; i < ARRAY_SIZE(adin_clause45_mmd_map); i++) { 523 m = &adin_clause45_mmd_map[i]; 524 if (m->devad == devad && m->cl45_regnum == cl45_regnum) 525 return m->adin_regnum; 526 } 527 528 phydev_err(phydev, 529 "No translation available for devad: %d reg: %04x\n", 530 devad, cl45_regnum); 531 532 return -EINVAL; 533 } 534 535 static int adin_read_mmd(struct phy_device *phydev, int devad, u16 regnum) 536 { 537 struct mii_bus *bus = phydev->mdio.bus; 538 int phy_addr = phydev->mdio.addr; 539 int adin_regnum; 540 int err; 541 542 adin_regnum = adin_cl45_to_adin_reg(phydev, devad, regnum); 543 if (adin_regnum < 0) 544 return adin_regnum; 545 546 err = __mdiobus_write(bus, phy_addr, ADIN1300_MII_EXT_REG_PTR, 547 adin_regnum); 548 if (err) 549 return err; 550 551 return __mdiobus_read(bus, phy_addr, ADIN1300_MII_EXT_REG_DATA); 552 } 553 554 static int adin_write_mmd(struct phy_device *phydev, int devad, u16 regnum, 555 u16 val) 556 { 557 struct mii_bus *bus = phydev->mdio.bus; 558 int phy_addr = phydev->mdio.addr; 559 int adin_regnum; 560 int err; 561 562 adin_regnum = adin_cl45_to_adin_reg(phydev, devad, regnum); 563 if (adin_regnum < 0) 564 return adin_regnum; 565 566 err = __mdiobus_write(bus, phy_addr, ADIN1300_MII_EXT_REG_PTR, 567 adin_regnum); 568 if (err) 569 return err; 570 571 return __mdiobus_write(bus, phy_addr, ADIN1300_MII_EXT_REG_DATA, val); 572 } 573 574 static int adin_config_mdix(struct phy_device *phydev) 575 { 576 bool auto_en, mdix_en; 577 int reg; 578 579 mdix_en = false; 580 auto_en = false; 581 switch (phydev->mdix_ctrl) { 582 case ETH_TP_MDI: 583 break; 584 case ETH_TP_MDI_X: 585 mdix_en = true; 586 break; 587 case ETH_TP_MDI_AUTO: 588 auto_en = true; 589 break; 590 default: 591 return -EINVAL; 592 } 593 594 reg = phy_read(phydev, ADIN1300_PHY_CTRL1); 595 if (reg < 0) 596 return reg; 597 598 if (mdix_en) 599 reg |= ADIN1300_MAN_MDIX_EN; 600 else 601 reg &= ~ADIN1300_MAN_MDIX_EN; 602 603 if (auto_en) 604 reg |= ADIN1300_AUTO_MDI_EN; 605 else 606 reg &= ~ADIN1300_AUTO_MDI_EN; 607 608 return phy_write(phydev, ADIN1300_PHY_CTRL1, reg); 609 } 610 611 static int adin_config_aneg(struct phy_device *phydev) 612 { 613 int ret; 614 615 ret = phy_clear_bits(phydev, ADIN1300_PHY_CTRL1, ADIN1300_DIAG_CLK_EN); 616 if (ret < 0) 617 return ret; 618 619 ret = phy_set_bits(phydev, ADIN1300_PHY_CTRL3, ADIN1300_LINKING_EN); 620 if (ret < 0) 621 return ret; 622 623 ret = adin_config_mdix(phydev); 624 if (ret) 625 return ret; 626 627 return genphy_config_aneg(phydev); 628 } 629 630 static int adin_mdix_update(struct phy_device *phydev) 631 { 632 bool auto_en, mdix_en; 633 bool swapped; 634 int reg; 635 636 reg = phy_read(phydev, ADIN1300_PHY_CTRL1); 637 if (reg < 0) 638 return reg; 639 640 auto_en = !!(reg & ADIN1300_AUTO_MDI_EN); 641 mdix_en = !!(reg & ADIN1300_MAN_MDIX_EN); 642 643 /* If MDI/MDIX is forced, just read it from the control reg */ 644 if (!auto_en) { 645 if (mdix_en) 646 phydev->mdix = ETH_TP_MDI_X; 647 else 648 phydev->mdix = ETH_TP_MDI; 649 return 0; 650 } 651 652 /** 653 * Otherwise, we need to deduce it from the PHY status2 reg. 654 * When Auto-MDI is enabled, the ADIN1300_MAN_MDIX_EN bit implies 655 * a preference for MDIX when it is set. 656 */ 657 reg = phy_read(phydev, ADIN1300_PHY_STATUS1); 658 if (reg < 0) 659 return reg; 660 661 swapped = !!(reg & ADIN1300_PAIR_01_SWAP); 662 663 if (mdix_en != swapped) 664 phydev->mdix = ETH_TP_MDI_X; 665 else 666 phydev->mdix = ETH_TP_MDI; 667 668 return 0; 669 } 670 671 static int adin_read_status(struct phy_device *phydev) 672 { 673 int ret; 674 675 ret = adin_mdix_update(phydev); 676 if (ret < 0) 677 return ret; 678 679 return genphy_read_status(phydev); 680 } 681 682 static int adin_soft_reset(struct phy_device *phydev) 683 { 684 int rc; 685 686 /* The reset bit is self-clearing, set it and wait */ 687 rc = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, 688 ADIN1300_GE_SOFT_RESET_REG, 689 ADIN1300_GE_SOFT_RESET); 690 if (rc < 0) 691 return rc; 692 693 msleep(20); 694 695 /* If we get a read error something may be wrong */ 696 rc = phy_read_mmd(phydev, MDIO_MMD_VEND1, 697 ADIN1300_GE_SOFT_RESET_REG); 698 699 return rc < 0 ? rc : 0; 700 } 701 702 static int adin_get_sset_count(struct phy_device *phydev) 703 { 704 return ARRAY_SIZE(adin_hw_stats); 705 } 706 707 static void adin_get_strings(struct phy_device *phydev, u8 *data) 708 { 709 int i; 710 711 for (i = 0; i < ARRAY_SIZE(adin_hw_stats); i++) { 712 strlcpy(&data[i * ETH_GSTRING_LEN], 713 adin_hw_stats[i].string, ETH_GSTRING_LEN); 714 } 715 } 716 717 static int adin_read_mmd_stat_regs(struct phy_device *phydev, 718 const struct adin_hw_stat *stat, 719 u32 *val) 720 { 721 int ret; 722 723 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, stat->reg1); 724 if (ret < 0) 725 return ret; 726 727 *val = (ret & 0xffff); 728 729 if (stat->reg2 == 0) 730 return 0; 731 732 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, stat->reg2); 733 if (ret < 0) 734 return ret; 735 736 *val <<= 16; 737 *val |= (ret & 0xffff); 738 739 return 0; 740 } 741 742 static u64 adin_get_stat(struct phy_device *phydev, int i) 743 { 744 const struct adin_hw_stat *stat = &adin_hw_stats[i]; 745 struct adin_priv *priv = phydev->priv; 746 u32 val; 747 int ret; 748 749 if (stat->reg1 > 0x1f) { 750 ret = adin_read_mmd_stat_regs(phydev, stat, &val); 751 if (ret < 0) 752 return (u64)(~0); 753 } else { 754 ret = phy_read(phydev, stat->reg1); 755 if (ret < 0) 756 return (u64)(~0); 757 val = (ret & 0xffff); 758 } 759 760 priv->stats[i] += val; 761 762 return priv->stats[i]; 763 } 764 765 static void adin_get_stats(struct phy_device *phydev, 766 struct ethtool_stats *stats, u64 *data) 767 { 768 int i, rc; 769 770 /* latch copies of all the frame-checker counters */ 771 rc = phy_read(phydev, ADIN1300_RX_ERR_CNT); 772 if (rc < 0) 773 return; 774 775 for (i = 0; i < ARRAY_SIZE(adin_hw_stats); i++) 776 data[i] = adin_get_stat(phydev, i); 777 } 778 779 static int adin_probe(struct phy_device *phydev) 780 { 781 struct device *dev = &phydev->mdio.dev; 782 struct adin_priv *priv; 783 784 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 785 if (!priv) 786 return -ENOMEM; 787 788 phydev->priv = priv; 789 790 return 0; 791 } 792 793 static int adin_cable_test_start(struct phy_device *phydev) 794 { 795 int ret; 796 797 ret = phy_clear_bits(phydev, ADIN1300_PHY_CTRL3, ADIN1300_LINKING_EN); 798 if (ret < 0) 799 return ret; 800 801 ret = phy_clear_bits(phydev, ADIN1300_PHY_CTRL1, ADIN1300_DIAG_CLK_EN); 802 if (ret < 0) 803 return ret; 804 805 /* wait a bit for the clock to stabilize */ 806 msleep(50); 807 808 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_CDIAG_RUN, 809 ADIN1300_CDIAG_RUN_EN); 810 } 811 812 static int adin_cable_test_report_trans(int result) 813 { 814 int mask; 815 816 if (result & ADIN1300_CDIAG_RSLT_GOOD) 817 return ETHTOOL_A_CABLE_RESULT_CODE_OK; 818 if (result & ADIN1300_CDIAG_RSLT_OPEN) 819 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN; 820 821 /* short with other pairs */ 822 mask = ADIN1300_CDIAG_RSLT_XSHRT3 | 823 ADIN1300_CDIAG_RSLT_XSHRT2 | 824 ADIN1300_CDIAG_RSLT_XSHRT1; 825 if (result & mask) 826 return ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT; 827 828 if (result & ADIN1300_CDIAG_RSLT_SHRT) 829 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT; 830 831 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC; 832 } 833 834 static int adin_cable_test_report_pair(struct phy_device *phydev, 835 unsigned int pair) 836 { 837 int fault_rslt; 838 int ret; 839 840 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, 841 ADIN1300_CDIAG_DTLD_RSLTS(pair)); 842 if (ret < 0) 843 return ret; 844 845 fault_rslt = adin_cable_test_report_trans(ret); 846 847 ret = ethnl_cable_test_result(phydev, pair, fault_rslt); 848 if (ret < 0) 849 return ret; 850 851 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, 852 ADIN1300_CDIAG_FLT_DIST(pair)); 853 if (ret < 0) 854 return ret; 855 856 switch (fault_rslt) { 857 case ETHTOOL_A_CABLE_RESULT_CODE_OPEN: 858 case ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT: 859 case ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT: 860 return ethnl_cable_test_fault_length(phydev, pair, ret * 100); 861 default: 862 return 0; 863 } 864 } 865 866 static int adin_cable_test_report(struct phy_device *phydev) 867 { 868 unsigned int pair; 869 int ret; 870 871 for (pair = ETHTOOL_A_CABLE_PAIR_A; pair <= ETHTOOL_A_CABLE_PAIR_D; pair++) { 872 ret = adin_cable_test_report_pair(phydev, pair); 873 if (ret < 0) 874 return ret; 875 } 876 877 return 0; 878 } 879 880 static int adin_cable_test_get_status(struct phy_device *phydev, 881 bool *finished) 882 { 883 int ret; 884 885 *finished = false; 886 887 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_CDIAG_RUN); 888 if (ret < 0) 889 return ret; 890 891 if (ret & ADIN1300_CDIAG_RUN_EN) 892 return 0; 893 894 *finished = true; 895 896 return adin_cable_test_report(phydev); 897 } 898 899 static struct phy_driver adin_driver[] = { 900 { 901 PHY_ID_MATCH_MODEL(PHY_ID_ADIN1200), 902 .name = "ADIN1200", 903 .flags = PHY_POLL_CABLE_TEST, 904 .probe = adin_probe, 905 .config_init = adin_config_init, 906 .soft_reset = adin_soft_reset, 907 .config_aneg = adin_config_aneg, 908 .read_status = adin_read_status, 909 .get_tunable = adin_get_tunable, 910 .set_tunable = adin_set_tunable, 911 .config_intr = adin_phy_config_intr, 912 .handle_interrupt = adin_phy_handle_interrupt, 913 .get_sset_count = adin_get_sset_count, 914 .get_strings = adin_get_strings, 915 .get_stats = adin_get_stats, 916 .resume = genphy_resume, 917 .suspend = genphy_suspend, 918 .read_mmd = adin_read_mmd, 919 .write_mmd = adin_write_mmd, 920 .cable_test_start = adin_cable_test_start, 921 .cable_test_get_status = adin_cable_test_get_status, 922 }, 923 { 924 PHY_ID_MATCH_MODEL(PHY_ID_ADIN1300), 925 .name = "ADIN1300", 926 .flags = PHY_POLL_CABLE_TEST, 927 .probe = adin_probe, 928 .config_init = adin_config_init, 929 .soft_reset = adin_soft_reset, 930 .config_aneg = adin_config_aneg, 931 .read_status = adin_read_status, 932 .get_tunable = adin_get_tunable, 933 .set_tunable = adin_set_tunable, 934 .config_intr = adin_phy_config_intr, 935 .handle_interrupt = adin_phy_handle_interrupt, 936 .get_sset_count = adin_get_sset_count, 937 .get_strings = adin_get_strings, 938 .get_stats = adin_get_stats, 939 .resume = genphy_resume, 940 .suspend = genphy_suspend, 941 .read_mmd = adin_read_mmd, 942 .write_mmd = adin_write_mmd, 943 .cable_test_start = adin_cable_test_start, 944 .cable_test_get_status = adin_cable_test_get_status, 945 }, 946 }; 947 948 module_phy_driver(adin_driver); 949 950 static struct mdio_device_id __maybe_unused adin_tbl[] = { 951 { PHY_ID_MATCH_MODEL(PHY_ID_ADIN1200) }, 952 { PHY_ID_MATCH_MODEL(PHY_ID_ADIN1300) }, 953 { } 954 }; 955 956 MODULE_DEVICE_TABLE(mdio, adin_tbl); 957 MODULE_DESCRIPTION("Analog Devices Industrial Ethernet PHY driver"); 958 MODULE_LICENSE("GPL"); 959