1 // SPDX-License-Identifier: GPL-2.0+ 2 /** 3 * Driver for Analog Devices Industrial Ethernet PHYs 4 * 5 * Copyright 2019 Analog Devices Inc. 6 */ 7 #include <linux/kernel.h> 8 #include <linux/bitfield.h> 9 #include <linux/delay.h> 10 #include <linux/errno.h> 11 #include <linux/init.h> 12 #include <linux/module.h> 13 #include <linux/mii.h> 14 #include <linux/phy.h> 15 #include <linux/property.h> 16 17 #define PHY_ID_ADIN1200 0x0283bc20 18 #define PHY_ID_ADIN1300 0x0283bc30 19 20 #define ADIN1300_MII_EXT_REG_PTR 0x0010 21 #define ADIN1300_MII_EXT_REG_DATA 0x0011 22 23 #define ADIN1300_PHY_CTRL1 0x0012 24 #define ADIN1300_AUTO_MDI_EN BIT(10) 25 #define ADIN1300_MAN_MDIX_EN BIT(9) 26 27 #define ADIN1300_RX_ERR_CNT 0x0014 28 29 #define ADIN1300_PHY_CTRL2 0x0016 30 #define ADIN1300_DOWNSPEED_AN_100_EN BIT(11) 31 #define ADIN1300_DOWNSPEED_AN_10_EN BIT(10) 32 #define ADIN1300_GROUP_MDIO_EN BIT(6) 33 #define ADIN1300_DOWNSPEEDS_EN \ 34 (ADIN1300_DOWNSPEED_AN_100_EN | ADIN1300_DOWNSPEED_AN_10_EN) 35 36 #define ADIN1300_PHY_CTRL3 0x0017 37 #define ADIN1300_LINKING_EN BIT(13) 38 #define ADIN1300_DOWNSPEED_RETRIES_MSK GENMASK(12, 10) 39 40 #define ADIN1300_INT_MASK_REG 0x0018 41 #define ADIN1300_INT_MDIO_SYNC_EN BIT(9) 42 #define ADIN1300_INT_ANEG_STAT_CHNG_EN BIT(8) 43 #define ADIN1300_INT_ANEG_PAGE_RX_EN BIT(6) 44 #define ADIN1300_INT_IDLE_ERR_CNT_EN BIT(5) 45 #define ADIN1300_INT_MAC_FIFO_OU_EN BIT(4) 46 #define ADIN1300_INT_RX_STAT_CHNG_EN BIT(3) 47 #define ADIN1300_INT_LINK_STAT_CHNG_EN BIT(2) 48 #define ADIN1300_INT_SPEED_CHNG_EN BIT(1) 49 #define ADIN1300_INT_HW_IRQ_EN BIT(0) 50 #define ADIN1300_INT_MASK_EN \ 51 (ADIN1300_INT_LINK_STAT_CHNG_EN | ADIN1300_INT_HW_IRQ_EN) 52 #define ADIN1300_INT_STATUS_REG 0x0019 53 54 #define ADIN1300_PHY_STATUS1 0x001a 55 #define ADIN1300_PAIR_01_SWAP BIT(11) 56 57 /* EEE register addresses, accessible via Clause 22 access using 58 * ADIN1300_MII_EXT_REG_PTR & ADIN1300_MII_EXT_REG_DATA. 59 * The bit-fields are the same as specified by IEEE for EEE. 60 */ 61 #define ADIN1300_EEE_CAP_REG 0x8000 62 #define ADIN1300_EEE_ADV_REG 0x8001 63 #define ADIN1300_EEE_LPABLE_REG 0x8002 64 #define ADIN1300_CLOCK_STOP_REG 0x9400 65 #define ADIN1300_LPI_WAKE_ERR_CNT_REG 0xa000 66 67 #define ADIN1300_GE_SOFT_RESET_REG 0xff0c 68 #define ADIN1300_GE_SOFT_RESET BIT(0) 69 70 #define ADIN1300_GE_RGMII_CFG_REG 0xff23 71 #define ADIN1300_GE_RGMII_RX_MSK GENMASK(8, 6) 72 #define ADIN1300_GE_RGMII_RX_SEL(x) \ 73 FIELD_PREP(ADIN1300_GE_RGMII_RX_MSK, x) 74 #define ADIN1300_GE_RGMII_GTX_MSK GENMASK(5, 3) 75 #define ADIN1300_GE_RGMII_GTX_SEL(x) \ 76 FIELD_PREP(ADIN1300_GE_RGMII_GTX_MSK, x) 77 #define ADIN1300_GE_RGMII_RXID_EN BIT(2) 78 #define ADIN1300_GE_RGMII_TXID_EN BIT(1) 79 #define ADIN1300_GE_RGMII_EN BIT(0) 80 81 /* RGMII internal delay settings for rx and tx for ADIN1300 */ 82 #define ADIN1300_RGMII_1_60_NS 0x0001 83 #define ADIN1300_RGMII_1_80_NS 0x0002 84 #define ADIN1300_RGMII_2_00_NS 0x0000 85 #define ADIN1300_RGMII_2_20_NS 0x0006 86 #define ADIN1300_RGMII_2_40_NS 0x0007 87 88 #define ADIN1300_GE_RMII_CFG_REG 0xff24 89 #define ADIN1300_GE_RMII_FIFO_DEPTH_MSK GENMASK(6, 4) 90 #define ADIN1300_GE_RMII_FIFO_DEPTH_SEL(x) \ 91 FIELD_PREP(ADIN1300_GE_RMII_FIFO_DEPTH_MSK, x) 92 #define ADIN1300_GE_RMII_EN BIT(0) 93 94 /* RMII fifo depth values */ 95 #define ADIN1300_RMII_4_BITS 0x0000 96 #define ADIN1300_RMII_8_BITS 0x0001 97 #define ADIN1300_RMII_12_BITS 0x0002 98 #define ADIN1300_RMII_16_BITS 0x0003 99 #define ADIN1300_RMII_20_BITS 0x0004 100 #define ADIN1300_RMII_24_BITS 0x0005 101 102 /** 103 * struct adin_cfg_reg_map - map a config value to aregister value 104 * @cfg value in device configuration 105 * @reg value in the register 106 */ 107 struct adin_cfg_reg_map { 108 int cfg; 109 int reg; 110 }; 111 112 static const struct adin_cfg_reg_map adin_rgmii_delays[] = { 113 { 1600, ADIN1300_RGMII_1_60_NS }, 114 { 1800, ADIN1300_RGMII_1_80_NS }, 115 { 2000, ADIN1300_RGMII_2_00_NS }, 116 { 2200, ADIN1300_RGMII_2_20_NS }, 117 { 2400, ADIN1300_RGMII_2_40_NS }, 118 { }, 119 }; 120 121 static const struct adin_cfg_reg_map adin_rmii_fifo_depths[] = { 122 { 4, ADIN1300_RMII_4_BITS }, 123 { 8, ADIN1300_RMII_8_BITS }, 124 { 12, ADIN1300_RMII_12_BITS }, 125 { 16, ADIN1300_RMII_16_BITS }, 126 { 20, ADIN1300_RMII_20_BITS }, 127 { 24, ADIN1300_RMII_24_BITS }, 128 { }, 129 }; 130 131 /** 132 * struct adin_clause45_mmd_map - map to convert Clause 45 regs to Clause 22 133 * @devad device address used in Clause 45 access 134 * @cl45_regnum register address defined by Clause 45 135 * @adin_regnum equivalent register address accessible via Clause 22 136 */ 137 struct adin_clause45_mmd_map { 138 int devad; 139 u16 cl45_regnum; 140 u16 adin_regnum; 141 }; 142 143 static struct adin_clause45_mmd_map adin_clause45_mmd_map[] = { 144 { MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE, ADIN1300_EEE_CAP_REG }, 145 { MDIO_MMD_AN, MDIO_AN_EEE_LPABLE, ADIN1300_EEE_LPABLE_REG }, 146 { MDIO_MMD_AN, MDIO_AN_EEE_ADV, ADIN1300_EEE_ADV_REG }, 147 { MDIO_MMD_PCS, MDIO_CTRL1, ADIN1300_CLOCK_STOP_REG }, 148 { MDIO_MMD_PCS, MDIO_PCS_EEE_WK_ERR, ADIN1300_LPI_WAKE_ERR_CNT_REG }, 149 }; 150 151 struct adin_hw_stat { 152 const char *string; 153 u16 reg1; 154 u16 reg2; 155 }; 156 157 static struct adin_hw_stat adin_hw_stats[] = { 158 { "total_frames_checked_count", 0x940A, 0x940B }, /* hi + lo */ 159 { "length_error_frames_count", 0x940C }, 160 { "alignment_error_frames_count", 0x940D }, 161 { "symbol_error_count", 0x940E }, 162 { "oversized_frames_count", 0x940F }, 163 { "undersized_frames_count", 0x9410 }, 164 { "odd_nibble_frames_count", 0x9411 }, 165 { "odd_preamble_packet_count", 0x9412 }, 166 { "dribble_bits_frames_count", 0x9413 }, 167 { "false_carrier_events_count", 0x9414 }, 168 }; 169 170 /** 171 * struct adin_priv - ADIN PHY driver private data 172 * stats statistic counters for the PHY 173 */ 174 struct adin_priv { 175 u64 stats[ARRAY_SIZE(adin_hw_stats)]; 176 }; 177 178 static int adin_lookup_reg_value(const struct adin_cfg_reg_map *tbl, int cfg) 179 { 180 size_t i; 181 182 for (i = 0; tbl[i].cfg; i++) { 183 if (tbl[i].cfg == cfg) 184 return tbl[i].reg; 185 } 186 187 return -EINVAL; 188 } 189 190 static u32 adin_get_reg_value(struct phy_device *phydev, 191 const char *prop_name, 192 const struct adin_cfg_reg_map *tbl, 193 u32 dflt) 194 { 195 struct device *dev = &phydev->mdio.dev; 196 u32 val; 197 int rc; 198 199 if (device_property_read_u32(dev, prop_name, &val)) 200 return dflt; 201 202 rc = adin_lookup_reg_value(tbl, val); 203 if (rc < 0) { 204 phydev_warn(phydev, 205 "Unsupported value %u for %s using default (%u)\n", 206 val, prop_name, dflt); 207 return dflt; 208 } 209 210 return rc; 211 } 212 213 static int adin_config_rgmii_mode(struct phy_device *phydev) 214 { 215 u32 val; 216 int reg; 217 218 if (!phy_interface_is_rgmii(phydev)) 219 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 220 ADIN1300_GE_RGMII_CFG_REG, 221 ADIN1300_GE_RGMII_EN); 222 223 reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_GE_RGMII_CFG_REG); 224 if (reg < 0) 225 return reg; 226 227 reg |= ADIN1300_GE_RGMII_EN; 228 229 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 230 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) { 231 reg |= ADIN1300_GE_RGMII_RXID_EN; 232 233 val = adin_get_reg_value(phydev, "adi,rx-internal-delay-ps", 234 adin_rgmii_delays, 235 ADIN1300_RGMII_2_00_NS); 236 reg &= ~ADIN1300_GE_RGMII_RX_MSK; 237 reg |= ADIN1300_GE_RGMII_RX_SEL(val); 238 } else { 239 reg &= ~ADIN1300_GE_RGMII_RXID_EN; 240 } 241 242 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 243 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) { 244 reg |= ADIN1300_GE_RGMII_TXID_EN; 245 246 val = adin_get_reg_value(phydev, "adi,tx-internal-delay-ps", 247 adin_rgmii_delays, 248 ADIN1300_RGMII_2_00_NS); 249 reg &= ~ADIN1300_GE_RGMII_GTX_MSK; 250 reg |= ADIN1300_GE_RGMII_GTX_SEL(val); 251 } else { 252 reg &= ~ADIN1300_GE_RGMII_TXID_EN; 253 } 254 255 return phy_write_mmd(phydev, MDIO_MMD_VEND1, 256 ADIN1300_GE_RGMII_CFG_REG, reg); 257 } 258 259 static int adin_config_rmii_mode(struct phy_device *phydev) 260 { 261 u32 val; 262 int reg; 263 264 if (phydev->interface != PHY_INTERFACE_MODE_RMII) 265 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 266 ADIN1300_GE_RMII_CFG_REG, 267 ADIN1300_GE_RMII_EN); 268 269 reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_GE_RMII_CFG_REG); 270 if (reg < 0) 271 return reg; 272 273 reg |= ADIN1300_GE_RMII_EN; 274 275 val = adin_get_reg_value(phydev, "adi,fifo-depth-bits", 276 adin_rmii_fifo_depths, 277 ADIN1300_RMII_8_BITS); 278 279 reg &= ~ADIN1300_GE_RMII_FIFO_DEPTH_MSK; 280 reg |= ADIN1300_GE_RMII_FIFO_DEPTH_SEL(val); 281 282 return phy_write_mmd(phydev, MDIO_MMD_VEND1, 283 ADIN1300_GE_RMII_CFG_REG, reg); 284 } 285 286 static int adin_get_downshift(struct phy_device *phydev, u8 *data) 287 { 288 int val, cnt, enable; 289 290 val = phy_read(phydev, ADIN1300_PHY_CTRL2); 291 if (val < 0) 292 return val; 293 294 cnt = phy_read(phydev, ADIN1300_PHY_CTRL3); 295 if (cnt < 0) 296 return cnt; 297 298 enable = FIELD_GET(ADIN1300_DOWNSPEEDS_EN, val); 299 cnt = FIELD_GET(ADIN1300_DOWNSPEED_RETRIES_MSK, cnt); 300 301 *data = (enable && cnt) ? cnt : DOWNSHIFT_DEV_DISABLE; 302 303 return 0; 304 } 305 306 static int adin_set_downshift(struct phy_device *phydev, u8 cnt) 307 { 308 u16 val; 309 int rc; 310 311 if (cnt == DOWNSHIFT_DEV_DISABLE) 312 return phy_clear_bits(phydev, ADIN1300_PHY_CTRL2, 313 ADIN1300_DOWNSPEEDS_EN); 314 315 if (cnt > 7) 316 return -E2BIG; 317 318 val = FIELD_PREP(ADIN1300_DOWNSPEED_RETRIES_MSK, cnt); 319 val |= ADIN1300_LINKING_EN; 320 321 rc = phy_modify(phydev, ADIN1300_PHY_CTRL3, 322 ADIN1300_LINKING_EN | ADIN1300_DOWNSPEED_RETRIES_MSK, 323 val); 324 if (rc < 0) 325 return rc; 326 327 return phy_set_bits(phydev, ADIN1300_PHY_CTRL2, 328 ADIN1300_DOWNSPEEDS_EN); 329 } 330 331 static int adin_get_tunable(struct phy_device *phydev, 332 struct ethtool_tunable *tuna, void *data) 333 { 334 switch (tuna->id) { 335 case ETHTOOL_PHY_DOWNSHIFT: 336 return adin_get_downshift(phydev, data); 337 default: 338 return -EOPNOTSUPP; 339 } 340 } 341 342 static int adin_set_tunable(struct phy_device *phydev, 343 struct ethtool_tunable *tuna, const void *data) 344 { 345 switch (tuna->id) { 346 case ETHTOOL_PHY_DOWNSHIFT: 347 return adin_set_downshift(phydev, *(const u8 *)data); 348 default: 349 return -EOPNOTSUPP; 350 } 351 } 352 353 static int adin_config_init(struct phy_device *phydev) 354 { 355 int rc; 356 357 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; 358 359 rc = adin_config_rgmii_mode(phydev); 360 if (rc < 0) 361 return rc; 362 363 rc = adin_config_rmii_mode(phydev); 364 if (rc < 0) 365 return rc; 366 367 rc = adin_set_downshift(phydev, 4); 368 if (rc < 0) 369 return rc; 370 371 phydev_dbg(phydev, "PHY is using mode '%s'\n", 372 phy_modes(phydev->interface)); 373 374 return 0; 375 } 376 377 static int adin_phy_ack_intr(struct phy_device *phydev) 378 { 379 /* Clear pending interrupts */ 380 int rc = phy_read(phydev, ADIN1300_INT_STATUS_REG); 381 382 return rc < 0 ? rc : 0; 383 } 384 385 static int adin_phy_config_intr(struct phy_device *phydev) 386 { 387 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) 388 return phy_set_bits(phydev, ADIN1300_INT_MASK_REG, 389 ADIN1300_INT_MASK_EN); 390 391 return phy_clear_bits(phydev, ADIN1300_INT_MASK_REG, 392 ADIN1300_INT_MASK_EN); 393 } 394 395 static int adin_cl45_to_adin_reg(struct phy_device *phydev, int devad, 396 u16 cl45_regnum) 397 { 398 struct adin_clause45_mmd_map *m; 399 int i; 400 401 if (devad == MDIO_MMD_VEND1) 402 return cl45_regnum; 403 404 for (i = 0; i < ARRAY_SIZE(adin_clause45_mmd_map); i++) { 405 m = &adin_clause45_mmd_map[i]; 406 if (m->devad == devad && m->cl45_regnum == cl45_regnum) 407 return m->adin_regnum; 408 } 409 410 phydev_err(phydev, 411 "No translation available for devad: %d reg: %04x\n", 412 devad, cl45_regnum); 413 414 return -EINVAL; 415 } 416 417 static int adin_read_mmd(struct phy_device *phydev, int devad, u16 regnum) 418 { 419 struct mii_bus *bus = phydev->mdio.bus; 420 int phy_addr = phydev->mdio.addr; 421 int adin_regnum; 422 int err; 423 424 adin_regnum = adin_cl45_to_adin_reg(phydev, devad, regnum); 425 if (adin_regnum < 0) 426 return adin_regnum; 427 428 err = __mdiobus_write(bus, phy_addr, ADIN1300_MII_EXT_REG_PTR, 429 adin_regnum); 430 if (err) 431 return err; 432 433 return __mdiobus_read(bus, phy_addr, ADIN1300_MII_EXT_REG_DATA); 434 } 435 436 static int adin_write_mmd(struct phy_device *phydev, int devad, u16 regnum, 437 u16 val) 438 { 439 struct mii_bus *bus = phydev->mdio.bus; 440 int phy_addr = phydev->mdio.addr; 441 int adin_regnum; 442 int err; 443 444 adin_regnum = adin_cl45_to_adin_reg(phydev, devad, regnum); 445 if (adin_regnum < 0) 446 return adin_regnum; 447 448 err = __mdiobus_write(bus, phy_addr, ADIN1300_MII_EXT_REG_PTR, 449 adin_regnum); 450 if (err) 451 return err; 452 453 return __mdiobus_write(bus, phy_addr, ADIN1300_MII_EXT_REG_DATA, val); 454 } 455 456 static int adin_config_mdix(struct phy_device *phydev) 457 { 458 bool auto_en, mdix_en; 459 int reg; 460 461 mdix_en = false; 462 auto_en = false; 463 switch (phydev->mdix_ctrl) { 464 case ETH_TP_MDI: 465 break; 466 case ETH_TP_MDI_X: 467 mdix_en = true; 468 break; 469 case ETH_TP_MDI_AUTO: 470 auto_en = true; 471 break; 472 default: 473 return -EINVAL; 474 } 475 476 reg = phy_read(phydev, ADIN1300_PHY_CTRL1); 477 if (reg < 0) 478 return reg; 479 480 if (mdix_en) 481 reg |= ADIN1300_MAN_MDIX_EN; 482 else 483 reg &= ~ADIN1300_MAN_MDIX_EN; 484 485 if (auto_en) 486 reg |= ADIN1300_AUTO_MDI_EN; 487 else 488 reg &= ~ADIN1300_AUTO_MDI_EN; 489 490 return phy_write(phydev, ADIN1300_PHY_CTRL1, reg); 491 } 492 493 static int adin_config_aneg(struct phy_device *phydev) 494 { 495 int ret; 496 497 ret = adin_config_mdix(phydev); 498 if (ret) 499 return ret; 500 501 return genphy_config_aneg(phydev); 502 } 503 504 static int adin_mdix_update(struct phy_device *phydev) 505 { 506 bool auto_en, mdix_en; 507 bool swapped; 508 int reg; 509 510 reg = phy_read(phydev, ADIN1300_PHY_CTRL1); 511 if (reg < 0) 512 return reg; 513 514 auto_en = !!(reg & ADIN1300_AUTO_MDI_EN); 515 mdix_en = !!(reg & ADIN1300_MAN_MDIX_EN); 516 517 /* If MDI/MDIX is forced, just read it from the control reg */ 518 if (!auto_en) { 519 if (mdix_en) 520 phydev->mdix = ETH_TP_MDI_X; 521 else 522 phydev->mdix = ETH_TP_MDI; 523 return 0; 524 } 525 526 /** 527 * Otherwise, we need to deduce it from the PHY status2 reg. 528 * When Auto-MDI is enabled, the ADIN1300_MAN_MDIX_EN bit implies 529 * a preference for MDIX when it is set. 530 */ 531 reg = phy_read(phydev, ADIN1300_PHY_STATUS1); 532 if (reg < 0) 533 return reg; 534 535 swapped = !!(reg & ADIN1300_PAIR_01_SWAP); 536 537 if (mdix_en != swapped) 538 phydev->mdix = ETH_TP_MDI_X; 539 else 540 phydev->mdix = ETH_TP_MDI; 541 542 return 0; 543 } 544 545 static int adin_read_status(struct phy_device *phydev) 546 { 547 int ret; 548 549 ret = adin_mdix_update(phydev); 550 if (ret < 0) 551 return ret; 552 553 return genphy_read_status(phydev); 554 } 555 556 static int adin_soft_reset(struct phy_device *phydev) 557 { 558 int rc; 559 560 /* The reset bit is self-clearing, set it and wait */ 561 rc = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, 562 ADIN1300_GE_SOFT_RESET_REG, 563 ADIN1300_GE_SOFT_RESET); 564 if (rc < 0) 565 return rc; 566 567 msleep(10); 568 569 /* If we get a read error something may be wrong */ 570 rc = phy_read_mmd(phydev, MDIO_MMD_VEND1, 571 ADIN1300_GE_SOFT_RESET_REG); 572 573 return rc < 0 ? rc : 0; 574 } 575 576 static int adin_get_sset_count(struct phy_device *phydev) 577 { 578 return ARRAY_SIZE(adin_hw_stats); 579 } 580 581 static void adin_get_strings(struct phy_device *phydev, u8 *data) 582 { 583 int i; 584 585 for (i = 0; i < ARRAY_SIZE(adin_hw_stats); i++) { 586 strlcpy(&data[i * ETH_GSTRING_LEN], 587 adin_hw_stats[i].string, ETH_GSTRING_LEN); 588 } 589 } 590 591 static int adin_read_mmd_stat_regs(struct phy_device *phydev, 592 struct adin_hw_stat *stat, 593 u32 *val) 594 { 595 int ret; 596 597 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, stat->reg1); 598 if (ret < 0) 599 return ret; 600 601 *val = (ret & 0xffff); 602 603 if (stat->reg2 == 0) 604 return 0; 605 606 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, stat->reg2); 607 if (ret < 0) 608 return ret; 609 610 *val <<= 16; 611 *val |= (ret & 0xffff); 612 613 return 0; 614 } 615 616 static u64 adin_get_stat(struct phy_device *phydev, int i) 617 { 618 struct adin_hw_stat *stat = &adin_hw_stats[i]; 619 struct adin_priv *priv = phydev->priv; 620 u32 val; 621 int ret; 622 623 if (stat->reg1 > 0x1f) { 624 ret = adin_read_mmd_stat_regs(phydev, stat, &val); 625 if (ret < 0) 626 return (u64)(~0); 627 } else { 628 ret = phy_read(phydev, stat->reg1); 629 if (ret < 0) 630 return (u64)(~0); 631 val = (ret & 0xffff); 632 } 633 634 priv->stats[i] += val; 635 636 return priv->stats[i]; 637 } 638 639 static void adin_get_stats(struct phy_device *phydev, 640 struct ethtool_stats *stats, u64 *data) 641 { 642 int i, rc; 643 644 /* latch copies of all the frame-checker counters */ 645 rc = phy_read(phydev, ADIN1300_RX_ERR_CNT); 646 if (rc < 0) 647 return; 648 649 for (i = 0; i < ARRAY_SIZE(adin_hw_stats); i++) 650 data[i] = adin_get_stat(phydev, i); 651 } 652 653 static int adin_probe(struct phy_device *phydev) 654 { 655 struct device *dev = &phydev->mdio.dev; 656 struct adin_priv *priv; 657 658 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 659 if (!priv) 660 return -ENOMEM; 661 662 phydev->priv = priv; 663 664 return 0; 665 } 666 667 static struct phy_driver adin_driver[] = { 668 { 669 PHY_ID_MATCH_MODEL(PHY_ID_ADIN1200), 670 .name = "ADIN1200", 671 .probe = adin_probe, 672 .config_init = adin_config_init, 673 .soft_reset = adin_soft_reset, 674 .config_aneg = adin_config_aneg, 675 .read_status = adin_read_status, 676 .get_tunable = adin_get_tunable, 677 .set_tunable = adin_set_tunable, 678 .ack_interrupt = adin_phy_ack_intr, 679 .config_intr = adin_phy_config_intr, 680 .get_sset_count = adin_get_sset_count, 681 .get_strings = adin_get_strings, 682 .get_stats = adin_get_stats, 683 .resume = genphy_resume, 684 .suspend = genphy_suspend, 685 .read_mmd = adin_read_mmd, 686 .write_mmd = adin_write_mmd, 687 }, 688 { 689 PHY_ID_MATCH_MODEL(PHY_ID_ADIN1300), 690 .name = "ADIN1300", 691 .probe = adin_probe, 692 .config_init = adin_config_init, 693 .soft_reset = adin_soft_reset, 694 .config_aneg = adin_config_aneg, 695 .read_status = adin_read_status, 696 .get_tunable = adin_get_tunable, 697 .set_tunable = adin_set_tunable, 698 .ack_interrupt = adin_phy_ack_intr, 699 .config_intr = adin_phy_config_intr, 700 .get_sset_count = adin_get_sset_count, 701 .get_strings = adin_get_strings, 702 .get_stats = adin_get_stats, 703 .resume = genphy_resume, 704 .suspend = genphy_suspend, 705 .read_mmd = adin_read_mmd, 706 .write_mmd = adin_write_mmd, 707 }, 708 }; 709 710 module_phy_driver(adin_driver); 711 712 static struct mdio_device_id __maybe_unused adin_tbl[] = { 713 { PHY_ID_MATCH_MODEL(PHY_ID_ADIN1200) }, 714 { PHY_ID_MATCH_MODEL(PHY_ID_ADIN1300) }, 715 { } 716 }; 717 718 MODULE_DEVICE_TABLE(mdio, adin_tbl); 719 MODULE_DESCRIPTION("Analog Devices Industrial Ethernet PHY driver"); 720 MODULE_LICENSE("GPL"); 721