xref: /openbmc/linux/drivers/net/pcs/pcs-xpcs.c (revision f4356947f0297b0962fdd197672db7edf9f58be6)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (c) 2020 Synopsys, Inc. and/or its affiliates.
4  * Synopsys DesignWare XPCS helpers
5  *
6  * Author: Jose Abreu <Jose.Abreu@synopsys.com>
7  */
8 
9 #include <linux/delay.h>
10 #include <linux/pcs/pcs-xpcs.h>
11 #include <linux/mdio.h>
12 #include <linux/phylink.h>
13 #include <linux/workqueue.h>
14 #include "pcs-xpcs.h"
15 
16 #define phylink_pcs_to_xpcs(pl_pcs) \
17 	container_of((pl_pcs), struct dw_xpcs, pcs)
18 
19 static const int xpcs_usxgmii_features[] = {
20 	ETHTOOL_LINK_MODE_Pause_BIT,
21 	ETHTOOL_LINK_MODE_Asym_Pause_BIT,
22 	ETHTOOL_LINK_MODE_Autoneg_BIT,
23 	ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
24 	ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
25 	ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
26 	ETHTOOL_LINK_MODE_2500baseX_Full_BIT,
27 	__ETHTOOL_LINK_MODE_MASK_NBITS,
28 };
29 
30 static const int xpcs_10gkr_features[] = {
31 	ETHTOOL_LINK_MODE_Pause_BIT,
32 	ETHTOOL_LINK_MODE_Asym_Pause_BIT,
33 	ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
34 	__ETHTOOL_LINK_MODE_MASK_NBITS,
35 };
36 
37 static const int xpcs_xlgmii_features[] = {
38 	ETHTOOL_LINK_MODE_Pause_BIT,
39 	ETHTOOL_LINK_MODE_Asym_Pause_BIT,
40 	ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
41 	ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
42 	ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
43 	ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
44 	ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
45 	ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
46 	ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
47 	ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
48 	ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
49 	ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
50 	ETHTOOL_LINK_MODE_50000baseKR_Full_BIT,
51 	ETHTOOL_LINK_MODE_50000baseSR_Full_BIT,
52 	ETHTOOL_LINK_MODE_50000baseCR_Full_BIT,
53 	ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT,
54 	ETHTOOL_LINK_MODE_50000baseDR_Full_BIT,
55 	ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
56 	ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
57 	ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
58 	ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
59 	ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT,
60 	ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT,
61 	ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT,
62 	ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT,
63 	ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT,
64 	__ETHTOOL_LINK_MODE_MASK_NBITS,
65 };
66 
67 static const int xpcs_sgmii_features[] = {
68 	ETHTOOL_LINK_MODE_Pause_BIT,
69 	ETHTOOL_LINK_MODE_Asym_Pause_BIT,
70 	ETHTOOL_LINK_MODE_Autoneg_BIT,
71 	ETHTOOL_LINK_MODE_10baseT_Half_BIT,
72 	ETHTOOL_LINK_MODE_10baseT_Full_BIT,
73 	ETHTOOL_LINK_MODE_100baseT_Half_BIT,
74 	ETHTOOL_LINK_MODE_100baseT_Full_BIT,
75 	ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
76 	ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
77 	__ETHTOOL_LINK_MODE_MASK_NBITS,
78 };
79 
80 static const int xpcs_1000basex_features[] = {
81 	ETHTOOL_LINK_MODE_Pause_BIT,
82 	ETHTOOL_LINK_MODE_Asym_Pause_BIT,
83 	ETHTOOL_LINK_MODE_Autoneg_BIT,
84 	ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
85 	__ETHTOOL_LINK_MODE_MASK_NBITS,
86 };
87 
88 static const int xpcs_2500basex_features[] = {
89 	ETHTOOL_LINK_MODE_Pause_BIT,
90 	ETHTOOL_LINK_MODE_Asym_Pause_BIT,
91 	ETHTOOL_LINK_MODE_Autoneg_BIT,
92 	ETHTOOL_LINK_MODE_2500baseX_Full_BIT,
93 	ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
94 	__ETHTOOL_LINK_MODE_MASK_NBITS,
95 };
96 
97 static const phy_interface_t xpcs_usxgmii_interfaces[] = {
98 	PHY_INTERFACE_MODE_USXGMII,
99 };
100 
101 static const phy_interface_t xpcs_10gkr_interfaces[] = {
102 	PHY_INTERFACE_MODE_10GKR,
103 };
104 
105 static const phy_interface_t xpcs_xlgmii_interfaces[] = {
106 	PHY_INTERFACE_MODE_XLGMII,
107 };
108 
109 static const phy_interface_t xpcs_sgmii_interfaces[] = {
110 	PHY_INTERFACE_MODE_SGMII,
111 };
112 
113 static const phy_interface_t xpcs_1000basex_interfaces[] = {
114 	PHY_INTERFACE_MODE_1000BASEX,
115 };
116 
117 static const phy_interface_t xpcs_2500basex_interfaces[] = {
118 	PHY_INTERFACE_MODE_2500BASEX,
119 	PHY_INTERFACE_MODE_MAX,
120 };
121 
122 enum {
123 	DW_XPCS_USXGMII,
124 	DW_XPCS_10GKR,
125 	DW_XPCS_XLGMII,
126 	DW_XPCS_SGMII,
127 	DW_XPCS_1000BASEX,
128 	DW_XPCS_2500BASEX,
129 	DW_XPCS_INTERFACE_MAX,
130 };
131 
132 struct xpcs_compat {
133 	const int *supported;
134 	const phy_interface_t *interface;
135 	int num_interfaces;
136 	int an_mode;
137 	int (*pma_config)(struct dw_xpcs *xpcs);
138 };
139 
140 struct xpcs_id {
141 	u32 id;
142 	u32 mask;
143 	const struct xpcs_compat *compat;
144 };
145 
146 static const struct xpcs_compat *xpcs_find_compat(const struct xpcs_id *id,
147 						  phy_interface_t interface)
148 {
149 	int i, j;
150 
151 	for (i = 0; i < DW_XPCS_INTERFACE_MAX; i++) {
152 		const struct xpcs_compat *compat = &id->compat[i];
153 
154 		for (j = 0; j < compat->num_interfaces; j++)
155 			if (compat->interface[j] == interface)
156 				return compat;
157 	}
158 
159 	return NULL;
160 }
161 
162 int xpcs_get_an_mode(struct dw_xpcs *xpcs, phy_interface_t interface)
163 {
164 	const struct xpcs_compat *compat;
165 
166 	compat = xpcs_find_compat(xpcs->id, interface);
167 	if (!compat)
168 		return -ENODEV;
169 
170 	return compat->an_mode;
171 }
172 EXPORT_SYMBOL_GPL(xpcs_get_an_mode);
173 
174 static bool __xpcs_linkmode_supported(const struct xpcs_compat *compat,
175 				      enum ethtool_link_mode_bit_indices linkmode)
176 {
177 	int i;
178 
179 	for (i = 0; compat->supported[i] != __ETHTOOL_LINK_MODE_MASK_NBITS; i++)
180 		if (compat->supported[i] == linkmode)
181 			return true;
182 
183 	return false;
184 }
185 
186 #define xpcs_linkmode_supported(compat, mode) \
187 	__xpcs_linkmode_supported(compat, ETHTOOL_LINK_MODE_ ## mode ## _BIT)
188 
189 int xpcs_read(struct dw_xpcs *xpcs, int dev, u32 reg)
190 {
191 	return mdiodev_c45_read(xpcs->mdiodev, dev, reg);
192 }
193 
194 int xpcs_write(struct dw_xpcs *xpcs, int dev, u32 reg, u16 val)
195 {
196 	return mdiodev_c45_write(xpcs->mdiodev, dev, reg, val);
197 }
198 
199 static int xpcs_modify_changed(struct dw_xpcs *xpcs, int dev, u32 reg,
200 			       u16 mask, u16 set)
201 {
202 	return mdiodev_c45_modify_changed(xpcs->mdiodev, dev, reg, mask, set);
203 }
204 
205 static int xpcs_read_vendor(struct dw_xpcs *xpcs, int dev, u32 reg)
206 {
207 	return xpcs_read(xpcs, dev, DW_VENDOR | reg);
208 }
209 
210 static int xpcs_write_vendor(struct dw_xpcs *xpcs, int dev, int reg,
211 			     u16 val)
212 {
213 	return xpcs_write(xpcs, dev, DW_VENDOR | reg, val);
214 }
215 
216 static int xpcs_read_vpcs(struct dw_xpcs *xpcs, int reg)
217 {
218 	return xpcs_read_vendor(xpcs, MDIO_MMD_PCS, reg);
219 }
220 
221 static int xpcs_write_vpcs(struct dw_xpcs *xpcs, int reg, u16 val)
222 {
223 	return xpcs_write_vendor(xpcs, MDIO_MMD_PCS, reg, val);
224 }
225 
226 static int xpcs_poll_reset(struct dw_xpcs *xpcs, int dev)
227 {
228 	/* Poll until the reset bit clears (50ms per retry == 0.6 sec) */
229 	unsigned int retries = 12;
230 	int ret;
231 
232 	do {
233 		msleep(50);
234 		ret = xpcs_read(xpcs, dev, MDIO_CTRL1);
235 		if (ret < 0)
236 			return ret;
237 	} while (ret & MDIO_CTRL1_RESET && --retries);
238 
239 	return (ret & MDIO_CTRL1_RESET) ? -ETIMEDOUT : 0;
240 }
241 
242 static int xpcs_soft_reset(struct dw_xpcs *xpcs,
243 			   const struct xpcs_compat *compat)
244 {
245 	int ret, dev;
246 
247 	switch (compat->an_mode) {
248 	case DW_AN_C73:
249 		dev = MDIO_MMD_PCS;
250 		break;
251 	case DW_AN_C37_SGMII:
252 	case DW_2500BASEX:
253 	case DW_AN_C37_1000BASEX:
254 		dev = MDIO_MMD_VEND2;
255 		break;
256 	default:
257 		return -1;
258 	}
259 
260 	ret = xpcs_write(xpcs, dev, MDIO_CTRL1, MDIO_CTRL1_RESET);
261 	if (ret < 0)
262 		return ret;
263 
264 	return xpcs_poll_reset(xpcs, dev);
265 }
266 
267 #define xpcs_warn(__xpcs, __state, __args...) \
268 ({ \
269 	if ((__state)->link) \
270 		dev_warn(&(__xpcs)->mdiodev->dev, ##__args); \
271 })
272 
273 static int xpcs_read_fault_c73(struct dw_xpcs *xpcs,
274 			       struct phylink_link_state *state,
275 			       u16 pcs_stat1)
276 {
277 	int ret;
278 
279 	if (pcs_stat1 & MDIO_STAT1_FAULT) {
280 		xpcs_warn(xpcs, state, "Link fault condition detected!\n");
281 		return -EFAULT;
282 	}
283 
284 	ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_STAT2);
285 	if (ret < 0)
286 		return ret;
287 
288 	if (ret & MDIO_STAT2_RXFAULT)
289 		xpcs_warn(xpcs, state, "Receiver fault detected!\n");
290 	if (ret & MDIO_STAT2_TXFAULT)
291 		xpcs_warn(xpcs, state, "Transmitter fault detected!\n");
292 
293 	ret = xpcs_read_vendor(xpcs, MDIO_MMD_PCS, DW_VR_XS_PCS_DIG_STS);
294 	if (ret < 0)
295 		return ret;
296 
297 	if (ret & DW_RXFIFO_ERR) {
298 		xpcs_warn(xpcs, state, "FIFO fault condition detected!\n");
299 		return -EFAULT;
300 	}
301 
302 	ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_PCS_10GBRT_STAT1);
303 	if (ret < 0)
304 		return ret;
305 
306 	if (!(ret & MDIO_PCS_10GBRT_STAT1_BLKLK))
307 		xpcs_warn(xpcs, state, "Link is not locked!\n");
308 
309 	ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_PCS_10GBRT_STAT2);
310 	if (ret < 0)
311 		return ret;
312 
313 	if (ret & MDIO_PCS_10GBRT_STAT2_ERR) {
314 		xpcs_warn(xpcs, state, "Link has errors!\n");
315 		return -EFAULT;
316 	}
317 
318 	return 0;
319 }
320 
321 static void xpcs_config_usxgmii(struct dw_xpcs *xpcs, int speed)
322 {
323 	int ret, speed_sel;
324 
325 	switch (speed) {
326 	case SPEED_10:
327 		speed_sel = DW_USXGMII_10;
328 		break;
329 	case SPEED_100:
330 		speed_sel = DW_USXGMII_100;
331 		break;
332 	case SPEED_1000:
333 		speed_sel = DW_USXGMII_1000;
334 		break;
335 	case SPEED_2500:
336 		speed_sel = DW_USXGMII_2500;
337 		break;
338 	case SPEED_5000:
339 		speed_sel = DW_USXGMII_5000;
340 		break;
341 	case SPEED_10000:
342 		speed_sel = DW_USXGMII_10000;
343 		break;
344 	default:
345 		/* Nothing to do here */
346 		return;
347 	}
348 
349 	ret = xpcs_read_vpcs(xpcs, MDIO_CTRL1);
350 	if (ret < 0)
351 		goto out;
352 
353 	ret = xpcs_write_vpcs(xpcs, MDIO_CTRL1, ret | DW_USXGMII_EN);
354 	if (ret < 0)
355 		goto out;
356 
357 	ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1);
358 	if (ret < 0)
359 		goto out;
360 
361 	ret &= ~DW_USXGMII_SS_MASK;
362 	ret |= speed_sel | DW_USXGMII_FULL;
363 
364 	ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, ret);
365 	if (ret < 0)
366 		goto out;
367 
368 	ret = xpcs_read_vpcs(xpcs, MDIO_CTRL1);
369 	if (ret < 0)
370 		goto out;
371 
372 	ret = xpcs_write_vpcs(xpcs, MDIO_CTRL1, ret | DW_USXGMII_RST);
373 	if (ret < 0)
374 		goto out;
375 
376 	return;
377 
378 out:
379 	pr_err("%s: XPCS access returned %pe\n", __func__, ERR_PTR(ret));
380 }
381 
382 static int _xpcs_config_aneg_c73(struct dw_xpcs *xpcs,
383 				 const struct xpcs_compat *compat)
384 {
385 	int ret, adv;
386 
387 	/* By default, in USXGMII mode XPCS operates at 10G baud and
388 	 * replicates data to achieve lower speeds. Hereby, in this
389 	 * default configuration we need to advertise all supported
390 	 * modes and not only the ones we want to use.
391 	 */
392 
393 	/* SR_AN_ADV3 */
394 	adv = 0;
395 	if (xpcs_linkmode_supported(compat, 2500baseX_Full))
396 		adv |= DW_C73_2500KX;
397 
398 	/* TODO: 5000baseKR */
399 
400 	ret = xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV3, adv);
401 	if (ret < 0)
402 		return ret;
403 
404 	/* SR_AN_ADV2 */
405 	adv = 0;
406 	if (xpcs_linkmode_supported(compat, 1000baseKX_Full))
407 		adv |= DW_C73_1000KX;
408 	if (xpcs_linkmode_supported(compat, 10000baseKX4_Full))
409 		adv |= DW_C73_10000KX4;
410 	if (xpcs_linkmode_supported(compat, 10000baseKR_Full))
411 		adv |= DW_C73_10000KR;
412 
413 	ret = xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV2, adv);
414 	if (ret < 0)
415 		return ret;
416 
417 	/* SR_AN_ADV1 */
418 	adv = DW_C73_AN_ADV_SF;
419 	if (xpcs_linkmode_supported(compat, Pause))
420 		adv |= DW_C73_PAUSE;
421 	if (xpcs_linkmode_supported(compat, Asym_Pause))
422 		adv |= DW_C73_ASYM_PAUSE;
423 
424 	return xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV1, adv);
425 }
426 
427 static int xpcs_config_aneg_c73(struct dw_xpcs *xpcs,
428 				const struct xpcs_compat *compat)
429 {
430 	int ret;
431 
432 	ret = _xpcs_config_aneg_c73(xpcs, compat);
433 	if (ret < 0)
434 		return ret;
435 
436 	ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_CTRL1);
437 	if (ret < 0)
438 		return ret;
439 
440 	ret |= MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART;
441 
442 	return xpcs_write(xpcs, MDIO_MMD_AN, MDIO_CTRL1, ret);
443 }
444 
445 static int xpcs_aneg_done_c73(struct dw_xpcs *xpcs,
446 			      struct phylink_link_state *state,
447 			      const struct xpcs_compat *compat, u16 an_stat1)
448 {
449 	int ret;
450 
451 	if (an_stat1 & MDIO_AN_STAT1_COMPLETE) {
452 		ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_AN_LPA);
453 		if (ret < 0)
454 			return ret;
455 
456 		/* Check if Aneg outcome is valid */
457 		if (!(ret & DW_C73_AN_ADV_SF)) {
458 			xpcs_config_aneg_c73(xpcs, compat);
459 			return 0;
460 		}
461 
462 		return 1;
463 	}
464 
465 	return 0;
466 }
467 
468 static int xpcs_read_lpa_c73(struct dw_xpcs *xpcs,
469 			     struct phylink_link_state *state, u16 an_stat1)
470 {
471 	u16 lpa[3];
472 	int i, ret;
473 
474 	if (!(an_stat1 & MDIO_AN_STAT1_LPABLE)) {
475 		phylink_clear(state->lp_advertising, Autoneg);
476 		return 0;
477 	}
478 
479 	phylink_set(state->lp_advertising, Autoneg);
480 
481 	/* Read Clause 73 link partner advertisement */
482 	for (i = ARRAY_SIZE(lpa); --i >= 0; ) {
483 		ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_AN_LPA + i);
484 		if (ret < 0)
485 			return ret;
486 
487 		lpa[i] = ret;
488 	}
489 
490 	mii_c73_mod_linkmode(state->lp_advertising, lpa);
491 
492 	return 0;
493 }
494 
495 static int xpcs_get_max_xlgmii_speed(struct dw_xpcs *xpcs,
496 				     struct phylink_link_state *state)
497 {
498 	unsigned long *adv = state->advertising;
499 	int speed = SPEED_UNKNOWN;
500 	int bit;
501 
502 	for_each_set_bit(bit, adv, __ETHTOOL_LINK_MODE_MASK_NBITS) {
503 		int new_speed = SPEED_UNKNOWN;
504 
505 		switch (bit) {
506 		case ETHTOOL_LINK_MODE_25000baseCR_Full_BIT:
507 		case ETHTOOL_LINK_MODE_25000baseKR_Full_BIT:
508 		case ETHTOOL_LINK_MODE_25000baseSR_Full_BIT:
509 			new_speed = SPEED_25000;
510 			break;
511 		case ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT:
512 		case ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT:
513 		case ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT:
514 		case ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT:
515 			new_speed = SPEED_40000;
516 			break;
517 		case ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT:
518 		case ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT:
519 		case ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT:
520 		case ETHTOOL_LINK_MODE_50000baseKR_Full_BIT:
521 		case ETHTOOL_LINK_MODE_50000baseSR_Full_BIT:
522 		case ETHTOOL_LINK_MODE_50000baseCR_Full_BIT:
523 		case ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT:
524 		case ETHTOOL_LINK_MODE_50000baseDR_Full_BIT:
525 			new_speed = SPEED_50000;
526 			break;
527 		case ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT:
528 		case ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT:
529 		case ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT:
530 		case ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT:
531 		case ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT:
532 		case ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT:
533 		case ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT:
534 		case ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT:
535 		case ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT:
536 			new_speed = SPEED_100000;
537 			break;
538 		default:
539 			continue;
540 		}
541 
542 		if (new_speed > speed)
543 			speed = new_speed;
544 	}
545 
546 	return speed;
547 }
548 
549 static void xpcs_resolve_pma(struct dw_xpcs *xpcs,
550 			     struct phylink_link_state *state)
551 {
552 	state->pause = MLO_PAUSE_TX | MLO_PAUSE_RX;
553 	state->duplex = DUPLEX_FULL;
554 
555 	switch (state->interface) {
556 	case PHY_INTERFACE_MODE_10GKR:
557 		state->speed = SPEED_10000;
558 		break;
559 	case PHY_INTERFACE_MODE_XLGMII:
560 		state->speed = xpcs_get_max_xlgmii_speed(xpcs, state);
561 		break;
562 	default:
563 		state->speed = SPEED_UNKNOWN;
564 		break;
565 	}
566 }
567 
568 static int xpcs_validate(struct phylink_pcs *pcs, unsigned long *supported,
569 			 const struct phylink_link_state *state)
570 {
571 	__ETHTOOL_DECLARE_LINK_MODE_MASK(xpcs_supported) = { 0, };
572 	const struct xpcs_compat *compat;
573 	struct dw_xpcs *xpcs;
574 	int i;
575 
576 	xpcs = phylink_pcs_to_xpcs(pcs);
577 	compat = xpcs_find_compat(xpcs->id, state->interface);
578 
579 	/* Populate the supported link modes for this PHY interface type.
580 	 * FIXME: what about the port modes and autoneg bit? This masks
581 	 * all those away.
582 	 */
583 	if (compat)
584 		for (i = 0; compat->supported[i] != __ETHTOOL_LINK_MODE_MASK_NBITS; i++)
585 			set_bit(compat->supported[i], xpcs_supported);
586 
587 	linkmode_and(supported, supported, xpcs_supported);
588 
589 	return 0;
590 }
591 
592 void xpcs_get_interfaces(struct dw_xpcs *xpcs, unsigned long *interfaces)
593 {
594 	int i, j;
595 
596 	for (i = 0; i < DW_XPCS_INTERFACE_MAX; i++) {
597 		const struct xpcs_compat *compat = &xpcs->id->compat[i];
598 
599 		for (j = 0; j < compat->num_interfaces; j++)
600 			if (compat->interface[j] < PHY_INTERFACE_MODE_MAX)
601 				__set_bit(compat->interface[j], interfaces);
602 	}
603 }
604 EXPORT_SYMBOL_GPL(xpcs_get_interfaces);
605 
606 int xpcs_config_eee(struct dw_xpcs *xpcs, int mult_fact_100ns, int enable)
607 {
608 	int ret;
609 
610 	ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL0);
611 	if (ret < 0)
612 		return ret;
613 
614 	if (enable) {
615 	/* Enable EEE */
616 		ret = DW_VR_MII_EEE_LTX_EN | DW_VR_MII_EEE_LRX_EN |
617 		      DW_VR_MII_EEE_TX_QUIET_EN | DW_VR_MII_EEE_RX_QUIET_EN |
618 		      DW_VR_MII_EEE_TX_EN_CTRL | DW_VR_MII_EEE_RX_EN_CTRL |
619 		      mult_fact_100ns << DW_VR_MII_EEE_MULT_FACT_100NS_SHIFT;
620 	} else {
621 		ret &= ~(DW_VR_MII_EEE_LTX_EN | DW_VR_MII_EEE_LRX_EN |
622 		       DW_VR_MII_EEE_TX_QUIET_EN | DW_VR_MII_EEE_RX_QUIET_EN |
623 		       DW_VR_MII_EEE_TX_EN_CTRL | DW_VR_MII_EEE_RX_EN_CTRL |
624 		       DW_VR_MII_EEE_MULT_FACT_100NS);
625 	}
626 
627 	ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL0, ret);
628 	if (ret < 0)
629 		return ret;
630 
631 	ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL1);
632 	if (ret < 0)
633 		return ret;
634 
635 	if (enable)
636 		ret |= DW_VR_MII_EEE_TRN_LPI;
637 	else
638 		ret &= ~DW_VR_MII_EEE_TRN_LPI;
639 
640 	return xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL1, ret);
641 }
642 EXPORT_SYMBOL_GPL(xpcs_config_eee);
643 
644 static int xpcs_config_aneg_c37_sgmii(struct dw_xpcs *xpcs, unsigned int mode)
645 {
646 	int ret, mdio_ctrl;
647 
648 	/* For AN for C37 SGMII mode, the settings are :-
649 	 * 1) VR_MII_MMD_CTRL Bit(12) [AN_ENABLE] = 0b (Disable SGMII AN in case
650 	      it is already enabled)
651 	 * 2) VR_MII_AN_CTRL Bit(2:1)[PCS_MODE] = 10b (SGMII AN)
652 	 * 3) VR_MII_AN_CTRL Bit(3) [TX_CONFIG] = 0b (MAC side SGMII)
653 	 *    DW xPCS used with DW EQoS MAC is always MAC side SGMII.
654 	 * 4) VR_MII_DIG_CTRL1 Bit(9) [MAC_AUTO_SW] = 1b (Automatic
655 	 *    speed/duplex mode change by HW after SGMII AN complete)
656 	 * 5) VR_MII_MMD_CTRL Bit(12) [AN_ENABLE] = 1b (Enable SGMII AN)
657 	 *
658 	 * Note: Since it is MAC side SGMII, there is no need to set
659 	 *	 SR_MII_AN_ADV. MAC side SGMII receives AN Tx Config from
660 	 *	 PHY about the link state change after C28 AN is completed
661 	 *	 between PHY and Link Partner. There is also no need to
662 	 *	 trigger AN restart for MAC-side SGMII.
663 	 */
664 	mdio_ctrl = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL);
665 	if (mdio_ctrl < 0)
666 		return mdio_ctrl;
667 
668 	if (mdio_ctrl & AN_CL37_EN) {
669 		ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL,
670 				 mdio_ctrl & ~AN_CL37_EN);
671 		if (ret < 0)
672 			return ret;
673 	}
674 
675 	ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL);
676 	if (ret < 0)
677 		return ret;
678 
679 	ret &= ~(DW_VR_MII_PCS_MODE_MASK | DW_VR_MII_TX_CONFIG_MASK);
680 	ret |= (DW_VR_MII_PCS_MODE_C37_SGMII <<
681 		DW_VR_MII_AN_CTRL_PCS_MODE_SHIFT &
682 		DW_VR_MII_PCS_MODE_MASK);
683 	ret |= (DW_VR_MII_TX_CONFIG_MAC_SIDE_SGMII <<
684 		DW_VR_MII_AN_CTRL_TX_CONFIG_SHIFT &
685 		DW_VR_MII_TX_CONFIG_MASK);
686 	ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL, ret);
687 	if (ret < 0)
688 		return ret;
689 
690 	ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1);
691 	if (ret < 0)
692 		return ret;
693 
694 	if (phylink_autoneg_inband(mode))
695 		ret |= DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW;
696 	else
697 		ret &= ~DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW;
698 
699 	ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1, ret);
700 	if (ret < 0)
701 		return ret;
702 
703 	if (phylink_autoneg_inband(mode))
704 		ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL,
705 				 mdio_ctrl | AN_CL37_EN);
706 
707 	return ret;
708 }
709 
710 static int xpcs_config_aneg_c37_1000basex(struct dw_xpcs *xpcs, unsigned int mode,
711 					  const unsigned long *advertising)
712 {
713 	phy_interface_t interface = PHY_INTERFACE_MODE_1000BASEX;
714 	int ret, mdio_ctrl, adv;
715 	bool changed = 0;
716 
717 	/* According to Chap 7.12, to set 1000BASE-X C37 AN, AN must
718 	 * be disabled first:-
719 	 * 1) VR_MII_MMD_CTRL Bit(12)[AN_ENABLE] = 0b
720 	 * 2) VR_MII_AN_CTRL Bit(2:1)[PCS_MODE] = 00b (1000BASE-X C37)
721 	 */
722 	mdio_ctrl = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL);
723 	if (mdio_ctrl < 0)
724 		return mdio_ctrl;
725 
726 	if (mdio_ctrl & AN_CL37_EN) {
727 		ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL,
728 				 mdio_ctrl & ~AN_CL37_EN);
729 		if (ret < 0)
730 			return ret;
731 	}
732 
733 	ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL);
734 	if (ret < 0)
735 		return ret;
736 
737 	ret &= ~DW_VR_MII_PCS_MODE_MASK;
738 	ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL, ret);
739 	if (ret < 0)
740 		return ret;
741 
742 	/* Check for advertising changes and update the C45 MII ADV
743 	 * register accordingly.
744 	 */
745 	adv = phylink_mii_c22_pcs_encode_advertisement(interface,
746 						       advertising);
747 	if (adv >= 0) {
748 		ret = xpcs_modify_changed(xpcs, MDIO_MMD_VEND2,
749 					  MII_ADVERTISE, 0xffff, adv);
750 		if (ret < 0)
751 			return ret;
752 
753 		changed = ret;
754 	}
755 
756 	/* Clear CL37 AN complete status */
757 	ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS, 0);
758 	if (ret < 0)
759 		return ret;
760 
761 	if (phylink_autoneg_inband(mode) &&
762 	    linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, advertising)) {
763 		ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL,
764 				 mdio_ctrl | AN_CL37_EN);
765 		if (ret < 0)
766 			return ret;
767 	}
768 
769 	return changed;
770 }
771 
772 static int xpcs_config_2500basex(struct dw_xpcs *xpcs)
773 {
774 	int ret;
775 
776 	ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1);
777 	if (ret < 0)
778 		return ret;
779 	ret |= DW_VR_MII_DIG_CTRL1_2G5_EN;
780 	ret &= ~DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW;
781 	ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1, ret);
782 	if (ret < 0)
783 		return ret;
784 
785 	ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL);
786 	if (ret < 0)
787 		return ret;
788 	ret &= ~AN_CL37_EN;
789 	ret |= SGMII_SPEED_SS6;
790 	ret &= ~SGMII_SPEED_SS13;
791 	return xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL, ret);
792 }
793 
794 int xpcs_do_config(struct dw_xpcs *xpcs, phy_interface_t interface,
795 		   unsigned int mode, const unsigned long *advertising)
796 {
797 	const struct xpcs_compat *compat;
798 	int ret;
799 
800 	compat = xpcs_find_compat(xpcs->id, interface);
801 	if (!compat)
802 		return -ENODEV;
803 
804 	switch (compat->an_mode) {
805 	case DW_AN_C73:
806 		if (test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, advertising)) {
807 			ret = xpcs_config_aneg_c73(xpcs, compat);
808 			if (ret)
809 				return ret;
810 		}
811 		break;
812 	case DW_AN_C37_SGMII:
813 		ret = xpcs_config_aneg_c37_sgmii(xpcs, mode);
814 		if (ret)
815 			return ret;
816 		break;
817 	case DW_AN_C37_1000BASEX:
818 		ret = xpcs_config_aneg_c37_1000basex(xpcs, mode,
819 						     advertising);
820 		if (ret)
821 			return ret;
822 		break;
823 	case DW_2500BASEX:
824 		ret = xpcs_config_2500basex(xpcs);
825 		if (ret)
826 			return ret;
827 		break;
828 	default:
829 		return -1;
830 	}
831 
832 	if (compat->pma_config) {
833 		ret = compat->pma_config(xpcs);
834 		if (ret)
835 			return ret;
836 	}
837 
838 	return 0;
839 }
840 EXPORT_SYMBOL_GPL(xpcs_do_config);
841 
842 static int xpcs_config(struct phylink_pcs *pcs, unsigned int mode,
843 		       phy_interface_t interface,
844 		       const unsigned long *advertising,
845 		       bool permit_pause_to_mac)
846 {
847 	struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs);
848 
849 	return xpcs_do_config(xpcs, interface, mode, advertising);
850 }
851 
852 static int xpcs_get_state_c73(struct dw_xpcs *xpcs,
853 			      struct phylink_link_state *state,
854 			      const struct xpcs_compat *compat)
855 {
856 	bool an_enabled;
857 	int pcs_stat1;
858 	int an_stat1;
859 	int ret;
860 
861 	/* The link status bit is latching-low, so it is important to
862 	 * avoid unnecessary re-reads of this register to avoid missing
863 	 * a link-down event.
864 	 */
865 	pcs_stat1 = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_STAT1);
866 	if (pcs_stat1 < 0) {
867 		state->link = false;
868 		return pcs_stat1;
869 	}
870 
871 	/* Link needs to be read first ... */
872 	state->link = !!(pcs_stat1 & MDIO_STAT1_LSTATUS);
873 
874 	/* ... and then we check the faults. */
875 	ret = xpcs_read_fault_c73(xpcs, state, pcs_stat1);
876 	if (ret) {
877 		ret = xpcs_soft_reset(xpcs, compat);
878 		if (ret)
879 			return ret;
880 
881 		state->link = 0;
882 
883 		return xpcs_do_config(xpcs, state->interface, MLO_AN_INBAND, NULL);
884 	}
885 
886 	/* There is no point doing anything else if the link is down. */
887 	if (!state->link)
888 		return 0;
889 
890 	an_enabled = linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
891 				       state->advertising);
892 	if (an_enabled) {
893 		/* The link status bit is latching-low, so it is important to
894 		 * avoid unnecessary re-reads of this register to avoid missing
895 		 * a link-down event.
896 		 */
897 		an_stat1 = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_STAT1);
898 		if (an_stat1 < 0) {
899 			state->link = false;
900 			return an_stat1;
901 		}
902 
903 		state->an_complete = xpcs_aneg_done_c73(xpcs, state, compat,
904 							an_stat1);
905 		if (!state->an_complete) {
906 			state->link = false;
907 			return 0;
908 		}
909 
910 		ret = xpcs_read_lpa_c73(xpcs, state, an_stat1);
911 		if (ret < 0) {
912 			state->link = false;
913 			return ret;
914 		}
915 
916 		phylink_resolve_c73(state);
917 	} else {
918 		xpcs_resolve_pma(xpcs, state);
919 	}
920 
921 	return 0;
922 }
923 
924 static int xpcs_get_state_c37_sgmii(struct dw_xpcs *xpcs,
925 				    struct phylink_link_state *state)
926 {
927 	int ret;
928 
929 	/* Reset link_state */
930 	state->link = false;
931 	state->speed = SPEED_UNKNOWN;
932 	state->duplex = DUPLEX_UNKNOWN;
933 	state->pause = 0;
934 
935 	/* For C37 SGMII mode, we check DW_VR_MII_AN_INTR_STS for link
936 	 * status, speed and duplex.
937 	 */
938 	ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS);
939 	if (ret < 0)
940 		return ret;
941 
942 	if (ret & DW_VR_MII_C37_ANSGM_SP_LNKSTS) {
943 		int speed_value;
944 
945 		state->link = true;
946 
947 		speed_value = (ret & DW_VR_MII_AN_STS_C37_ANSGM_SP) >>
948 			      DW_VR_MII_AN_STS_C37_ANSGM_SP_SHIFT;
949 		if (speed_value == DW_VR_MII_C37_ANSGM_SP_1000)
950 			state->speed = SPEED_1000;
951 		else if (speed_value == DW_VR_MII_C37_ANSGM_SP_100)
952 			state->speed = SPEED_100;
953 		else
954 			state->speed = SPEED_10;
955 
956 		if (ret & DW_VR_MII_AN_STS_C37_ANSGM_FD)
957 			state->duplex = DUPLEX_FULL;
958 		else
959 			state->duplex = DUPLEX_HALF;
960 	}
961 
962 	return 0;
963 }
964 
965 static int xpcs_get_state_c37_1000basex(struct dw_xpcs *xpcs,
966 					struct phylink_link_state *state)
967 {
968 	int lpa, bmsr;
969 
970 	if (linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
971 			      state->advertising)) {
972 		/* Reset link state */
973 		state->link = false;
974 
975 		lpa = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_LPA);
976 		if (lpa < 0 || lpa & LPA_RFAULT)
977 			return lpa;
978 
979 		bmsr = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_BMSR);
980 		if (bmsr < 0)
981 			return bmsr;
982 
983 		phylink_mii_c22_pcs_decode_state(state, bmsr, lpa);
984 	}
985 
986 	return 0;
987 }
988 
989 static void xpcs_get_state(struct phylink_pcs *pcs,
990 			   struct phylink_link_state *state)
991 {
992 	struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs);
993 	const struct xpcs_compat *compat;
994 	int ret;
995 
996 	compat = xpcs_find_compat(xpcs->id, state->interface);
997 	if (!compat)
998 		return;
999 
1000 	switch (compat->an_mode) {
1001 	case DW_AN_C73:
1002 		ret = xpcs_get_state_c73(xpcs, state, compat);
1003 		if (ret) {
1004 			pr_err("xpcs_get_state_c73 returned %pe\n",
1005 			       ERR_PTR(ret));
1006 			return;
1007 		}
1008 		break;
1009 	case DW_AN_C37_SGMII:
1010 		ret = xpcs_get_state_c37_sgmii(xpcs, state);
1011 		if (ret) {
1012 			pr_err("xpcs_get_state_c37_sgmii returned %pe\n",
1013 			       ERR_PTR(ret));
1014 		}
1015 		break;
1016 	case DW_AN_C37_1000BASEX:
1017 		ret = xpcs_get_state_c37_1000basex(xpcs, state);
1018 		if (ret) {
1019 			pr_err("xpcs_get_state_c37_1000basex returned %pe\n",
1020 			       ERR_PTR(ret));
1021 		}
1022 		break;
1023 	default:
1024 		return;
1025 	}
1026 }
1027 
1028 static void xpcs_link_up_sgmii(struct dw_xpcs *xpcs, unsigned int mode,
1029 			       int speed, int duplex)
1030 {
1031 	int val, ret;
1032 
1033 	if (phylink_autoneg_inband(mode))
1034 		return;
1035 
1036 	val = mii_bmcr_encode_fixed(speed, duplex);
1037 	ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, val);
1038 	if (ret)
1039 		pr_err("%s: xpcs_write returned %pe\n", __func__, ERR_PTR(ret));
1040 }
1041 
1042 static void xpcs_link_up_1000basex(struct dw_xpcs *xpcs, unsigned int mode,
1043 				   int speed, int duplex)
1044 {
1045 	int val, ret;
1046 
1047 	if (phylink_autoneg_inband(mode))
1048 		return;
1049 
1050 	switch (speed) {
1051 	case SPEED_1000:
1052 		val = BMCR_SPEED1000;
1053 		break;
1054 	case SPEED_100:
1055 	case SPEED_10:
1056 	default:
1057 		pr_err("%s: speed = %d\n", __func__, speed);
1058 		return;
1059 	}
1060 
1061 	if (duplex == DUPLEX_FULL)
1062 		val |= BMCR_FULLDPLX;
1063 	else
1064 		pr_err("%s: half duplex not supported\n", __func__);
1065 
1066 	ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, val);
1067 	if (ret)
1068 		pr_err("%s: xpcs_write returned %pe\n", __func__, ERR_PTR(ret));
1069 }
1070 
1071 void xpcs_link_up(struct phylink_pcs *pcs, unsigned int mode,
1072 		  phy_interface_t interface, int speed, int duplex)
1073 {
1074 	struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs);
1075 
1076 	if (interface == PHY_INTERFACE_MODE_USXGMII)
1077 		return xpcs_config_usxgmii(xpcs, speed);
1078 	if (interface == PHY_INTERFACE_MODE_SGMII)
1079 		return xpcs_link_up_sgmii(xpcs, mode, speed, duplex);
1080 	if (interface == PHY_INTERFACE_MODE_1000BASEX)
1081 		return xpcs_link_up_1000basex(xpcs, mode, speed, duplex);
1082 }
1083 EXPORT_SYMBOL_GPL(xpcs_link_up);
1084 
1085 static void xpcs_an_restart(struct phylink_pcs *pcs)
1086 {
1087 	struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs);
1088 	int ret;
1089 
1090 	ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1);
1091 	if (ret >= 0) {
1092 		ret |= BMCR_ANRESTART;
1093 		xpcs_write(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, ret);
1094 	}
1095 }
1096 
1097 static u32 xpcs_get_id(struct dw_xpcs *xpcs)
1098 {
1099 	int ret;
1100 	u32 id;
1101 
1102 	/* First, search C73 PCS using PCS MMD */
1103 	ret = xpcs_read(xpcs, MDIO_MMD_PCS, MII_PHYSID1);
1104 	if (ret < 0)
1105 		return 0xffffffff;
1106 
1107 	id = ret << 16;
1108 
1109 	ret = xpcs_read(xpcs, MDIO_MMD_PCS, MII_PHYSID2);
1110 	if (ret < 0)
1111 		return 0xffffffff;
1112 
1113 	/* If Device IDs are not all zeros or all ones,
1114 	 * we found C73 AN-type device
1115 	 */
1116 	if ((id | ret) && (id | ret) != 0xffffffff)
1117 		return id | ret;
1118 
1119 	/* Next, search C37 PCS using Vendor-Specific MII MMD */
1120 	ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_PHYSID1);
1121 	if (ret < 0)
1122 		return 0xffffffff;
1123 
1124 	id = ret << 16;
1125 
1126 	ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_PHYSID2);
1127 	if (ret < 0)
1128 		return 0xffffffff;
1129 
1130 	/* If Device IDs are not all zeros, we found C37 AN-type device */
1131 	if (id | ret)
1132 		return id | ret;
1133 
1134 	return 0xffffffff;
1135 }
1136 
1137 static const struct xpcs_compat synopsys_xpcs_compat[DW_XPCS_INTERFACE_MAX] = {
1138 	[DW_XPCS_USXGMII] = {
1139 		.supported = xpcs_usxgmii_features,
1140 		.interface = xpcs_usxgmii_interfaces,
1141 		.num_interfaces = ARRAY_SIZE(xpcs_usxgmii_interfaces),
1142 		.an_mode = DW_AN_C73,
1143 	},
1144 	[DW_XPCS_10GKR] = {
1145 		.supported = xpcs_10gkr_features,
1146 		.interface = xpcs_10gkr_interfaces,
1147 		.num_interfaces = ARRAY_SIZE(xpcs_10gkr_interfaces),
1148 		.an_mode = DW_AN_C73,
1149 	},
1150 	[DW_XPCS_XLGMII] = {
1151 		.supported = xpcs_xlgmii_features,
1152 		.interface = xpcs_xlgmii_interfaces,
1153 		.num_interfaces = ARRAY_SIZE(xpcs_xlgmii_interfaces),
1154 		.an_mode = DW_AN_C73,
1155 	},
1156 	[DW_XPCS_SGMII] = {
1157 		.supported = xpcs_sgmii_features,
1158 		.interface = xpcs_sgmii_interfaces,
1159 		.num_interfaces = ARRAY_SIZE(xpcs_sgmii_interfaces),
1160 		.an_mode = DW_AN_C37_SGMII,
1161 	},
1162 	[DW_XPCS_1000BASEX] = {
1163 		.supported = xpcs_1000basex_features,
1164 		.interface = xpcs_1000basex_interfaces,
1165 		.num_interfaces = ARRAY_SIZE(xpcs_1000basex_interfaces),
1166 		.an_mode = DW_AN_C37_1000BASEX,
1167 	},
1168 	[DW_XPCS_2500BASEX] = {
1169 		.supported = xpcs_2500basex_features,
1170 		.interface = xpcs_2500basex_interfaces,
1171 		.num_interfaces = ARRAY_SIZE(xpcs_2500basex_interfaces),
1172 		.an_mode = DW_2500BASEX,
1173 	},
1174 };
1175 
1176 static const struct xpcs_compat nxp_sja1105_xpcs_compat[DW_XPCS_INTERFACE_MAX] = {
1177 	[DW_XPCS_SGMII] = {
1178 		.supported = xpcs_sgmii_features,
1179 		.interface = xpcs_sgmii_interfaces,
1180 		.num_interfaces = ARRAY_SIZE(xpcs_sgmii_interfaces),
1181 		.an_mode = DW_AN_C37_SGMII,
1182 		.pma_config = nxp_sja1105_sgmii_pma_config,
1183 	},
1184 };
1185 
1186 static const struct xpcs_compat nxp_sja1110_xpcs_compat[DW_XPCS_INTERFACE_MAX] = {
1187 	[DW_XPCS_SGMII] = {
1188 		.supported = xpcs_sgmii_features,
1189 		.interface = xpcs_sgmii_interfaces,
1190 		.num_interfaces = ARRAY_SIZE(xpcs_sgmii_interfaces),
1191 		.an_mode = DW_AN_C37_SGMII,
1192 		.pma_config = nxp_sja1110_sgmii_pma_config,
1193 	},
1194 	[DW_XPCS_2500BASEX] = {
1195 		.supported = xpcs_2500basex_features,
1196 		.interface = xpcs_2500basex_interfaces,
1197 		.num_interfaces = ARRAY_SIZE(xpcs_2500basex_interfaces),
1198 		.an_mode = DW_2500BASEX,
1199 		.pma_config = nxp_sja1110_2500basex_pma_config,
1200 	},
1201 };
1202 
1203 static const struct xpcs_id xpcs_id_list[] = {
1204 	{
1205 		.id = SYNOPSYS_XPCS_ID,
1206 		.mask = SYNOPSYS_XPCS_MASK,
1207 		.compat = synopsys_xpcs_compat,
1208 	}, {
1209 		.id = NXP_SJA1105_XPCS_ID,
1210 		.mask = SYNOPSYS_XPCS_MASK,
1211 		.compat = nxp_sja1105_xpcs_compat,
1212 	}, {
1213 		.id = NXP_SJA1110_XPCS_ID,
1214 		.mask = SYNOPSYS_XPCS_MASK,
1215 		.compat = nxp_sja1110_xpcs_compat,
1216 	},
1217 };
1218 
1219 static const struct phylink_pcs_ops xpcs_phylink_ops = {
1220 	.pcs_validate = xpcs_validate,
1221 	.pcs_config = xpcs_config,
1222 	.pcs_get_state = xpcs_get_state,
1223 	.pcs_an_restart = xpcs_an_restart,
1224 	.pcs_link_up = xpcs_link_up,
1225 };
1226 
1227 struct dw_xpcs *xpcs_create(struct mdio_device *mdiodev,
1228 			    phy_interface_t interface)
1229 {
1230 	struct dw_xpcs *xpcs;
1231 	u32 xpcs_id;
1232 	int i, ret;
1233 
1234 	xpcs = kzalloc(sizeof(*xpcs), GFP_KERNEL);
1235 	if (!xpcs)
1236 		return ERR_PTR(-ENOMEM);
1237 
1238 	mdio_device_get(mdiodev);
1239 	xpcs->mdiodev = mdiodev;
1240 
1241 	xpcs_id = xpcs_get_id(xpcs);
1242 
1243 	for (i = 0; i < ARRAY_SIZE(xpcs_id_list); i++) {
1244 		const struct xpcs_id *entry = &xpcs_id_list[i];
1245 		const struct xpcs_compat *compat;
1246 
1247 		if ((xpcs_id & entry->mask) != entry->id)
1248 			continue;
1249 
1250 		xpcs->id = entry;
1251 
1252 		compat = xpcs_find_compat(entry, interface);
1253 		if (!compat) {
1254 			ret = -ENODEV;
1255 			goto out;
1256 		}
1257 
1258 		xpcs->pcs.ops = &xpcs_phylink_ops;
1259 		xpcs->pcs.poll = true;
1260 
1261 		ret = xpcs_soft_reset(xpcs, compat);
1262 		if (ret)
1263 			goto out;
1264 
1265 		return xpcs;
1266 	}
1267 
1268 	ret = -ENODEV;
1269 
1270 out:
1271 	mdio_device_put(mdiodev);
1272 	kfree(xpcs);
1273 
1274 	return ERR_PTR(ret);
1275 }
1276 EXPORT_SYMBOL_GPL(xpcs_create);
1277 
1278 void xpcs_destroy(struct dw_xpcs *xpcs)
1279 {
1280 	if (xpcs)
1281 		mdio_device_put(xpcs->mdiodev);
1282 	kfree(xpcs);
1283 }
1284 EXPORT_SYMBOL_GPL(xpcs_destroy);
1285 
1286 struct dw_xpcs *xpcs_create_mdiodev(struct mii_bus *bus, int addr,
1287 				    phy_interface_t interface)
1288 {
1289 	struct mdio_device *mdiodev;
1290 	struct dw_xpcs *xpcs;
1291 
1292 	mdiodev = mdio_device_create(bus, addr);
1293 	if (IS_ERR(mdiodev))
1294 		return ERR_CAST(mdiodev);
1295 
1296 	xpcs = xpcs_create(mdiodev, interface);
1297 
1298 	/* xpcs_create() has taken a refcount on the mdiodev if it was
1299 	 * successful. If xpcs_create() fails, this will free the mdio
1300 	 * device here. In any case, we don't need to hold our reference
1301 	 * anymore, and putting it here will allow mdio_device_put() in
1302 	 * xpcs_destroy() to automatically free the mdio device.
1303 	 */
1304 	mdio_device_put(mdiodev);
1305 
1306 	return xpcs;
1307 }
1308 EXPORT_SYMBOL_GPL(xpcs_create_mdiodev);
1309 
1310 MODULE_LICENSE("GPL v2");
1311